500 MILLION PARTS FROM 12000 MANUFACTURERS

DATASHEET SEARCH ENGINE

Top Results

Part Manufacturer Description Datasheet BUY
MSP430-3P-TOTAL-TP120210-DEVKT Texas Instruments SPI Development Kit visit Texas Instruments
MSP430-3P-TOTAL-TP280120-PPT Texas Instruments Cheetah SPI Host Adapter visit Texas Instruments
ADS8319IBDGSR Texas Instruments Precision 16-Bit SAR w/ SPI interface in MSOP-10 10-VSSOP -40 to 85 visit Texas Instruments
ADS8319IDGST Texas Instruments Precision 16-Bit SAR w/ SPI interface in MSOP-10 10-VSSOP -40 to 85 visit Texas Instruments Buy
ADS8319IBDGST Texas Instruments Precision 16-Bit SAR w/ SPI interface in MSOP-10 10-VSSOP -40 to 85 visit Texas Instruments Buy
ADS8319IDGSR Texas Instruments Precision 16-Bit SAR w/ SPI interface in MSOP-10 10-VSSOP -40 to 85 visit Texas Instruments

SPI to IEEE-488

Catalog Datasheet MFG & Type PDF Document Tags

8291 gpib

Abstract: intel d 8292 gpib Initialization of the Bus Responds to Service Requests (SRQ) Sends Remote Enable (REN), Allowing Instruments to Switch to Remote Control The 8292 GPIB Controller is a microprocessor-controlled chip designed to function with the 8291 GPIB Talk er/Listener to implement the full IEEE Standard 488 controller function , Control Seizure Prevents the Destruction of Any Data Transmission in Progress Connects with the 8291 to Form a Complete IEEE Standard 488 Interface Talker/Listener/Controller Complete IEEE Standard 488
-
OCR Scan

8291 gpib

Abstract: intel 8041A Transmission in Progress Connects with the 8291 to Form a Complete IEEE Standard 488 Interface Talker , with the 8291 GPIB Talk er/Listener to implement the full IEEE Standard 488 controller function , 8292 GPIB CONTROLLER Complete IEEE Standard 488 Controller Function Interface Clear (IFC) Sending Capability Allows Seizure of Bus Control and/or Initialization of the Bus Responds to Service Requests (SRQ) Sends Remote Enable (REN), Allowing Instruments to Switch to Remote Control Complete
-
OCR Scan

intel d 8293

Abstract: intel 8293 the 8292 when it is controller in charge. If true, SPI interrupt to the master will be generated , Transceivers to form a complete IEEE-488 Bus Interface for a microprocessor. The electrical interface is , d3 d2 d1 Do d7 d0 The Interrupt Mask Register Is used to enable features and to mask the SPI and , in CIDS. System Configuration The 8291 and 8292 must be interfaced to an IEEE-488 bus meeting a , SYC MODE 2 OPTB â'¢ IEEE-488 BUS -Vcc - Vcc . TO IEEE-488 ' BUS Figure 5. 8291, 8292, and 8293
-
OCR Scan

intel 8292

Abstract: INTEL 8041 charge. If true, SPI interrupt to the master will be generated. ATNI 22 I ATTENTION IN: Used by the 8292 , The Interrupt Mask Register is used to enable features and to mask the SPI and TCI interrupts. The , controller, it will remain in CIDS. System Configuration The 8291 and 8292 must be interfaced to an IEEE-488 , in tel 8292 GPIB CONTROLLER â  Complete IEEE Standard 488 Controller Function â  Interface ,   Responds to Service Requests (SRQ) â  Sends Remote Enable (REN), Allowing Instruments to Switch to Remote
-
OCR Scan

intel 8041A

Abstract: ) â  Connects with the 8291 to Form a Complete IEEE Standard 488 Interface Talker/Llstener , /Listener to implement the full IEEE Standard 488 controller function, including transfer control protocol , it is controller in charge. If true, SPI interrupt to the master will be generated. ATNI 22 , TCI The Interrupt Mask Register is used to enable fea­ tures and to mask the SPI and TCI , SPI Special Interrupt 8292 To Master Processor Interface Four different interrupts are
-
OCR Scan

4-20ma spi

Abstract: max1468 OSCILLATOR DSP C2D EEPROM MAX1468 SPI * Motorola, Inc. 0.001pF TEMP DIGITAL FILTER , . Maxim 112 GPIB ( IEEE-488 ) ( DAS ) 16 RS-232 PC GPIB Maxim / / 1. GPIB , Analog 1st-order resistor programmable 10mV/V to 30mV/V Current source* ­ Laser trim , Analog 16-bit DACs (selectable from 1 to 179 point temp compensation) 1mV/V to 40mV/V Current , 0.5V-4.5V, 0-5V, 2.5V ±2.5V Analog 16-bit DACs (selectable from 1 to 179 point temp compensation
Maxim Integrated Products
Original
MAX1455 MAX1475 MAX1450 MAX1452 MAX1457 MAX1458 4-20ma spi max1461 RTV SOT23 MAX1454 4-20ma to digital ADC maxim adc 16 bit MAX1458/MAX1459/MAX1478

hc335

Abstract: 1517P functionally and electrically equivalent to the Stratix III FPGA features. The combination of the Quartus® II , devices for high-volume production, provides a complete, low-risk design solution to meet your business , family is an alternative to the standard cell ASIC for low-cost, high-performance logic, digital signal , power Core logic performance up to double that of the Stratix III FPGA prototype Power , data sheet are design-dependent. Logic and DSP 2.7 to 7 million usable gates for both
Altera
Original
hc335 1517P WF484 HIII51001-3

intel d 8293

Abstract: intel 8293   On-chip Decoder for Mode Configuration â  Power Up/Power Down Protection to Prevent Disrupting the IEEE Bus â  Connects with the 8291A and 8292 to Form an IEEE Standard 488 Interface Talker/Listener/Controller with no Additional Components â  Only Two 8293's Required per QPIB Interface â  On Chip IEEE-488 , optb to ieee-488 bus - Vcc to ieee-488 bus Figure 9. 8291A and 8293 System Configuration 7-476 , ATN" EOI EOI" EOI2 ATNI IFCL CIC CLTH OPTA SYC OPTB MODE 2 TO ieee'488 BUS -Vss - Vcc
-
OCR Scan
intel d 8293 intel 8293 TTL 7479 IEEE 3 bus datas 7472 PIN DIAGRAM SPI to IEEE-488 IEEE-488 DATA10 AFN-00825C

8089 microprocessor block diagram

Abstract: 8089 intel microprocessor Architecture Diagram , 8080/85, 8086/88) to an IEEE Standard 488 Digital Interface Bus Programmable Data Transfer Rate , microprocessors to an IEEE Standard 488 Instrumentation Interface Bus. It implements all of the Standard , . This is to comply with some additions to the 1975 IEEE-488 Standard incorporated in the 1978 Standard , , IEEE 488 specifies negative logic on its 16 signal lines. Thus, the data is inverted once from D0-D7 to , listener functions as defined in IEEE-488. To use Mode 2 addressing the primary address must be loaded
-
OCR Scan
8089 microprocessor block diagram 8089 intel microprocessor Architecture Diagram intel 8292 8089 microprocessor pin diagram intel 8089 microprocessor Features 8089 microprocessor Features

EP3SGX

Abstract: DDR3 "application note" - EP3SE260 - 488 744 976 - Note to Table 1­2: (1) (2) (3) (4) The , , which provides the ability to turn on the performance where needed and turn down the power consumption , to deliver the industry's lowest power, high performance FPGAs. Specifically designed for ease of , to meet different application needs: The Stratix III L family provides balanced logic , with a common bank structure for vertical migration lend efficiency and flexibility to the high speed
Altera
Original
EP3SGX DDR3 "application note" EP3SE50 SIII51001-1

SPI to IEEE-488

Abstract: 8080 intel microprocessor pin diagram , 8051, 8080/85, 8086/88) to an IEEE Standard 488 Digital Interface Bus â  Programmable Data Transfer , version of the 8291 GPIB Talker/Listener designed to interface microprocessors to an IEEE Standard 488 , ninth data bit rather than as a control bit. This is to comply with some additions to the 1975 IEEE-488 , listener functions as defined in IEEE-488. To use Mode 2 addressing the primary address must be loaded , processed. The IEEE-488 Standard does not permit users to define their own commands, but upgrades of the
-
OCR Scan
8080 intel microprocessor pin diagram intel 8291A 8291 gpib intel 8291 8291A 8089 microprocessor architecture

MAX14522

Abstract: max1456 www.maxim-ic.com () www.maxim-ic.com/sensortips.htm * 1¥130/1 AV TO QU A FR ILABLE EE AL IFI ED CU ST O ME RS 112 16(DAS) PCGPIB(IEEE-488)RS , SPI EEPROM RISC (V) 5V
Maxim Integrated Products
Original
MAX1474 MAX1474SC70 MAX1462 MAX14522 max1456 max14622 MAX1452EVKIT MAX14680 max1477 SC70MAX1474 MAX1474RF MAX1457MAX1456 TCMAX1457MAX1456

intel 8291A

Abstract: 8089 microprocessor architecture , 8080/85, 8086/88) to an IEEE Standard 488 Digital Interface Bus â  Programmable Data Transfer Rate â , microprocessors to an fEEE Standard 488 Instrumentation Interface Bus. It implements ail of the Standard , data bit rather than as a control bit. This is to comply with some additions to the 1975 IEEE-488 , passed to the microprocessor. 3. All Controller messages must be sent via Intel's 8292. Table 3. IEEE 488 , extended talker and listener functions as defined in IEEE-488. To use Mode 2 addressing the primary address
-
OCR Scan
JST MSA using the 8292 gpib controller intel DOC intel 8257 interrupt controller Intel 8237 dma controller block diagram

using the 8292 gpib controller

Abstract: 8089 microprocessor architecture , 8080/85, 8086/88) to an IEEE Standard 488 Digital Interface Bus Programmable Data Transfer Rate , to interface microprocessors to an IEEE Standard 488 Instrumentation Interface Bus. It implements all , is to comply with some additions to the 1975 IEEE-488 Standard incorporated in the 1978 Standard. 2 , to the microprocessor. 3. All Controller messages must be sent via Intel's 8292. Table 3. IEEE 488 , functions as defined in IEEE-488. To use Mode 2 addressing the primary address must be loaded into the
-
OCR Scan
110B8 8291 Microprocessor 8048 microprocessors interface 8237 8048 intel microprocessor pin diagram interfacing of 8237 with 8086 30I08

uln2803 to drive 7 segment display

Abstract: working of 5 pen pc technology provide Interlaces to many Industry standard specifications. Many of the devices add key operational , functions, Address and Control Bus Extenders These devices are designed to extend the drive capabilities , Noninverting Inverting Hex 3-State Buffers/Inverters Ta = 0° to +75°C The noninverting MC8T97/MC6887 and , head and converting to a digital output. Magnetic Tape Sense Amplifier. Trace independent preamplifiers , ) Suffix/ Package P/738 MC3470, A MC34167 0 to + 70 P/707 MOTOROLA LINEAR/INTERFACE ICs DEVICE
-
OCR Scan
MC14495 MC14499 uln2803 to drive 7 segment display working of 5 pen pc technology 4 digit 7 segment LED display AM26L532 AM26L53 4-DIGIT 7-SEGMENT LED DISPLAY MC8T97/ MC6887 MC8T98/ MC6888 P/648 MC8T98/MC68880

KDS 16.000

Abstract: KDS 16.000MHz low-current operation. Transition from the Off to Idle mode occurs when RST is negated. Once in Idle, the SPI , Hibernate Crystal Reference Oscillator Off. (SPI not functional.) IC Responds to ATTN. Data is retained , (300 + 1/CLKO) µs 7, Bit 9 = 1 for frequencies of 1 MHz or less. (SPI not functional.) Responds to , the MC13192/MC13193, checks its status, and reads/writes data to the device through the 4-wire SPI , bursts and can extend to a greater number of bursts. 2. SPI Clock (SPICLK) - The host drives the SPICLK
Freescale Semiconductor
Original
QFN-32 MC13192 MC13193 HCS08 KDS 16.000 KDS 16.000MHz DSX321G kds DSX321G kds thermostats ZD00882 MC13192/D

4upg

Abstract: DSX321G is negated. Once in Idle, the SPI is active and is used to control the IC. Transition to Hibernate , Oscillator Off. (SPI not functional.) IC Responds to ATTN. Data is retained. Transition Time To or From Idle , Register (300 + 1/CLKO) µs 7, Bit 9 = 1 for frequencies of 1 MHz or less. (SPI not functional.) Responds to , , checks its status, and reads/writes data to the device through the 4-wire SPI port. The transceiver , extend to a greater number of bursts. 2. SPI Clock (SPICLK) - The host drives the SPICLK input to the
Freescale Semiconductor
Original
4upg
Abstract: dBm EVM - 20 31 250 -42 -44 35 - % dB kbps dBc dBc SPI Register 12 programmed to 0x00BC which sets output power to nominal (0 dBm typical). SPI Register 12 programmed to 0x00FC which , negated. Once in Idle, the SPI is active and is used to control the IC. Transition to Hibernate and Doze , . (SPI not functional.) IC Responds to ATTN. Data is retained. Transition Time To or From Idle 25 ms to , 1/CLKO) µs 7, Bit 9 = 1 for frequencies of 1 MHz or less. (SPI not functional.) Responds to Idle to Freescale Semiconductor
Original

KDS 16.000MHz

Abstract: KDS 16.000MHz crystal oscillator programmed to 0x00BC which sets output power to nominal (0 dBm typical). SPI Register 12 programmed to 0x00FC , is negated. Once in Idle, the SPI is active and is used to control the IC. Transition to Hibernate , Oscillator Off. (SPI not functional.) IC Responds to ATTN. Data is retained. Transition Time To or From Idle , Register (300 + 1/CLKO) µs 7, Bit 9 = 1 for frequencies of 1 MHz or less. (SPI not functional.) Responds to , , checks its status, and reads/writes data to the device through the 4-wire SPI port. The transceiver
Freescale Semiconductor
Original
KDS 16.000MHz crystal oscillator kds 2 pin crystal oscillator 4 MHz kds of 16.000 Modem qpsk block diagram

TSX-10A

Abstract: KDS IR Sensor Register 12 programmed to 0x00BC which sets output power to nominal (0 dBm typical). SPI Register 12 , negated. Once in Idle, the SPI is active and is used to control the IC. Transition to Hibernate and Doze , 25 ms to Idle Hibernate Crystal Reference Oscillator Off. (SPI not functional.) IC Responds to , transaction is a minimum of 3 SPI bursts and can extend to a greater number of bursts. 2. SPI Clock (SPICLK , clock (CLKcore), derived from the crystal reference oscillator, to communicate from the SPI registers
Freescale Semiconductor
Original
TSX-10A KDS IR Sensor KDS DSX321G tn4-26139 KDS 48 MHZ crystal oscillator KDS 8 MHZ crystal
Showing first 20 results.