SPFD5420A 720-CHANNEL SPFD5420A-C S1-720 V31-0 DB17-0 G1-432 /C11C12 /C12C13 - Datasheet Archive

 

720-channel 6-bit Source Driver with System-on-chip for Color Amorphous TFT-LCDs Preliminary JUL. 13, 2007 Version 0.2 ORISE

 

SPFD5420A SPFD5420A 720-channel 6-bit Source Driver with System-on-chip for Color Amorphous TFT-LCDs Preliminary JUL. 13, 2007 Version 0.2 ORISE Technology reserves the right to change this documentation without prior notice. Information provided by ORISE Technology is believed to be accurate and reliable. However, ORISE Technology makes no warranty for any errors which may appear in this document. Contact ORISE Technology to obtain the latest version of device specifications before placing your order. No responsibility is assumed by ORISE Technology for any infringement of patent or other rights of third parties which may result from its use. In addition, ORISE Technology products are not authorized for use as critical components in life support devices/ systems or aviation devices/systems, where a malfunction or failure of the product may reasonably be expected to result in significant injury to the user, without the express written approval of ORISE Technology. Preliminary SPFD5420A SPFD5420A Table of Contents PAGE 1. GENERAL DESCRIPTION . 4 2. FEATURES. 4 3. ORDERING INFORMATION. 4 4. BLOCK DIAGRAM . 5 5. SIGNAL DESCRIPTIONS. 7 6. INSTRUCTIONS . 11 6.1. OUTLINE .11 6.2. INSTRUCTION . 12 6.2.1. Index Register (IR) . 13 6.2.2. ID Read Register (R000h). 13 6.2.3. Driver Output Control Register (R001h) . 14 6.2.4. LCD Driving Waveform Control (R002h) . 14 6.2.5. Entry Mode (R003h) . 15 6.2.6. Display Control 1 (R007h) . 16 6.2.7. Display Control 2 (R008h) . 17 6.2.8. Display Control 3 (R009h) . 18 6.2.9. Low Power Control (R00Bh). 19 6.2.10. External Display Interface Control 1 (R00Ch) . 19 6.2.11. External Display Interface Control 2 (R00Fh) . 20 6.2.12. Panel Interface Control 1 (R010h). 20 6.2.13. Panel Interface Control 2 (R011h). 21 6.2.14. Panel Interface control 3 (R012h) . 22 6.2.15. Panel Interface control 4 (R020h) . 22 6.2.16. Panel Interface Control 5 (021Rh). 24 6.2.17. Panel Interface Control 6 (R022h). 25 6.2.18. Frame Marker Control (R090h) . 25 6.2.19. Power Control 1 (R100h). 26 6.2.20. Power Control 2 (R101h). 27 6.2.21. Power Control 3 (R102h). 28 6.2.22. Power Control 4 (R103h). 29 6.2.23. Power Control 5 (R107h). 30 6.2.24. Power Control 6(R110h). 30 6.2.25. GRAM Address Set (Horizontal Address) (R200h). 30 6.2.26. GRAM Address Set (Vertical Address) (R201h) . 30 6.2.27. Write Data to GRAM (R202h). 31 6.2.28. Read Data Read from GRAM (R202h). 33 6.2.29. NVM read data 1 (R280h) . 33 6.2.30. NVM read data 2 (R281h) . 34 6.2.31. NVM read data 3 (R282h) . 34 6.2.32. Window Horizontal RAM Address Start (R210h) . 35 6.2.33. Window Horziontal RAM Address End (R211h) . 35 6.2.34. Window Vertical RAM Address Start (R212h) . 35 6.2.35. Window Vertical RAM Address End (R213h) . 35 © ORISE Technology Co., Ltd. Proprietary & Confidential 2 JUL. 13, 2007 Preliminary Version: 0.2 Preliminary SPFD5420A SPFD5420A 6.2.36. Control (R300h to R30Dh). 35 6.2.37. Base Image Number of Line (R400h) . 36 6.2.38. Base Image Display Control (R401h). 39 6.2.39. Based Image Vertical Scroll Control (R404h). 40 6.2.40. Display Position - Partial Display 1 (R500h). 40 6.2.41. RAM Address Start ­ Partial Display 1 (R501h) . 40 6.2.42. RAM Address End ­ Partail Display 1 (R502h) . 40 6.2.43. Display Position ­ Partial Display 2 (R503h). 40 6.2.44. RAM Address Start ­ Partial Display 2 (R504h) . 41 6.2.45. RAM Address End ­ Partial Display 2 (R505h) . 41 6.2.46. Pin Control (R606h). 41 6.2.47. NVM Access Control (R6F0h) . 41 7. GRAM . 42 8. INTERFACES . 44 8.1. SYSTEM INTERFACE . 44 8.2. VSYNC INTERFACE . 47 8.3. EXTERNAL DISPLAY INTERFACE . 48 9. DISPLAY FEATURE FUNCTION: . 51 9.1. FMARK FUNCTION: . 51 9.2. SCAN MODE FUNCTION: . 52 9.3. PARTIAL DISPLAY FUNCTION: . 53 9.4. GAMMA CORRECTION FUNCTIONS:. 54 10. POWER MANAGEMENT SYSTEM: . 55 11. APPLICATION CIRCUITS:. 58 12. INITIAL CODE:. 58 13. ELECTRICAL CHARACTERISTICS:. 59 13.1. ABSOLUTE MAXIMUM RATINGS: . 59 13.2. DC CHARACTERISTICS . 59 13.3. AC CHARACTERISTICS . 60 © ORISE Technology Co., Ltd. Proprietary & Confidential 3 JUL. 13, 2007 Preliminary Version: 0.2 Preliminary SPFD5420A SPFD5420A 720-CHANNEL 720-CHANNEL DRIVER WITH SYSTEM-ON-CHIP (SOC) FOR COLOR AMORPHOUS TFT LCD 1. GENERAL DESCRIPTION The SPFD5420A SPFD5420A, a 262144-color System-on-Chip (SoC) driver System interfaces LSI designed for small and medium sizes of TFT LCD display, is - High-speed interfaces to 8-, 9-, 16-, and 18-bit parallel ports capable of supporting up to 240xRGBx432 in resolution which can - Serial Peripheral Interface (SPI) be achieved by the designated RAM for graphic data. The Interfaces for moving picture display - 6-, 16-, and 18-bit RGB interfaces 720-channel source driver has true 6-bit resolution, which generates 64 Gamma-corrected values by an internal D/A Varies RAM accessing for functional display converter. - Window address function to display at any area on the The SPFD5420A SPFD5420A is able to operate with low IO interface power - Window address function to limit the data rewriting area screen via a moving picture display interface supply up to 1.65V and incorporate with several charge pumps to and reduce data transfer generate various voltage levels that form an on-chip power - Moving and still picture can display at the same time management system for gate driver and source driver. - Vertical scrolling function - Partial screen display The built-in timing controller in SPFD5420A SPFD5420A can support several Power supply interfaces for the diverse request of medium or small size portable - Logic power supply voltage (Vcc): 2.5 ~ 3.1 V display. SPFD5420A SPFD5420A provides system interfaces, which include - I/O interface supply voltage (IOVcc): 1.65 ~ 31 V 8-/9-/16-/18-bit parallel interfaces and serial interface (SPI), to - Analog power supply voltage (Vci): 2.5 ~ 3.1 V configure system. Not only can the system interfaces be used to On-chip power management system configure system, they can also access RAM at high speed for still - Power saving mode (standby / 8-color mode, etc) picture display. In addition, the SPFD5420A SPFD5420A incorporates 6, 16, - Low power consumption structure for source driver. and 18-bit RGB interfaces for picture movement display. The Built-in Charge Pump circuits SPFD5420A SPFD5420A also supports eight-color mode and standby mode for - Source driver voltage level: DDVDH-GND=4.5V ~ 6V. power saving consideration. - Gate driver voltage level (VGH, VGL) VGH = 10.0V ~15.0V 2. FEATURES VGL = -4.5V ~ -12.5V VGH ­ VGL 28.0V One-chip solution for amorphous TFT-LCD. Supports resolution up to 240xRGBx432, incorporating a - Built-in internal oscillator and hardware reset 720-channel source driver and a 432-channel gate driver Built­in One-Time-Programmable (OTP) function for VCOM Outputs 64 -corrected values using an internal true 6-bit amplitude and VcomH voltage adjustment. User identification resolution D/A converter to achieve 262K colors code,4 bits, VCOM level adjustment, 5 bits x 2 sets Built-in 233,280 bytes internal RAM Line Inversion AC drive / frame inversion AC drive 3. ORDERING INFORMATION Product Number Package Type SPFD5420A-C SPFD5420A-C Chip Form with Gold Bump © ORISE Technology Co., Ltd. Proprietary & Confidential 4 JUL. 13, 2007 Preliminary Version: 0.2 Preliminary SPFD5420A SPFD5420A 4. BLOCK DIAGRAM 4.1. Block Function RGND GND 18 Serial interface Graphic RAM (GRAM) 233,280 bytes 18 Read data latch 18 External display interface VSYNC HSYNC DOTCLK ENABLE 18 Write data latch VCC Grayscale voltage generating circuit Gamma-correction Internal reference voltage generating circuit Gate line drive circuit Scan data generating circuit Timing generator CPG VDDTEST S1-720 S1-720 V31-0 V31-0 RESET FMARK TEST1/2 TSC VIREG VREFC VRTEST VREF Source line drive circuit 18 IOGND2 Latch circuit 18 18 bits 16 bits 9 bits 8 bits CS RS WRSCL RD SDI SDO DB17-0 DB17-0 Address counter Latch circuit System Interface AGND M alternating IOVCC1 IM2-1, IM0/ID Control register (CR) Latch circuit Index register (IR) Internal logic power supply regulator NVM VGS VTEST V0T V31T VMON G1-432 G1-432 VPP1-3 VDD LCD drive level generating circuit Proprietary & Confidential 5 TESTA5 VCOM VCOML VCOMH VCOMR VREG1OUT VLOUT1 DDVDH VLOUT2 VGH VLOUT3 VGL VLOUT4 VCL VCI1 © ORISE Technology Co., Ltd. C11+/C11C12 /C11C12+/C12C13 /C12C13+/C13C21 /C13C21+/C21C22 /C21C22+/C22C23 /C22C23+/C23- /C23- VCIOUT VCI VCILVL VREFD JUL. 13, 2007 Preliminary Version: 0.2 Preliminary SPFD5420A SPFD5420A 4.2. System Interface 4.2.4. Graphics RAM (GRAM) 4.2.1. The SPFD5420A SPFD5420A supports three high-speed SPFD5420A SPFD5420A features a 233,280-byte (240RGB 240RGB x 432 x 18 / 8) system interfaces: Graphic RAM (GRAM). 1. 80-system high-speed interfaces with 8-, 9-, 16-, 18-bit parallel ports. 4.2.5. Grayscale Voltage Generating Circuit 2. Serial Peripheral Interface (SPI). SPFD5420A SPFD5420A has true 6-bit resolution D/A converter, which The SPFD5420A SPFD5420A has a 16-bit index register (IR) and two 18-bit generates 64 Gamma-corrected values and cooperates with data registers, a write-data register (WDR) and a read-data OP-AMP structure to enhance display quality. The grayscale register (RDR). voltage can be adjusted by grayscale data set in the -correction The IR register is used to store index information register. from control registers. The WDR register is used to temporarily store data to be written for register control and internal GRAM. The RDR register is used to temporarily store data read from the 4.2.6. Timing Controller GRAM. When graphic data is written to the internal GRAM from SPFD5420A SPFD5420A has a timing controller, which can generate a timing MCU/graphic engine, the data is first written to the WDR and then signal for internal circuit operation such as gate output timing, automatically written to the internal GRAM in internal operation. RAM accessing timing, etc. When graphic data read operation is executed, graphic data is read via the RDR from the internal GRAM. Therefore, invalid data 4.2.7. Oscillator (OSC) is first read out to the data bus when the SPFD5420A SPFD5420A executes st the 1 read operation. The SPFD5420A SPFD5420A also features an internal oscillator to generate Thus, valid data can be read out after the RC oscillation with an internal resistor. In standby mode, RC st SPFD5420A SPFD5420A executes the 1 read operation. oscillation is halted to reduce power consumption. 4.2.2. External Display Interface 4.2.8. Source Driver Circuit The SPFD5420A SPFD5420A supports external RGB interface for picture SPFD5420A SPFD5420A consists of a 720-output source driver circuit (S1 ~ movement display. th S720). display interfaces and the system interface via pin configuration so Data in the GRAM are latched when the 720 bit data is input. The SPFD5420A SPFD5420A allows switching between one of the external The latched data controls the source driver and generates a drive waveform. that the optimum interface is selected for still / moving picture displayed on the screen. 4.2.9. Gate Driver Circuit SPFD5420A SPFD5420A consists When the RGB interface is chosen, display operations are of a 432-output gate driver circuit (G1~G432). The gate driver circuit outputs gate driver signals at synchronized with external supplied signals, VSYNC, HSYNC, and either VGH or VGL level. DOTCLK. Moreover, valid display data (DB17-0 DB17-0) is written to GRAM, which synchronized with signal (DE) enabling. 4.2.10. LCD Driving Power Supply Circuit The LCD driving power supply circuit generates the voltage levels 4.2.3. Address Counter (AC) DDVDH, VLOUT2, VLOUT3 and VCOM for driving an LCD. All this SPFD5420A SPFD5420A features an Address Counter (AC) giving an address voltages can be adjusted by register setting. to the internal GRAM. The address in the AC is automatically updated plus or minus 1. The window address function enables writing data only in the rectangular area arbitrarily set by users on the GRAM. © ORISE Technology Co., Ltd. Proprietary & Confidential 6 JUL. 13, 2007 Preliminary Version: 0.2 Preliminary SPFD5420A SPFD5420A 5. SIGNAL DESCRIPTIONS Signal No. of I/O pins Connected Function with System Configuration Input Signal IM2~1, IM0/ID 3 I GND/ IOVCC Select a mode to interface to an MPU. In serial interface operation, the IM0 pin is used to set the ID bit of device code. IM2 IM1 IM0/ ID 0 0 0 0 0 1 0 1 0 80-system 16-bit interface 0 1 1 80-system 8-bit interface DB17-10 DB17-10 1 0 *(ID) Clock synchronous serial interface - 65,536 1 1 0 Setting disabled - - 1 1 1 Setting disabled - - Interface Mode Colors DB Pin 80-system 18-bit interface 80-system 9-bit interface DB17-0 DB17-0 262,144 DB17-9 DB17-9 262,144 262,144 see Note 1 262,144 see Note 2 DB17-10 DB17-10, DB8-1 Notes: 1. 65,536 colors in one transfer mode 2. 65,536 colors in two transfers mode /RESET 1 I MPU or RESET pin. This is an active low signal. external RC circuit Interface input Signals /CS 1 I MPU Chip select signal. Low: the SPFD5420A SPFD5420A is accessible High: the SPFD5420A SPFD5420A is not accessible Must be connected to the GND or IOVCC level when not used. RS 1 I MPU Register select signal. Low: Index register or internal status is selected. High: Control register is selected. Must be connected to the GND or IOVCC level when not used. (/WR) / (SCL) 1 I MPU (A) In 80-system interface mode, a write strobe signal can be input via this pin and initializes a write operation when the signal is low. (B) In SPI mode, served as a synchronizing clock signal. /RD 1 I MPU In 80-system interface mode, a read strobe signal can be input via this pin and initializes a read operation when the signal is low. Must be connected to the GND or IOVCC level when not in use. SDI 1 I MPU Serial Data is inputted on the rising edge of the SCL signal in SPI mode. Must be connected to the GND or IOVCC level when not in use SDO 1 O MPU Serial Data is outputted on the rising edge of the SCL signal in SPI mode. DB0-DB17 DB0-DB17 1 I/O MPU Served as an 18-bit parallel bi-directional data bus. Data bus pin assignment corresponding to different modes are summarized in the table: Mode 8-bit system interface DB17-DB9 DB17-DB9 16-bit system interface DB17-DB10 DB17-DB10, DB8-DB1 18-bit system interface Proprietary & Confidential DB17-DB10 DB17-DB10 9-bit system interface © ORISE Technology Co., Ltd. Pin Assignment DB17-DB0 DB17-DB0 7 JUL. 13, 2007 Preliminary Version: 0.2 Preliminary SPFD5420A SPFD5420A Signal No. of I/O pins Connected Function with 6-bit External (RGB) interface DB17-DB12 DB17-DB12 16-bit External (RGB) interface DB17-13 DB17-13, DB11-DB1 DB11-DB1 18-bit External (RGB) interface DB17-DB0 DB17-DB0 Must be connected to the GND or IOVCC level when not in use. VSYNC 1 I MPU In external interface mode, served as a vertical synchronize signal input Must be connected to the IOVCC or GND level when not in use. HSYNC 1 I MPU In external interface mode, served as a horizontal synchronized signal input ENABLE 1 I MPU In external interface mode, polarity of ENABLE signal is synchronized with Must be connected to the IOVCC or GND level when not used. valid graphic data input. Low: Valid data on DB17-DB0 DB17-DB0 High: Invalid data on DB17-DB0 DB17-DB0 Moreover, setting EPL bit can change the polarity of the ENABLE signal. Must be connected to the GND or IOVCC level when not in use. DOTCLK 1 I MPU In external interface mode, served as a dot clock signal. When DPL = "0": Input data on the rising edge of DOTCLK When DPL = "1": Input data on the falling edge of DOTCLK It is fixed to the IOVCC level when not in use. FMARK 1 O MPU Frame head pulse signal, which is used when writing data to the internal RAM. Keep this pin open when not used. Charge Pump and Power Supply Signal C11P/N C11P/N, 12 I/O Step-up Connect boost capacitors for the internal DC/DC converter circuit to these capacitor C12P/N C12P/N pins. C13P/N C13P/N Leave the pins open when DC/DC converter circuits are not used. C21P/N C21P/N, C22P/N C22P/N C23P/N C23P/N VCIOUT 1 O Stabilizing Output voltage from the step-up circuit 1, generated from the reference capacitor, VCI1 voltage. VC bits set the output factor. Make sure to connect to stabilizing capacitor. VCI1 1 I/O VCIOUT Reference voltage of step-up circuit 1. Make sure the output voltage levels from VLOUT1, VLOUT2, and VLOUT3 do not exceed the respective setting ranges. VLOUT1 I Output voltage from the step-up circuit 1, generated from VCI1. The step-up factor is set by BT. Make sure to connect to stabilizing capacitor. DDVDH 1 O Stabilizing capacitor, DDVDH 1 VLOUT1 = 4.5V ~ 6.0V VLOUT1 Power supply for the source driver liquid crystal drive unit and VCOM drive. Connect to VLOUT1. DDVDH = 4.5V ~ 6.0V VLOUT2 1 O Stabilizing Output voltage from the step-up circuit 2, generated from VCI1 and DDVDH. capacitor, VGH The step-up factor is set by BT. Make sure to connect to stabilizing capacitor. VLOUT2 = max 15.0V VGH 1 I VLOUT2 Liquid crystal drive power supply. Connect to VLOUT2. VLOUT3 1 O Stabilizing Output voltage from the step-up circuit 2, generated from VCI1 and DDVDH. capacitor, VGL The step-up factor is set by BT bits. Make sure to connect to stabilizing capacitor. VLOUT3 = min ­12.5V © ORISE Technology Co., Ltd. Proprietary & Confidential 8 JUL. 13, 2007 Preliminary Version: 0.2 Preliminary SPFD5420A SPFD5420A Signal No. of I/O pins Connected with VGL 1 I VLOUT4 1 O VLOUT3 Stabilizing capacitor, VCL VCL 1 Function Liquid crystal drive power supply. Connect to VLOUT3. Output voltage from the step-up circuit 2, generated from VCI1 and DDVDH. The step-up factor is set by BT bits. capacitor. Make sure to connect to stabilizing VLOUT = -1.9V ­ 3.0V. Stabilizing VCOML drive power supply. Make sure to connect to stabilizing capacitor. capacitor VCL = -1.9V ~ -3.0V I Reference VCILVL must be at the same electrical potential as VCI. VCILVL = 2.5V ~ power supply VCILVL O 3.1V. Connect to external power supply. In case of COG, connect to VCI on the FPC to prevent noise. VPP1 1 I Power supply or open OTP power supply. Operation mode VPP1 VPP2 VPP3 VPP2 1 I Power supply or NVM Write 9V 7.5V GND open NVM read Open Open GND/Open VPP3A, 3B 2 I Power supply or open Source/Gate Driver and VCOM Signals G1~G432 432 O LCD S1~S720 720 O Output gate driver signals, which has the swing from VGH to VGL LCD Output source driver signals. The D/A converted 64-gray-scale analog voltages are outputted. VREG1 OUT 1 O Stabilizing Output voltage generated from the reference voltage (VCILVL or VCIR). The capacitor factor is determined by instruction (VRH bits). VREG1OUT is used for (1) source driver grayscale reference voltage, (2) VCOMH level reference voltage, and (3) VCOM amplitude reference voltage. Connect to a stabilizing capacitor when in use. VREG1OUT = 4.0V ~ (DDVDH ­ 0.5)V VCOM 1 O TFT panel Power supply to TFT panel's common electrode. VCOM alternates between common VCOMH and VCOML. The alternating cycle is set by internal register. Also, the electrode 1 O VCOM output can be started and halted by register setting. Stabilizing The High level of VCOM amplitude. The output level can be adjusted by either capacitor VCOMH external resistor (VCOMR) or electronic volume. Make sure to connect to stabilizing capacitor. VCOML 1 O Stabilizing The Low level of VCOM amplitude. The output level can be adjusted by capacitor instruction (VDV bits). VCOML = (VCL+0.5)V ~ 0V. Make sure to connect to stabilizing capacitor. VCOMR 1 I Variable resistor or open Connect a variable resistor when adjusting the VCOMH level between VREG1OUT and GND. VGS 1 I GND VCC 1 - Power supply Internal logic power: VCC = 2.5V ~3.1V. VCC > IOVCC. GND 1 - Power supply Internal logic GND: GND = 0V. RGND 1 - VDD 1 O Stabilizing IOVCC 1 - Power supply Power supply capacitor Reference level for the grayscale voltage generating circuit. Internal RAM GND. RGND must be at the same electrical potential as GND. In case of COG, connect to GND on the FPC to prevent noise. Internal logic regulator output, which is used as the power supply to internal logic. Connect a stabilizing capacitor. Power supply to the interface pins: RESET*, CS*, WR, RD*, RS, DB17-0 DB17-0, VSYNC, HSYNC, DOTCLK, ENABLE. IOVCC = 1.65V ~ 3.3V. VCC IOVCC. In case of COG, connect to VCC on the FPC if IOVCC=VCC, to prevent noise. © ORISE Technology Co., Ltd. Proprietary & Confidential 9 JUL. 13, 2007 Preliminary Version: 0.2 Preliminary SPFD5420A SPFD5420A Signal No. of I/O pins IOGND 1 Connected Function with - Power supply GND for the interface pins: RESET*, CS*, WR, RD*, RS, DB17-0 DB17-0, VSYNC, HSYNC, DOTCLK, ENABLE. IOGND = 0V. In case of COG, connect to GND on the FPC to prevent noise. AGND 1 - Power supply Analog GND (for logic regulator and liquid crystal power supply circuit): AGND = 0V. In case of COG, connect to GND on the FPC to prevent noise. VCI VCILVL 1 1 I I Power supply Power supply to the liquid crystal power supply analog circuit. Connect to an external power supply of 2.5V ~ 3.1V. Reference VCILVL must be at the same electrical potential as VCI. VCILVL = 2.5V ~ power supply 3.1V. Connect to external power supply. In case of COG, connect to VCI on the FPC to prevent noise. Misc. Signal V0T, V31T 2 VTEST 1 VREFC 1 I/O Open I/O Open I/O Open I/O Open I/O Open I/O Open I/O Open I/O Open I/O Open I/O Open I/O Open I/O Open I/O Open I/O Open I/O Open I IOGND Test pins. Leave them open. SPFD5420A SPFD5420A use these pins to do self-test. No signal on panel can cross these pins, otherwise function fail. Test pins. Leave them open. SPFD5420A SPFD5420A use these pins to do self-test. No signal on panel can cross these pins, otherwise function fail. VREF VDDTEST VREFD 1 1 1 Test pins. Fix to the AGND level. Test pins. Leave them open. Test pins. Fix to the AGND level. Test pins. Leave them open. SPFD5420A SPFD5420A use these pins to do self-test. No signal on panel can cross these pins, otherwise function fail. VMON 1 Test pins. Leave them open. SPFD5420A SPFD5420A use these pins to do self-test. No signal on panel can cross these pins, otherwise function fail. TESTA5 1 Test pins. Leave them open. SPFD5420A SPFD5420A use these pins to do self-test. No signal on panel can cross these pins, otherwise function fail. IOVCCDUM1~2 2 VCCDUM1 1 IOGNDDUM1~3 3 AGNDDUM1~5 DUMMYR1~10 5 10 Test pins. Leave them open. Test pins. Leave them open. Test pins. Leave them open. Test pins. Fix to VREFC, VDDTEST. Test pins. Leave them open. SPFD5420A SPFD5420A use these pins to do self-test. No any signal on panel can cross these pins, otherwise function fail. VGLDMY1~4 4 TESTO1~18 18 TEST1~3 3 © ORISE Technology Co., Ltd. Proprietary & Confidential Test pins. Leave them open. Test pins. Leave them open. Test pins. Connect to IOGND. 10 JUL. 13, 2007 Preliminary Version: 0.2 Preliminary SPFD5420A SPFD5420A 6. INSTRUCTIONS 6.1. Outline The SPFD5420A SPFD5420A supports 18-bit data bus interface to access The instruction can be categorized into 8 groups. And the 8 groups command register to configure system. When the command are: register accessing is desired, sending the command information to 1. Specify the index of register specify which index register would be accessed and following the 2. Read a status data to that control register. Moreover, register accessing 3. Display control operation should cooperate with RS, /WR, /RD signal for 4. Power management Control SPFD5420A SPFD5420A to recognize the control instruction. And command 5. Graphics data processing instruction can be accomplished by using all system interfaces 6. Set internal GRAM address (18-bit, 16-bit, 9-bit, 8-bit 80 system and SPI). The corresponding 7. Transfer data to and from the internal GRAM pin assignment of different system interface are shown in Figure 8. Internal grayscale -correction 6-1 to Figure 6-6 80-system 18-bit interface 80-system 8-bit interface DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 CB 15 CB 14 CB 13 CB 12 CB 11 CB 10 CB 9 DB 9 CB 8 DB 8 CB 7 DB 7 CB 6 DB 6 CB 5 DB 5 CB 4 DB 4 CB 3 DB 3 CB 2 DB 2 CB 1 DB 1 1st Transfer DB 0 2nd Transfer DB 17 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 CB 15 CB 0 DB 16 CB 14 CB 13 CB 12 CB 11 CB 10 CB 9 CB 8 CB 7 CB 6 CB 5 CB 4 CB 3 CB 2 CB 1 CB 0 Figure 6-1 Figure 6-4 Serial interface Data Format 80-system 16-bit interface DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 8 DB 7 DB 6 DB 5 DB 4 DB 3 DB 2 1st Transfer DB 1 2nd Transfer D 15 CB 15 CB 14 CB 13 CB 12 CB 11 CB 10 CB 9 CB 7 CB 6 CB 5 CB 4 CB 3 CB 2 CB 1 D 13 D 12 D 11 D 10 D 9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 CB 15 CB 8 D 14 CB 14 CB 13 CB 12 CB 11 CB 10 CB 9 CB 8 CB 7 CB 6 CB 5 CB 4 CB 3 CB 2 CB 1 CB 0 CB 0 Figure 6-2 80-system 9-bit interface 1st Transfer DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 Figure 6-5 2nd Transfer DB 11 DB 10 DB 9 DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 9 Serial interface Data Transfer Format Transfer Start CB 15 CB 14 CB 13 CB 12 CB 11 CB 10 CB 9 CB 8 CB 7 CB 6 CB 5 CB 4 CB 3 CB 2 CB 1 Transfer end CS (input) CB 0 1 2 3 4 5 6 0 1 1 1 0 ID 7 8 9 10 11 12 13 14 15 16 17 18 19 D10 D9 D8 D7 D6 D5 20 21 22 23 D2 D1 24 SCL (input) MSB Figure 6-3 SDI (input) Device ID code SDO (output) LSB RS RW D15 D14 D13 D12 D11 RS RW D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D4 D3 D3 D2 D1 D0 D0 Figure 6-6 © ORISE Technology Co., Ltd. Proprietary & Confidential 11 JUL. 13, 2007 Preliminary Version: 0.2 Preliminary SPFD5420A SPFD5420A 6.2. Instruction Table 6-1 Instruction List Table Register No Register 000h 001h ID Read Driver Output Control 002h Upper 8-bit CB12 CB11 1 0 0 0 CB15 0 0 CB14 1 0 CB13 0 0 0 0 0 0 0 BGR (0) CB9 0 0 0 CB10 1 SM (0) 0 0 0 HWM (0) 0 0 0 FP3 (1) PTV (0) FP2 (0) PTS2 (0) FP1 (0) PTS1 (0) BASEE (0) FP0 (0) PTS0 (0) CB6 0 0 CB5 1 0 CB2 0 0 CB1 0 0 CB0 0 0 0 0 0 0 0 0 I/D0 (1) AM (0) 0 NW1 (0) EPF1 (0) NW0 (0) EPF0 (0) ORG (0) 0 I/D1 (1) 0 0 VON (0) 0 GON (0) 0 DTE (0) 0 0 0 0 PTG1 (0) PTG0 (0) BP3 (1) ISC3 (0) BP2 (0) ISC2 (0) D1 (0) BP1 (0) ISC1 (0) D0 (0) BP0 (0) ISC0 (0) 0 VEM0 (0) DM0 (0) 0 0 0 0 0 RIM1 (0) COL (0) RIM0 (0) HSPL (0) RTNI3 (0) 0 0 EPL (0) RTNI1 (1) SDTI1 (0) 0 DPL (0) RTNI0 (1) SDTI0 (0) 0 003h TRIREG (0) DFM (0) 004h-006h 007h Setting disabled Display Control (1) 0 0 008h Display Control (2) 0 0 009h Low Power Control (1) 0 0 0 0 00Ah 00Bh Setting Disabled Low Power Control (2) 0 0 0 0 0 0 0 0 0 0 0 0 ENC2 (0) ENC1 (0) ENC0 (0) 0 0 0 RM (0) 0 0 DM1 (0) 0Ch External Display Controll (1) 00Dh-00Eh Setting Disabled 00Fh External Display Controll (2) 010h Panel interface Control 1 011h Panel interface Control 2 012h Panel interface Control 3 013-01Fh Setting Disabled 020h Panel Interface Control 4 021h Panel Interface Control 5 022h Panel Interface Control 6 023h-08Fh Setting Disabled 090h Frame Marker Control Lower 8-bit CB4 CB3 0 0 0 0 CB7 0 0 LCD Drive Waveform Control Entry Mode PTDE1 PTDE0 (0) (0) 0 0 0 CB8 0 SS (0) B/C (0) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VSPL (0) RTNI4 (1) 0 0 0 0 0 0 NOWI2 (0) 0 DIVI0 (0) NOWI0 (0) VEQW10 VEQW10 (0) 0 0 DIVI1 (0) NOWI1 (0) VEQW11 VEQW11 (0) 0 0 0 0 0 RTNI2 (1) SDTI2 (0) 0 0 0 0 0 0 0 DIVE1 (0) DIVE0 (0) 0 RTNE6 (0) RTNE5 (0) RTNE4 (1) RTNE3 (1) RTNE2 (1) RTNE1 (1) RTNE0 (0) 0 0 0 0 NOWE3 (0) NOWE2 (0) NOWE1 (0) NOWE0 (0) 0 0 0 0 SDTE3 (0) SDTE2 (0) SDTE1 (0) SDTE0 (0) 0 0 0 0 0 VEQWE2 (0) VEQWE1 (0) VEQWE0 (0) 0 0 0 0 0 0 0 0 FMI3 (0) FMI2 (0) FMI1 (0) FMI0 (0) 0 0 0 FMP8 (0) FMP7 (0) FMP6 (0) FMP5 (0) FMP4 (0) FMP3 (0) FMP2 (0) FMP1 (0) FMP0 (0) 0 0 0 0 APE (0) 0 0 AP0 (0) DC00 (0) PON (0) 0 VRH3 (0) 0 DSTB (0) VC2 (0) VRH2 (0) 0 SLP (0) VC1 (0) VRH1 (0) 0 0 0 AP1 (0) DC01 (0) PSON (0) 0 0 0 BT1 (0) DC11 (0) 0 VC0 (0) VRH0 (0) 0 091h-0FFh 100h Setting disabled Power Control (1) 101h Power Control (2) 0 0 0 SAP (0) 0 102h Power Control (3) 0 0 0 0 0 BT2 (0) DC12 (0) 0 103h Power Control (4) 0 0 VCOMG (0) VDV4 (0) VDV3 (0) VDV2 (0) VDV1 (0) BT0 (0) DC10 (0) VCMR0 (0) VDV0 (0) 104h-106h 107h Setting disabled Power Control (5) 0 0 0 0 0 0 0 0 0 0 0 DCM0 (0) DCT3 (0) DCT2 (0) DCT1 (0) DCT0 (0) 108-10Fh 110h Setting disabled Power Control(6) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PSE (0) 111-1ffh 200h 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AD16 (0) AD7 (0) AD15 (0) AD6 (0) AD14 (0) AD5 (0) AD13 (0) AD4 (0) AD12 (0) AD3 (0) AD11 (0) AD2 (0) AD10 (0) AD1 (0) AD9 (0) AD0 (0) AD8 (0) HSA2 (0) HEA2 (1) VSA2 (0) VEA2 (1) HSA1 (0) HEA1 (1) VSA1 (0) VEA1 (1) HSA0 (0) HEA0 (1) VSA0 (0) VEA0 (1) 214-27Fh 280h Setting disabled GRAM address Set Horizontal Address GRAM address Set Vertical Address Write Data to GRAM Read Data from GRAM Setting disabled Window Horzontal RAM Address Start Window Horzontal RAM Address End Window Vertical RAM Address Start Window Vertical RAM Address End Setting Disabled NVM Write/Read 281h 201h 202h 203-20Fh 210h VREG1R (0) 0 DC02 (0) 0 Data format is varied according to "interface". 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VCom high voltage 1 0 0 0 0 0 282h VCom high voltage 2 0 0 0 0 0 283-2FFh 300h Setting disabled Control (1) 0 0 0 V1RP4 V1RP3 V1RP2 V1RP1 V1RP0 0 0 301h Control (2) 0 0 V2RP5 V2RP4 V2RP3 V2RP2 V2RP1 V2RP0 0 0 211h 212h 213h © ORISE Technology Co., Ltd. Proprietary & Confidential 0 VSA8 (0) VEA8 (1) HSA7 (0) HEA7 (1) VSA7 (0) VEA7 (0) HSA6 (0) HEA6 (1) VSA6 (0) VEA6 (0) HSA5 (0) HEA5 (1) VSA5 (0) VEA5 (1) HSA4 (0) HEA4 (0) VSA4 (0) VEA4 (1) HSA3 (0) HEA3 (1) VSA3 (0) VEA3 (1) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VCMSEL (0) 0 0 VCM14 VCM14 (0) VCM24 VCM24 (0) UID3 (0) VCM13 VCM13 (0) VCM23 VCM23 (0) UID2 UID1 (0) (0) VCM12 VCM12 VCM11 VCM11 (0) (0) VCM22 VCM22 VCM21 VCM21 (0) (0) 0 V1RN4 V1RN3 V1RN2 V1RN1 V1RN0 V2RN5 V2RN4 V2RN3 V2RN2 V2RN1 V2RN0 12 UID0 (0) VCM10 VCM10 (0) VCM20 VCM20 (0) JUL. 13, 2007 Preliminary Version: 0.2 Preliminary SPFD5420A SPFD5420A 302h Control (3) 0 0 V3RP5 V3RP4 V3RP3 V3RP2 V3RP1 V3RP0 0 0 V3RN5 V3RN4 V3RN3 V3RN2 V3RN1 V3RN0 303h Control (4) 0 0 V4RP5 V4RP4 V4RP3 V4RP2 V4RP1 V4RP0 0 0 V4RN5 V4RN4 V4RN3 V4RN2 V4RN1 V4RN0 304h Control (5) 0 0 V5RP5 V5RP4 V5RP3 V5RP2 V5RP1 V5RP0 0 0 V5RN5 V5RN4 V5RN3 V5RN2 V5RN1 V5RN0 305h Control (6) 0 0 0 V6RP4 V6RP3 V6RP2 V6RP1 V6RP0 0 0 0 V6RN4 V6RN3 V6RN2 V6RN1 V6RN0 306h Control (7) 0 0 0 V7RP4 V7RP3 V7RP2 V7RP1 V7RP0 0 0 0 V7RN4 V7RN3 V7RN2 V7RN1 V7RN0 307h Control (8) 0 0 0 V8RP4 V8RP3 V8RP2 V8RP1 V8RP0 0 0 0 V8RN4 V8RN3 V8RN2 V8RN1 V8RN0 308h Control (9) 0 0 0 0 V9RP3 V9RP2 V9RP1 V9RP0 0 0 0 0 V9RN3 V9RN2 V9RN1 V9RN0 309h Control (10) 0 0 0 0 V10RP3 V10RP3 V10RP2 V10RP2 V10RP1 V10RP1 V10RP0 V10RP0 0 0 0 0 V10RN3 V10RN3 V10RN2 V10RN2 V10RN1 V10RN1 V10RN0 V10RN0 30Ah Control (11) 0 0 0 0 V11RP3 V11RP3 V11RP2 V11RP2 V11RP1 V11RP1 V11RP0 V11RP0 0 0 0 0 V11RN3 V11RN3 30Bh Control (12) 0 0 0 0 V12RP3 V12RP3 V12RP2 V12RP2 V12RP1 V12RP1 V12RP0 V12RP0 0 0 0 0 V12RN3 V12RN3 V12RN2 V12RN2 V12RN1 V12RN1 V12RN0 V12RN0 30Ch Control (13) 0 0 0 0 V13RP3 V13RP3 V13RP2 V13RP2 V13RP1 V13RP1 V13RP0 V13RP0 0 0 0 0 V13RN3 V13RN3 V13RN2 V13RN2 V13RN1 V13RN1 V13RN0 V13RN0 30Dh Control (14) 0 0 0 0 V14RP3 V14RP3 V14RP2 V14RP2 V14RP1 V14RP1 V14RP0 V14RP0 0 0 0 0 V14RN3 V14RN3 V14RN2 V14RN2 V14RN1 V14RN1 V14RN0 V14RN0 30Eh Control (15) 0 0 0 0 V15RP3 V15RP3 V15RP2 V15RP2 V15RP1 V15RP1 V15RP0 V15RP0 0 0 0 0 V15RN3 V15RN3 V15RN2 V15RN2 V15RN1 V15RN1 V15RN0 V15RN0 0 0 0 0 V16RP3 V16RP3 V16RP2 V16RP2 V16RP1 V16RP1 V16RP0 V16RP0 0 0 0 0 V16RN3 V16RN3 V16RN2 V16RN2 V16RN1 V16RN1 V16RN0 V16RN0 GS (0) 0 0 NL4 (0) 0 NL3 (0) 0 NL2 (0) 0 NL1 (0) 0 NL0 (0) 0 0 0 0 NL5 (0) 0 0 0 SCN5 (0) 0 SCN4 (0) 0 SCN3 (0) 0 SCN2 (0) NDL (0) SCN1 (0) VLE (0) SCN0 (0) REV (0) 0 0 0 0 0 0 0 VL8 (0) VL7 (0) VL6 (0) VL5 (0) VL4 (0) VL3 (0) VL2 (0) VL1 (0) VL0 (0) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PTDP08 PTDP08 (0) PTSA08 PTSA08 (0) PTEA08 PTEA08 (0) PTDP18 PTDP18 (0) PTSA18 PTSA18 (0) PTEA18 PTEA18 (0) PTDP07 PTDP07 (0) PTSA07 PTSA07 (0) PTEA07 PTEA07 (0) PTDP17 PTDP17 (0) PTSA17 PTSA17 (0) PTEA17 PTEA17 (0) PTDP06 PTDP06 (0) PTSA06 PTSA06 (0) PTEA06 PTEA06 (0) PTDP16 PTDP16 (0) PTSA16 PTSA16 (0) PTEA16 PTEA16 (0) PTDP05 PTDP05 (0) PTSA05 PTSA05 (0) PTEA05 PTEA05 (0) PTDP15 PTDP15 (0) PTSA15 PTSA15 (0) PTEA15 PTEA15 (0) PTDP04 PTDP04 (0) PTSA04 PTSA04 (0) PTEA04 PTEA04 (0) PTDP14 PTDP14 (0) PTSA14 PTSA14 (0) PTEA14 PTEA14 (0) PTDP03 PTDP03 (0) PTSA03 PTSA03 (0) PTEA03 PTEA03 (0) PTDP13 PTDP13 (0) PTSA13 PTSA13 (0) PTEA13 PTEA13 (0) PTDP02 PTDP02 (0) PTSA02 PTSA02 (0) PTEA02 PTEA02 (0) PTDP12 PTDP12 (0) PTSA12 PTSA12 (0) PTEA12 PTEA12 (0) PTDP01 PTDP01 (0) PTSA01 PTSA01 (0) PTEA01 PTEA01 (0) PTDP11 PTDP11 (0) PTSA11 PTSA11 (0) PTEA11 PTEA11 (0) PTDP00 PTDP00 (0) PTSA00 PTSA00 (0) PTEA00 PTEA00 (0) PTDP10 PTDP10 (0) PTSA10 PTSA10 (0) PTEA10 PTEA10 (0) 30Fh Control (16) 310-3FFh 400h Setting disabled Size of base image 401h Base image display control Setting disabled Vertical Scoll Control 402-403h 404h 405-4FFh 500h 506-605h 606h Setting disabled Display Position Partial Display 1 RAM Address Start Partial Display 1 RAM Address End Partial Display 1 Display Position Partial Display 2 RAM Address Start Partial Display 2 RAM Address End Partial Display 2 Setting Disabled i80-I/F Endian Control 607-6EFh 6F0h Setting disabled NVM access control 6F1-FFFh V11RN2 V11RN2 V11RN1 V11RN1 V11RN0 V11RN0 Setting disabled 501h 502h 503h 504h 505h 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TCREV1 (0) 0 0 0 0 0 0 0 TCREV0 (0) 0 0 0 0 0 0 0 0 TE (0) 0 EOP1 (0) EOP0 (0) 0 0 EAD1 (0) EAD0 (0) The following are detailed explanations of instructions with illustrations of instruction bits (CB15-0 CB15-0) assigned to each interface. 6.2.1. Index Register (IR) R/W RS W 0 CB15 CB14 CB13 CB12 CB11 CB10 0 0 0 0 0 ID10 CB9 CB8 CB7 CB6 CB5 CB4 CB3 CB2 CB1 CB0 ID9 ID8 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 The index register specifies the index (R000h ~ RFFFh) of a control register. 6.2.2. ID Read Register (R000h) R/W RS R 0 CB15 CB14 CB13 CB12 CB11 CB10 0 1 0 1 0 1 CB9 CB8 CB7 CB6 CB5 CB4 CB3 CB2 CB1 CB0 0 0 0 0 1 0 0 0 0 0 The IC code of SPFD5420A SPFD5420A can be accessed by read operation. `5408H 5408H can be read out when read ID operation is exectued. © ORISE Technology Co., Ltd. Proprietary & Confidential 13 JUL. 13, 2007 Preliminary Version: 0.2 Preliminary SPFD5420A SPFD5420A 6.2.3. Driver Output Control Register (R001h) R/W RS W 1 SS: CB15 CB14 CB13 CB12 CB11 CB10 0 0 0 0 0 CB9 SM(0) 0 CB8 SS(0) CB7 CB6 CB5 CB4 CB3 CB2 CB1 CB0 0 0 0 0 0 0 0 0 Shift direction of the source driver output selection. When SS = "0", source driver shifts from S1 to S720. When SS = "1", source driver shifts from S720 to S1. Moreover, SS can cooperate with BGR for different color filter configuration of LCD panel. The combination of SS and BGR bit are summarized at Table 6-2. Table 6-2 SS=0;BGR=0; S1 S2 S3 S718 S719 S720 SS=0;BGR=1; S1 S2 S3 S718 S719 S720 SS=1,BGR=0; S1 S2 S3 S718 S719 S720 SS=1,BGR=1; S1 S2 S3 S718 S719 S720 SM: Set the scan mode of the gate driver output. Moreover, SM can cooperate with GS for different LCD panel gate line layout. The combination of GS and SM bit are summarized at Table 6-3. Table 6-3 SM GS Shift Direction (begin,.,end) 0 0 G1, G2, G3, G4.G429, G430, G431, G432 0 1 G432, G431, G430, G429.G4, G3, G2, G1 1 0 G1, G3, G5, .G429, G431, .G2, G4,. G430, G432 1 1 G432, G430, G428,.G4, G2, .G429, G431,.G3, G1 6.2.4. LCD Driving Waveform Control (R002h) R/W W RS 1 CB15 CB14 CB13 CB12 CB11 CB10 0 0 0 0 0 1 CB9 B/C(0) NW1-NW0: SPFD5420A SPFD5420A provides 1-line inversion for Vcom. CB8 CB7 CB6 CB5 CB4 CB3 CB2 0 0 0 0 0 0 0 CB1 CB0 NW1(0) NW0(0) B/C: This bit .is to set the Vcom toggle at frame rate format of N-line inversion format. B/C=0: Frame inversion. B/C=1: 1-line inversion. © ORISE Technology Co., Ltd. Proprietary & Confidential 14 JUL. 13, 2007 Preliminary Version: 0.2 Preliminary SPFD5420A SPFD5420A 6.2.5. Entry Mode (R003h) R/W RS W CB15 CB14 CB13 CB12 CB11 CB10 1 TRI DFM REG(0) 0 (0) BGR 0 0 CB9 HWM (0) CB8 CB7 0 ORG (0) CB6 0 (0) CB5 CB4 CB3 CB2 0 I/D1 I/D0 AM (1) (1) (0) CB1 CB0 EPF1 EPF0 (0) (0) the window start postion is treated as (00000h), regardless the physical location in GRAM. Table 6-4 ORG=0: RAM address setting should set to the address. Operation ORG AM I/D1 I/D0 Function mode Mode 1 0 0 0 0 Mode2 0 1 0 1 Replace vertical data Mode3 1 0 1 0 Conditionally replace horizontal data Mode4 1 1 1 1 HWM: SPFD5420A SPFD5420A provides a high speed GRAM accessing Replace horizontal data Conditionally replace vertical data mode that updated GRAM data in 1-line unit. Be aware that data can be written to GRAM only if accessing GRAM operation is halted after writing enough data for 1-line. Make sure the AM is set to "0", when HWM function is set to "1''. AM: To set the update direction when writing data to GRAM. If AM=1, data will write in vertical direction. If AM=0, data will BGR: To set the order of RGB dot location in GRAM. write in horizontal direction. Moreover, if a fixed window BGR=0: same assignment of RGB allocation of DB17-0 DB17-0 GRAM accessing is desired, the writing direction can be set BGR=1: inverse assignment of RGB allocation of DB17-0 DB17-0 by I/D1-0 and AM bits. DFM: In combination with TRIREG setting to set the different data transfer mode. I/D1-0: To specify address counter increment /decrement automatically function while GRAM is accessing. I/D[0] indicates the increment or decrement in horizontal TRIREG: to set 1­3 time transfer mode for system interface. direction. I/D[1] indicates the increment or decrement in TRIREG bit should cooperate with DFM to meet the vertical direction. specific transfer mode. I/D[0]=0: decrement in horizontal direction automatically For 8-bit databus interface mode: I/D[0]=1: increment in horizontal direction automatically TRIREG=0: 2 time transfer mode for 16-bit GRAM data. I/D[1]=0: decrement in vertical direction automatically TRIREG=1: 3 time transfer mode for 18-bit GRAM data I/D[1]=1: increment in vertical direction automatically For 16-bit databus interface mode: ID[1-0] setting can cooperate with AM bit to set the data TRIREG=0: 1 time transfer mode for 16-bit GRAM data. TRIREG=1: 2 time transfer mode for 18-bit GRAM data updating direction. Note: Set TRIREG=0, when using neither 8-bit nor 16-bit. ORG: SPFD5420A SPFD5420A provides the option of start address definition EPF1-0: To select the algorithm of expanding 8/16 bits to 18 bits. when window function is selected. ORG=1: RAM address setting should set to (00000h) no This setting is valid only when 16-bit or 8-bit interfaces matter where the window start address is. In this case, are in use. © ORISE Technology Co., Ltd. Proprietary & Confidential 15 JUL. 13, 2007 Preliminary Version: 0.2 Preliminary SPFD5420A SPFD5420A 6.2.6. Display Control 1 (R007h) R/W RS W CB15 CB14 CB13 CB12 CB11 CB10 1 0 0 0 PTDE1 PTDE0 (0) CB9 0 0 CB8 CB7 BASEE (0) 0 CB6 CB5 CB4 GON (0) CB2 CB1 CB0 0 0 D1 D0 (0) (0) DTE (0) (0) VON CB3 (0) To set the internal operation, source driver output and VON: To Control VCOM output signal. The combination of APE, VCOM output function. When D1-0=00; SPFD5420A SPFD5420A is AP[1:0] , VON and VCOMG bit is summarized at Table set to standby mode. The combination of D1-0 and D1-0: 6-7. BASEE bit is summarized at Table 6-5. Table 6-7 Table 6-5 APE D1 D0 BASEE Source, VCOM output Internal Operation VON VCOMG VCOM Output 0 * * * GND 00 0 0 GND 00 1 0-1 Setting Disabled 00 FLM AP [1:0] 0 1 Setting Disabled 0 0 * GND Terminated OFF 0 1 * GND Normal Operation ON 1 0 * Non-lit display Normal Operation ON 1 0 Non-lit display Normal Operation ON 01-11 0 0 GND 1 Normal display Normal Operation ON 01-11 0 1 VCOML 01-11 1 0 VCOMH/GND 01-11 1 1 VCOMH/VCOML 1 1 DTE, GON: Specify the high/low level of gate driver output signal. The combination of DTE and GON bit is summarized at Table 6-6. BASEE: To enable Base image display BASEE 0 (1) Non-lit display (2) Table 6-6 Partial image display APE GON DTE Gate Output 0 * * VGL(=GND) 0 0 VGH 0 1 VGH PTDE1-0: To set the partial-display enables function. 1 0 VGL PTDE [0]: "0" Partial image 1 display "Off". 1 1 VGH/VGL 1 1 Base image is display on the LCD "1" Partial image 1 display "On". PTDE [1]: "0" Partial image 2 display "Off". "1" Partial image 2 display "On". © ORISE Technology Co., Ltd. Proprietary & Confidential 16 JUL. 13, 2007 Preliminary Version: 0.2 Preliminary SPFD5420A SPFD5420A 6.2.7. Display Control 2 (R008h) R/W RS W CB15 CB14 CB13 CB12 CB11 CB10 1 0 0 0 0 CB9 CB8 FP3 FP2 FP1 FP0 (1) (0) (0) CB7 CB6 CB5 CB4 0 0 0 0 (0) CB3 CB2 CB1 CB0 BP3 BP2 BP1 BP0 (1) (0) (0) (0) FP3-0: Set the amount of blank period of front porch In external display interface mode, a back porch (BP) period starts BP3-0: Set the amount of blank period of back porch on the falling edge of the VSYNC signal, followed by a display operation period. After driving the number of lines set with NL bits, Table 6-8 summarized the function of FP3-0/BP3-0 setting. a front porch period starts. After the front porch period, a blank When setting this register, make sure that: period continues until the next input of VSYNC signal. Be aware BP + FP 16 lines that different interface mode, has different BP/ FP setting. Table FP 2 lines 6-9 summarized the setting for each interface mode. BP 2 lines Table 6-8 FP3 FP2 FP1 FP0 Number of lines for the Front BP3 BP2 BP1 BP0 Number of lines for the Back Porch Porch 0 0 0 0 Setting disabled 0 0 0 1 Setting disabled 0 0 1 0 2 lines 0 0 1 1 3 lines 0 1 0 0 4 lines 0 1 0 1 5 lines 0 1 1 0 6 lines 0 1 1 1 7 lines 1 0 0 0 8 lines 1 0 0 1 9 lines 1 0 1 0 10 lines 1 0 1 1 11 lines 1 1 0 0 12 lines 1 1 0 1 13 lines 1 1 1 0 14 lines 1 1 1 1 Setting disabled Figure 6-7 Front porch and back porch function diagram Table 6-9 Operation of Internal clock BP 2 lines FP 2 lines FP +BP 16 lines RGB interface BP 2 lines FP 2 lines FP +BP 16 lines VSYNC interface BP 2 lines FP 2 lines FP +BP = 16 lines © ORISE Technology Co., Ltd. Proprietary & Confidential 17 JUL. 13, 2007 Preliminary Version: 0.2 Preliminary SPFD5420A SPFD5420A 6.2.8. Display Control 3 (R009h) R/W RS W CB15 CB14 CB13 CB12 CB11 CB10 1 0 0 0 0 PTV (0) CB9 CB8 CB7 CB6 0 0 PTS2 PTS1 PTS0 (0) (0) (0) CB5 CB4 CB3 CB2 PTG1 PTG0 ISC3 (0) (0) (0) CB1 CB0 ISC2 ISC1 ISC0 (0) (0) (0) To set the gate driver scan cycle in non-display area. Table 6-10 summarized the function of ISC3-0 setting ISC3-0: Table 6-10 ISC3 ISC2 ISC1 ISC0 Scan cycle 0 0 0 0 Setting disable 0 0 0 1 3frames 50 ms 0 0 1 0 5 frames 84 ms 0 0 1 1 7 frames 117 ms 0 1 0 0 9 frames 150 ms 0 1 0 1 11 frames 184 ms 0 1 1 0 13 frames 217 ms 0 1 1 1 15 frames 251 ms 1000-1111 fFLM=60Hz Setting Disabled PTG1-0: To set the gate driver scan mode in non-display area. Table 6-11 summarized the function of PTG1-0 setting Table 6-11 0 0 0 1 display area Based on the PTS2-0 bits setting 1 1 Source outputs in non- display area PTG0 0 Gate outputs in non- Normal scan PTG1 1 VCOM output VCOMH/VCOML Setting Disable Interval scan Based on the PTS2-0 bits setting VCOMH/VCOML Setting Disable PTS2-0: To set the source driver output level in non-display area of partial display mode. Table 6-12 summarized the function of PTS2-0 setting. Table 6-12 PTS2 PTS1 PTS0 Source output in non-display area +ve polarity 0 0 0 V31 V0 001-011 1 0 Operation amplifier in non-display area -ve polarity V0-V31 V0-V31 Setting inhibited 0 V31 V0 101-111 V0-V31 V0-V31 Setting inhibited PTV: To set VCOM output in non-display area, Vcom operates normally when PTV = 1, and stops operation when PTV = 0. © ORISE Technology Co., Ltd. Proprietary & Confidential 18 JUL. 13, 2007 Preliminary Version: 0.2 Preliminary SPFD5420A SPFD5420A 6.2.9. Low Power Control (R00Bh) R/W RS W CB15 CB14 CB13 CB12 CB11 CB10 1 0 0 0 0 0 CB9 CB8 CB7 CB6 CB5 0 0 0 0 0 0 CB4 CB3 VEM0 (0) CB2 CB1 0 0 0 CB0 COL (0) COL: COL = 0: 262,144 colors COL = 1: 8 colors. In 8-color mode, the source output is either connected to VREGIOUT or GND. VEM0: VEM0 = 1, when VCOM is switched from VCOMH to VCOML, it will dropped to GND level in the intermediate stage. 6.2.10. External Display Interface Control 1 (R00Ch) R/W RS W CB15 CB14 CB13 CB12 CB11 CB10 1 ENC2 ENC1 ENC0 0 (0) (0) 0 CB9 0 0 CB8 CB7 CB6 0 0 RM (0) (0) CB5 CB4 DM1 DM0 (0) CB3 CB2 0 0 CB1 (0) CB0 RIM1 RIM0 (0) (0) RIM1-0: To set the different transfer modes of RGB interface. Table 6-13 summarized the function of RIM1-0 setting. Table 6-13 RIM1 RIM0 RGB Interface Mode Colors 0 0 18-bit RGB interface (one transfer/pixel) 262K DB 17-0 0 1 16-bit RGB interface (one transfer/pixel) 65K DB 17-13; DB 11-1 1 0 6-bit RGB interface (three transfers/pixel) 262K DB17-12 DB17-12 1 1 Setting disabled - - DM1-0: To specify the display interface mode. Set the RAM data write cycle in RGB interface mode. ENC2-0: Table 6-14summarized the function of DM1-0 setting. Table 6-16 summarized the function of ENC2-0 setting. Table 6-14 DM1 Data Bus Table 6-16 DM0 Display Interface 0 1 1 0 1 1 Table 6-15 0 1 2 frames 1 0 3 frames 1 1 4 frames 0 0 5 frames 0 1 6 frames 1 summarized the function of RM bit setting. 1 frame 1 GRAM. The setting of RM should be consistent with DM1-0. 0 1 RM: Select the interface to access the SPFD5420A SPFD5420A's internal 0 0 Setting disabled RAM data write cycle 0 VSYNC interface ECN0 0 RGB interface ECN1 0 Internal clock operation 0 ECN2 1 0 7 frames 1 0 1 1 8 frames Table 6-15 RM Interface for RAM Access 0 System interface/VSYNC interface 1 RGB interface © ORISE Technology Co., Ltd. Proprietary & Confidential 19 JUL. 13, 2007 Preliminary Version: 0.2 Preliminary SPFD5420A SPFD5420A 6.2.11. External Display Interface Control 2 (R00Fh) R/W RS CB15 CB14 CB13 CB12 CB11 CB10 CB9 CB8 CB7 CB6 CB5 W 1 0 0 0 0 0 0 0 0 0 0 0 DPL: Select the data latch edge of the DOTCLK signal in RGB CB4 CB3 VSPL HSPL (0) (0) CB2 CB1 EPL DPL (0) 0 CB0 (0) HSPL: The polarity of HSYNC signal selection in RGB interface interface mode. mode. DPL = "0": rising edge of the DOTCLK. HSPL = "0": Low active. DPL ="1": falling edge of the DOTCLK. HSPL = "1": High active. EPL: The polarity of ENABLE signal selection in RGB interface VSPL: The polarity of VSYNC signal selection in RGB interface mode. mode. EPL = "0": ENABLE: Low active VSPL = "0": Low active. EPL = "1": ENABLE: High active VSPL = "1": High active. 6.2.12. Panel Interface Control 1 (R010h) R/W RS W 1 RTNI4-0: CB15 CB14 CB13 CB12 CB11 CB10 0 0 0 0 0 CB9 CB8 DIVI1 DIVI0 0 (0) (0) CB7 CB6 CB5 0 0 0 CB4 CB3 CB2 CB1 CB0 RTNI4 RTNI3 RTNI2 RTNI1 RTNI0 (1) (0) (1) (1) (1) Set the clock cycle per line Table 6-17 summarized the function of RTNI4-0 setting. Table 6-17 RTNI4 0 RTNI3 0 RTNI2 0 RTNI1 RTNI0 0 Clock Cycles per line 0 Setting disable Setting disable 1 0 0 0 0 16 clocks 1 0 0 0 1 17 clocks 1 0 0 1 0 18 clocks 1 0 0 1 1 19 clocks 1 0 1 0 0 20 clocks 1 0 1 0 1 21 clocks 1 0 1 1 0 22 clocks 1 0 1 1 1 23 clocks 1 1 0 0 0 24 clocks 1 1 0 0 1 25 clocks 1 1 0 1 0 26 clocks 1 1 0 1 1 27 clocks 1 1 1 0 0 28 clocks 1 1 1 0 1 29 clocks 1 1 1 1 0 30 clocks 1 1 1 1 1 31 clocks © ORISE Technology Co., Ltd. Proprietary & Confidential 20 JUL. 13, 2007 Preliminary Version: 0.2 Preliminary SPFD5420A SPFD5420A DIVI1-0: To specified the division ratio of internal operation clock fosc =Frequency of RC oscillation frequency. Set the RTN and DIVI bits to adjust frame frequency. Be aware of that if the number of lines for Formula to calculate frame frequency driving liquid crystal is changed, the frame frequency must also be adjusted. Moreover, In RGB interface mode, the DIVI1-0 bits are disabled. Table 6-18 summarized the function of DIVI1-0 setting. fosc: frequency of RC oscillation Line: number of lines for driving liquid crystal (NL bits) Division ratio: DIVI bits Table 6-18 Division Ratio Frequency 0 1 fosc / 1 0 1 2 fosc / 2 1 0 4 fosc / 4 1 1 8 Clock cycles per line: RTNI bits Internal Operation Clock fosc / 8 DIVI1 DIVI0 0 FP: the number of lines for the front porch period BP: the number of lines for the back porch period 6.2.13. Panel Interface Control 2 (R011h) R/W RS W CB15 CB14 CB13 CB12 CB11 CB10 0 1 0 0 0 0 CB9 CB8 NOWI2 NOWI1 NOWI0 (0) (0) CB7 CB6 0 0 CB5 0 (0) CB4 0 CB3 0 CB2 CB1 CB0 SDTI2 SDTI1 SDTI0 (0) (0) (0) SDTI2-0: Set the delay of source output in every line. NOWI [2:0]: Set the adjacent gate driver output non-overlap period. Table 6-19 summarized the function of NOWI2-0 setting. Table 6-20 Table 6-19 Source output delay period Gate output non-overlap period NOWI2 NOWI1 NOWI0 SDTI2 SDTI1 SDTI0 0 0 0 0 clock 0 0 1 1 clocks 0 1 0 2 clocks 0 1 1 3 clocks 1 0 0 4 clocks 1 0 1 5 clocks 1 1 0 6 clocks 1 1 1 7 clocks Internal Operation (reference clock: internal oscillator) clock: internal oscillator) 0 0 0 0 clock 0 0 1 1 clocks 0 1 0 2 clocks 0 1 1 3 clocks 1 0 0 4 clocks 1 0 1 5 clocks 1 1 0 6 clocks 1 1 1 Internal Operation (reference 7 clocks © ORISE Technology Co., Ltd. Proprietary & Confidential 21 JUL. 13, 2007 Preliminary Version: 0.2 Preliminary SPFD5420A SPFD5420A 6.2.14. Panel Interface control 3 (R012h) R/W RS W CB15 CB14 CB13 CB12 CB11 CB10 0 1 0 0 0 0 CB9 VEQW1 VEQW0 (0) CB8 CB7 0 0 CB6 CB5 0 CB4 CB3 CB2 0 0 0 0 CB5 CB4 CB3 CB1 CB0 0 0 CB1 CB0 (0) VEQWI[1:0]: Set VCOM equalize period. Table 6-21 VEQWI1 VEQWI0 VCOM Equalize Period 0 0 0 clock 0 1 1 clock 1 0 2 clocks 1 1 3 clocks 6.2.15. Panel Interface control 4 (R020h) R/W RS W 1 CB15 CB14 CB13 CB12 CB11 CB10 0 0 0 0 0 0 CB9 CB8 DIVE1 DIVE0 (1) (0) CB7 0 CB6 CB2 RTNE6 RTNE5 RTNE4 RTNE3 RTNE2 RTNE1 RTNE0 (0) (0) (1) (1) (1) (1) (0) RTNE6-0: Set the clock cycle per line Table 6-22 summarized the function of RTNE5-0 setting. Table 6-22 RTNE5 0 RTNE4 0 RTNE3 0 RTNE2 0 RTNE1 0 RTNE0 Clock Cycles per line 0 Setting disable Setting disable 0 1 0 0 0 0 16 clocks 0 1 0 0 0 1 17 clocks 0 1 0 0 1 0 18 clocks 0 1 0 0 1 1 19 clocks 0 1 0 1 0 0 20 clocks 0 1 0 1 0 1 21 clocks 0 1 0 1 1 0 22 clocks 0 1 0 1 1 1 23 clocks 0 1 1 0 0 0 24 clocks 0 1 1 0 0 1 25 clocks 0 1 1 0 1 0 26 clocks 0 1 1 0 1 1 27 clocks 0 1 1 1 0 0 28 clocks 0 1 1 1 0 1 29 clocks 0 1 1 1 1 0 30 clocks 0 1 1 1 1 1 31 clocks 1 1 0 0 0 0 32 clocks 1 1 0 0 0 1 33 clocks 1 1 0 0 1 0 34 clocks © ORISE Technology Co., Ltd. Proprietary & Confidential 22 JUL. 13, 2007 Preliminary Version: 0.2 Preliminary SPFD5420A SPFD5420A RTNE5 RTNE4 RTNE3 RTNE2 RTNE1 RTNE0 Clock Cycles per line 1 1 0 0 1 1 35 clocks 1 1 0 1 0 0 36 clocks 1 1 0 1 0 1 37 clocks 1 1 0 1 1 0 38 clocks 1 1 0 1 1 1 39 clocks 1 1 1 0 0 0 40 clocks 1 1 1 0 0 1 41 clocks 1 1 1 0 1 0 42 clocks 1 1 1 0 1 1 43 clocks 1 1 1 1 0 0 44 clocks 1 1 1 1 0 1 45 clocks 1 1 1 1 1 0 46 clocks 1 1 1 1 1 1 47 clocks 1 1 0 0 0 0 48 clocks 1 1 0 0 0 1 49 clocks 1 1 0 0 1 0 50 clocks 1 1 0 0 1 1 51 clocks 1 1 0 1 0 0 52 clocks 1 1 0 1 0 1 53 clocks 1 1 0 1 1 0 54 clocks 1 1 0 1 1 1 55 clocks 1 1 1 0 0 0 56 clocks 1 1 1 0 0 1 57 clocks 1 1 1 0 1 0 58 clocks 1 1 1 0 1 1 59 clocks 1 1 1 1 0 0 60 clocks 1 1 1 1 0 1 61 clocks 1 1 1 1 1 0 62 clocks 1 1 1 1 1 1 63 clocks DIVE1-0: To specified the division ratio of internal operation clock frequency. Set the RTNE and DIVE bits to adjust frame frequency. Be aware of that if the number of lines for driving liquid crystal is changed, the frame frequency must also be adjusted. Moreover, In RGB interface mode, the DIVE1-0 bits are disabled. Table 6-23 summarized the function of DIVE1-0 setting. Table 6-23 Division Internal Operation Clock Frequency (16 bit, Internal Operation Clock Frequency(8 bit, three Ratio one time transfer) time transfer) DIVE1 DIVE0 0 0 0 1 4 fosc / 4 fosc / 12 1 0 8 fosc / 8 fosc / 24 1 1 16 fosc / 16 fosc / 48 Setting disable fosc =Frequency of RC oscillation © ORISE Technology Co., Ltd. Proprietary & Confidential 23 JUL. 13, 2007 Preliminary Version: 0.2 Preliminary SPFD5420A SPFD5420A 6.2.16. Panel Interface Control 5 (021Rh) R/W RS W CB15 1 CB14 0 CB13 CB12 0 0 CB11 0 CB10 CB9 CB8 CB7 NOW NOW NOW NOW E3(0) E2(0) E1(0) 0 CB6 CB5 0 CB4 0 E0(0) CB3 0 CB2 CB1 SDT SDT SDT SDT E3(0) E2(0) E1(0) E0(0) NOWE [3:0]: Set the adjacent gate driver output non-overlap period in RGB interface. Table 6-24 summarized the function of NOWE3-0 setting. Table 6-24 NOWE3 NOWE2 NOWE1 NOWE0 Gate output non-overlap period Internal Operation (reference clock: internal oscillator) 0 0 0 0 0 clock 0 0 0 1 1 clocks 0 0 1 0 2 clocks 0 0 1 1 3 clocks 0 1 0 0 4 clocks 0 1 0 1 5 clocks 0 1 1 0 6 clocks 0 1 1 1 7 clocks 1 0 0 0 8 clocks 1 0 0 1 9 clocks 1 0 1 0 10 clocks 1 0 1 1 11 clocks 1 1 0 0 12 clocks 1 1 0 1 13 clocks 1 1 1 0 14 clocks 1 1 1 1 15 clocks SDTE: Set the source output delay in RGB interface. Table 6-25 Source output period SDTE3 SDTE 2 SDTE 1 SDTE 0 0 0 0 0 0 0 0 1 1 clocks 0 0 1 0 2 clocks 0 0 1 1 3 clocks 0 1 0 0 4 clocks 0 1 0 1 5 clocks 0 1 1 0 6 clocks 0 1 1 1 7 clocks 1 0 0 0 8 clocks 1 0 0 1 9 clocks 1 0 1 0 10 clocks Internal Operation (reference clock: internal oscillator) 0 clock 1 0 1 1 11 clocks 1 1 0 0 12 clocks © ORISE Technology Co., Ltd. Proprietary & Confidential 24 CB0 JUL. 13, 2007 Preliminary Version: 0.2 Preliminary SPFD5420A SPFD5420A 1 1 0 1 13 clocks 1 1 1 0 14 clocks 1 1 1 1 15 clocks 6.2.17. Panel Interface Control 6 (R022h) R/W RS W CB15 CB14 CB13 CB12 CB11 CB10 0 1 0 0 0 0 VEQ CB9 CB8 CB7 VEQ VEQ CB6 0 0 CB5 0 CB4 0 CB3 CB2 0 CB1 0 CB0 0 0 WE2(0)WE1(0)WE0(0) VEQWE2-0: To set the drive period of low power VCOM, which is valid when the operation is synchronized with RGB interface signals. Table 6-26 VEQWE2 VEQWE1 VEQWE0 Source Output Delay Perios 0 0 0 0 clock 0 0 1 1 clocks 0 1 0 2 clocks 0 1 1 3 clocks 1 0 0 4 clocks 1 0 1 5 clocks 1 1 0 6 clocks 1 1 1 7 clocks 6.2.18. Frame Marker Control (R090h) R/W RS W CB15 CB14 CB13 CB12 CB11 CB10 1 FMI2 FMI1 FMI0 (0) 0 (0) 0 0 CB9 CB8 0 (0) CB7 CB6 CB5 CB4 CB3 CB2 CB1 CB0 FMP8 FMP7 FMP6 FMP5 FMP4 FMP3 FMP2 FMP1 FMP0 (0) (0) (0) (0) (0) (0) (0) (0) (0) FMP8-0: Set the position of the frame marker. 0 < FMP < BP + NL + FP Table 6-27 FMP8-0 Frame Marker Position 000000000 0 000000001 1 000000010 2 000000011 3 . . 110111100 444 110111101 445 110111110 446 110111111 447 FMI2-0: Set the period of the Frame Marker. 0 1 1 2 frames Table 6-28 1 0 1 4 frames 1 1 1 6 frames FMI2 FMI1 FMI0 Period of FMARK 0 0 0 1 frame © ORISE Technology Co., Ltd. Proprietary & Confidential 25 JUL. 13, 2007 Preliminary Version: 0.2 Preliminary SPFD5420A SPFD5420A 6.2.19. Power Control 1 (R100h) R/W RS CB15 CB14 CB13 W 1 0 0 0 CB12 SAP (0) CB11 0 CB10 CB9 CB8 CB7 BT2 BT1 BT0 APE (0) (0) (0) CB6 (0) CB5 AP1 AP0 (0) 0 CB4 (0) CB3 CB1 DSTB SLP (0) 0 CB2 (0) CB0 0 SLP: Sleep mode selection. When SLP =1, SPFD5420A SPFD5420A set to AP1-0: Operational amplifier DC bias current adjustment. Set AP1-0 sleep mode. In sleep mode, all internal operations are = "00" to stop operational amplifier and DC/DC charge terminated except internal RC oscillation. Be sure that a pump circuits to reduce current consumption during non display off sequence should be executed before set SLP to display period. Table 6-29 summarized the function of "1". In sleep mode, no instruction can be accepted. Set AP1-0 setting. STB=0 can exit sleep mode. Moreover, when exit from sleep table are the ratios of the currents of the corresponding mode, data in GRAM and in instruction registers are settings to the current at the max rank. remained unchanged. Please note that the values listed in the Table 6-29 set to deep standby mode. In this mode, all internal AP0 Constant current in Constant current in power supply circuit AP1 DSTB: Deep Standby mode selection. When DSTB =1, SPFD5420A SPFD5420A Gamma circuit 0 Be sure that start oscillation following by 10ms delay should Halt 0.5 0.62 0 0.75 0.71 1 before set DSTB to "1". Set DSTB=0 can exit standby mode. Halt 1 1 Be sure that a display off sequence should be executed 0 0 operations are terminated including internal RC oscillation. 1 1 1 APE: Enable bit for both liquid crystal power supply and gamma be executed before set DSTB to "0". Moreover, when exit from deep standby mode, data in GRAM and register would voltage generation circuit. be lost, reset and re-sending command and data into GRAM APE="0", Halt liquid crystal power supply and gamma voltage generation circuit are necessary. APE="1", Enable liquid crystal power supply and gamma voltage generation circuit. BT3-0: Set the voltage level of DDVDH, VGH, VGL and VCL. Table 6-30 summarized the function of BT2-0 setting BT2 BT1 BT0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 DDVDH VGH VGL VCI1 x 2 DDVDH x 3 -(VCI1+DDVDHx 2) -VCI1 [VCI1x2] [VCI1 x 6] [VCI1x -5] [VCI1x-1] Setting Disabled Setting Disabled Setting Disabled Setting Disabled Setting Disabled Setting Disabled Setting Disabled Setting Disabled VCI1 x 2 DDVDH x 3 + VCI1 -(VCI1+DDVDHx 2) [x2] [VCI1 x 7] [VCI1x -5] VCI1 x 2 DDVDH x 3 + VCI1 -(DDVDHx 2) [x2] [VCI1 x 7] [VCI1x -4] VCI1 x 2 DDVDH x 3 + VCI1 -(VCI1+DDVDH) [x2] [VCI1 x 7] [VCI1x -3] VCI1 x 2 DDVDH x 3 -(DDVDHx 2) [x2] [VCI1 x 6] [VCI1x -4] VCI1 x 2 DDVDH x 3 -(VCI1+DDVDH) [x2] [VCI1 x 6] [VCI1x -3] Setting Disabled Setting Disabled VCL Capacitor connection pins C23 can be eliminated -VCI1 -VCI1 -VCI1 -VCI1 C23 can be eliminated -VCI1 C23 can be eliminated SAP: Enable bit for gamma voltage generation circuit. SAP="0", Halt gamma voltage generation circuit. SAP="1", Enable gamma voltage generation circuit. © ORISE Technology Co., Ltd. Proprietary & Confidential 26 JUL. 13, 2007 Preliminary Version: 0.2 Preliminary SPFD5420A SPFD5420A 6.2.20. Power Control 2 (R101h) R/W RS CB15 CB14 CB13 CB12 CB11 W 1 0 0 0 0 0 CB10 CB9 CB8 DC12 DC11 DC10 (1) (1) (0) VC2-0: Set the voltage of VCIOUT. VCIOUT is generated by VCILVL. Table 6-31 summarized the function of VC2-0 setting CB7 CB6 CB4 DC02 DC01 DC00 (1) 0 CB5 (1) (0) CB3 0 CB2 CB1 CB0 VC2 VC1 VC0 (0) (0) (0) DC12-10 DC12-10: Set DC/DC charge pump circuit 2 operating frequency. Table 6-33 summarized the function of DC02-00 DC02-00 setting Table 6-33 Table 6-31 VC2 VC1 VC0 VCIOUT 0 0 0 0.94 x VCILVL 0 0 1 0.89 x VCILVL Step-up circuit 2 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 1 0 Oscillation clock / 64 1 1 Oscillation clock / 128 0 0 Oscillation clock / 256 1 0 1 Setting disabled 1 1.00 x VCILVL Oscillation clock / 32 1 Setting Disable Oscillation clock / 16 1 0 Setting Disable 0 0 0 0.76 x VCILVL 0 0 Setting Disable DC10 0 Setting Disable DC11 1 0 Halt Step-up Circuit 2 1 0 DC12 1 1 Setting disabled step-up frequency (fDCDC2) DC02-00 DC02-00: Set DC/DC charge pump circuit 1 operating frequency. Table 6-32 summarized the function of DC02-00 DC02-00 setting Table 6-32 DC/DC charge pump circuit 1 DC02 DC01 DC00 0 0 0 0 0 1 Oscillation clock / 2 0 1 0 Oscillation clock / 4 0 1 1 Oscillation clock / 8 1 0 0 Oscillation clock / 16 frequency (fDCDC1) Oscillation clock 1 0 1 Invalid Setting 1 1 0 Halt Step-up Circuit 1 1 1 1 Invalid Setting © ORISE Technology Co., Ltd. Proprietary & Confidential 27 JUL. 13, 2007 Preliminary Version: 0.2 Preliminary SPFD5420A SPFD5420A 6.2.21. Power Control 3 (R102h) R/W RS W CB15 CB14 CB13 1 0 0 0 CB12 CB11 CB10 0 0 CB9 0 CB8 VCM 0 CB7 CB6 VRE R0(0) G1R(0) 0 CB5 CB4 CB3 CB2 CB1 CB0 PSON PON VRH3 VRH2 VRH1 VRH0 () (0) (0) (0) (0) (0) VRH3-0: Set the voltage level of VREG1OUT, which generated from VCILVL. Table 6-34 summarized the function of VRH3-0 setting Table 6-34 VRH3 VRH2 VRH1 VRH0 VCILVL VCIR 0 0 0 0 Halt 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 disable disable 0 1 0 1 Setting Setting disable disable 0 1 1 1 0 VRH2 VRH1 VRH0 VCILVL VCIR Halt 1 0 0 0 VCILVLx1.6 2.5Vx1.6 Halt Halt 1 0 0 1 VCILVLx1.65 2.5Vx1.65 Halt Halt 1 0 1 0 VCILVLx1.7 2.5Vx1.7 Halt Halt 1 0 1 1 VCILVLx1.75 2.5Vx1.75 Setting Setting 1 1 0 0 VCILVLx1.8 2.5Vx1.8 1 1 0 1 VCILVLx1.85 2.5Vx1.85 1 1 1 0 VCILVLx1.9 2.5Vx1.9 1 1 1 1 1 Setting Setting disable 0 1 VRH3 VREG1OUT voltage VREG1OUT voltage disable Setting Setting disable disable Setting Setting disable disable PON: VLOUT3 ON/OFF control. Set PON = "0" to stop VLOUT3. Set PON = "1" to start VLOUT3. PSON: Power Supply control bit for ON/OFF. When turning on power supply, Set PSE = "1" and then set PSON = "1" to start internal power supply operation. VREG1R: Select reference voltage for VREG1OUT VREG1R = "0" (default): VCILVL (External) as reference voltage for VREG1OUT. VREG1R = "1": VCIR (internal) as reference voltage for VREG1OUT. VCMR[0]: Select VCOMH external resistance or internal setting for VCOMH voltage level. VCMR[0] = "0" use VCOMR (External) setting as VCOMH voltage. VCMR[0] = "1": use register (Internal) setting as VCOMH voltage. © ORISE Technology Co., Ltd. Proprietary & Confidential 28 JUL. 13, 2007 Preliminary Version: 0.2 Preliminary SPFD5420A SPFD5420A 6.2.22. Power Control 4 (R103h) R/W RS W CB15 CB14 1 0 0 CB13 CB12 CB11 CB10 CB9 CB8 VCO VDV4 VDV3 VDV2 VDV1 VDV0 MG(0) (0) (0) (0) (0) (0) CB7 CB6 CB5 CB4 CB3 CB2 CB1 CB0 0 0 0 0 0 0 0 0 VDV4-0: Set the Vcom amplitude. Vcom amplitude is generated from VREG1OUT, the coefficient is valid from 0.7 to 1.24. Table 6-35 VDV4 VDV3 VDV2 VDV1 VDV0 Vcom amplitude 0 0 0 0 0 VREG1OUT x 0.70 0 0 0 0 1 VREG1OUT x 0.72 0 0 0 1 0 VREG1OUT x 0.74 0 0 0 1 1 VREG1OUT x 0.76 0 0 1 0 0 VREG1OUT x 0.78 0 0 1 0 1 VREG1OUT x 0.80 0 0 1 1 0 VREG1OUT x 0.82 0 0 1 1 1 VREG1OUT x 0.84 0 1 0 0 0 VREG1OUT x 0.86 0 1 0 0 1 VREG1OUT x 0.88 0 1 0 1 0 VREG1OUT x 0.90 0 1 0 1 1 VREG1OUT x 0.92 0 1 1 0 0 VREG1OUT x 0.94 0 1 1 0 1 VREG1OUT x 0.96 0 1 1 1 0 VREG1OUT x 0.98 0 1 1 1 1 VREG1OUT x 1.00 1 0 0 0 0 VREG1OUT x 1.02 1 0 0 0 1 VREG1OUT x 1.04 1 0 0 1 0 VREG1OUT x 1.06 1 0 0 1 1 VREG1OUT x 1.08 1 0 1 0 0 VREG1OUT x 1.10 1 0 1 0 1 VREG1OUT x 1.12 1 0 1 1 0 VREG1OUT x 1.14 1 0 1 1 1 VREG1OUT x 1.16 1 1 0 0 0 VREG1OUT x 1.18 1 1 0 0 1 VREG1OUT x 1.20 1 1 0 1 0 VREG1OUT x 1.22 1 1 0 1 1 VREG1OUT x 1.24 1 1 1 0 0 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1 Setting Disabled VCOMG: Set the value of VcomL. When VCOMG = 0, VcomL equals to GND. When VCOMG = 0, VcomL is set by VDV4-0. © ORISE Technology Co., Ltd. Proprietary & Confidential 29 JUL. 13, 2007 Preliminary Version: 0.2 Preliminary SPFD5420A SPFD5420A 6.2.23. Power Control 5 (R107h) R/W RS W 1 CB15 CB14 0 CB13 CB12 CB11 CB10 CB9 CB8 CB7 CB6 CB5 0 0 0 0 0 0 0 0 0 0 CB4 DCM0 (0) CB3 CB2 CB1 CB0 0 0 0 0 6.2.24. Power Control 6(R110h) R/W RS CB15 CB14 CB13 CB12 CB11 CB10 CB9 CB8 CB7 CB6 CB5 CB4 CB3 CB2 CB1 CB0 W 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PSE CB9 CB8 CB7 CB6 CB5 CB4 CB3 CB2 0 0 CB9 CB8 PSE: Power supply enable bit PSE = "1", and set PSON can start SPFD5408 SPFD5408 power supply system. PSE = "0", power supply system reset. . 6.2.25. GRAM Address Set (Horizontal Address) (R200h) R/W W RS CB15 CB14 CB13 CB12 CB11 CB10 1 0 0 0 0 0 0 AD7 AD6 AD5 AD4 AD3 AD2 CB1 AD1 CB0 AD0 See R201h. 6.2.26. GRAM Address Set (Vertical Address) (R201h) R/W W RS CB15 CB14 CB13 CB12 CB11 CB10 1 0 0 0 0 0 0 0 CB7 CB6 CB5 CB4 CB3 CB2 AD16 AD15 AD14 AD13 AD12 AD11 AD10 AD16­0: To set the initial address counter for GRAM address. CB1 AD9 CB0 AD8 Table 6-36 Based on AM and I/D[1:0] setting, the address counter is AD16­AD0 GRAM Setting "00000"H ­ "000EF 000EF"H Bitmap data for G1 "00100"H ­ "001EF 001EF"H Bitmap data for G2 "00200"H ­ "002EF 002EF"H Bitmap data for G3 "00300"H ­ "003EF 003EF"H Bitmap data for G4 GRAM instruction is executed. Moreover, the address : : counter cannot be accessed when the SPFD5420A SPFD5420A is in "1AC00 1AC00"H ­ "1ACEF"H Bitmap data for G399 standby mode. "1AD00 1AD00"H ­ "1ADEF"H Bitmap data for G430 "1AE00 1AE00"H ­ "1AEEF"H Bitmap data for G431 "1AF00 1AF00"H ­ "1AFEF"H Bitmap data for G432 automatically increment or decrement while data are written to the internal GRAM There is no need to updated AD16-0 AD16-0 every data transfer if AD16-0 AD16-0 was set in the beginning of one frame graphic data. Be aware that address counter is not automatically updated if reading data from the internal Table 6-36 summarized the function of AD15-0 AD15-0 setting Note1: The address AD16-0 AD16-0 should be set in the address counter every frame on the falling edge of VSYNC if RGB interface mode is selected. Note2: The address AD16-0 AD16-0 should be set when executing an instruction if system or VSYNC interface mode is selected. © ORISE Technology Co., Ltd. Proprietary & Confidential 30 JUL. 13, 2007 Preliminary Version: 0.2 Preliminary SPFD5420A SPFD5420A 6.2.27. Write Data to GRAM (R202h) R/W RS W CB15 CB14 CB13 CB12 CB11 CB10 1 CB9 CB8 CB7 CB6 CB5 CB4 CB3 CB2 CB1 CB0 RAM write data (WD17-0 WD17-0) The DB17-0 DB17-0 pin assignment is different in different transferring modes. WD17-0 WD17-0: SPFD5420A SPFD5420A supports 18 bits data format. However, if Data in GRAM only 16-bit (565format) is input to GRAM, SPFD5420A SPFD5420A Source Driver Grayscale Output ­ REV=1 (REV=0) will expand the 16 bit data into 18-bit format. Same case RGB Negative(Postive) Positive(Negative) when RGB interface is selected. Based on the graphic 011101 (V17+V16)/2 (V14+V13)/2 data in GRAM, the grayscale voltage of source driver is 011110 Data in GRAM V16 (V15+V14)/2 (V17+V16)/2 V14 V17 100011 Table 6-37 V15 100010 among data bus (DB17-0 DB17-0), (WD17-0 WD17-0) and GRAM. (V16+V15)/2 100001 Figure 6-8 ~ Figure 6-18 illustrates the pin assignment V15 (V16+V15)/2 100000 grayscale voltage output versus graphic data in GRAM. V16 011111 selected. Table 6-37 summarized the source driver (V14+V13)/2 (V18+V17)/2 Source Driver Grayscale Output ­ REV=1 100100 V13 V18 (REV=0) 100101 (V13+V12)/2 (V19+V18)/2 RGB Negative(Postive) Positive(Negative) 100110 V12 V19 000000 V31 V0 100111 (V12+V11)/2 (V20+V19)/2 000001 (V30+V31)/2 (V1+V0)/2 101000 V11 V20 000010 V30 V1 101001 (V11+V10)/2 (V21+V20)/2 000011 (V29+V30)/2 (V2+V1)/2 101010 V10 V21 000100 V29 V2 101011 (V10+V9)/2 (V22+V21)/2 000101 (V29+V28)/2 (V3+V2)/2 101100 V9 V22 000110 V28 V3 101101 (V9+V8)/2 (V23+V22)/2 000111 (V28+V27)/2 (V4+V3)/2 101110 V8 V23 001000 V27 V4 101111 (V8+V7)/2 (V24+V23)/2 001001 (V27+V26)/2 (V5+V4)/2 110000 V7 V24 001010 V26 V5 110001 (V7+V6)/2 (V25+V24)/2 001011 (V26+V25)/2 (V6+V5)/2 110010 V6 V25 001100 V25 V6 110011 (V6+V5)/2 (V26+V25)/2 001101 (V25+V24)/2 (V7+V6)/2 110100 V5 V26 001110 V24 V7 110101 (V5+V4)/2 (V27+V26)/2 001111 (V24+V23)/2 (V8+V7)/2 110110 V4 V27 010000 V23 V8 110111 (V4+V3)/2 (V28+V27)/2 010001 (V23+V22)/2 (V9+V8)/2 111000 V3 V28 010010 V22 V9 111001 (V3+V2)/2 (V29+V28)/2 010011 (V22+V21)/2 (V10+V9)/2 111010 V2 V29 010100 V21 V10 111011 (V2+V1)/2 (V29+V30)/2 V1 V30 010101 (V21+V20)/2 (V11+V10)/2 111100 010110 V20 V11 111101 (V1+V0)/2 (V30+V31)/2 010111 (V20+V19)/2 (V12+V11)/2 111110 (V1+2V0)/2 (V30+2V31)/2 111111 V0 V31 011000 V19 V12 011001 (V19+V18)/2 (V12+V11)/2 011010 V18 V13 011011 (V18+V17)/2 (V13+V12)/2 011100 V17 V14 © ORISE Technology Co., Ltd. Proprietary & Confidential 31 JUL. 13, 2007 Preliminary Version: 0.2 Preliminary SPFD5420A SPFD5420A Figure 6-14 8-bit interface 262 colors) TRIREG = 1, DFM=0. Figure 6-8 18-bit interface (262,144 colors) Figure 6-15 8-bit interface (262K colors) TRIREG = 1, DFM=1 Figure 6-9 16-bit interface (65,536 colors) TRIREG= 0 Figure 6-16 18-bit RGB interface (262,144 colors) Figure 6-10 16-bit interface (262,144 colors) TRIREG = 1, DFM = 0 Figure 6-17 16-bit RGB interface (65,563 colors) Figure 6-11 16-bit interface (262,144 colors) TRIREG = 1, DFM = 1 Figure 6-18 6-bit RGB interface (262,144 colors) Figure 6-12 9-bit interface (262,144 colors) Figure 6-13 8-bit interface (65,536 colors) TRIREG = 0 © ORISE Technology Co., Ltd. Proprietary & Confidential 32 JUL. 13, 2007 Preliminary Version: 0.2 Preliminary SPFD5420A SPFD5420A SPFD5420A SPFD5420A supports external (RGB) interface. In RGB interface mode, all graphic data are stored in GRAM. To meet the diverse requirement of small size LCD panel, SPFD5420A SPFD5420A also supports in a fix window using RGB interface and outside the window still use system interface. In RGB interface mode, data writing to the internal RAM is synchronized with DOTCLK during ENABLE = "Low". Set ENABLE "High" to terminate writing data to RAM. Wait for a write/read bus Figure 6-19 cycle time. If accessing internal RAM using the RGB interface is desired after accessing the RAM via the system interface. Figure 6-19 illustrates the timing diagram while RGB and system interface are both use in the same time. 6.2.28. Read Data Read from GRAM (R202h) R/W W RS CB15 CB14 CB13 CB12 CB11 CB10 1 CB9 CB8 CB7 CB6 CB5 CB4 CB3 CB2 CB1 CB0 RAM Read data (RD17-0 RD17-0) The DB17-0 DB17-0 pin assignment is different in different transferring modes. R202 also served as a register, which store the data read out from GRAM. When data are read out from the GRAM is desired, first sets the RAM address and executes first word read, and issues second word read. When first word read instruction is issued, Invalid data are sent to the data bus DB17-0 DB17-0. Valid data are sent to the data bus as second word data is executed. The LSBs of R and B dots cannot read out, when the 8 or 16-bit interface is selected, Note: This register is not available with the RGB interface. Figure 6-20 and Figure 6-23Figure 6-23 illustrates the pin assignment among data bus (DB17-0 DB17-0), R22 (RD17-0 RD17-0) and GRAM in read data instruction. Figure 6-20 18-bit interface Figure 6-22 9-bit interface Figure 6-21 16-bit interface Figure 6-23 8-bit interface / SPI 6.2.29. NVM read data 1 (R280h) R/W W RS 1 CB15 CB14 CB13 CB12 CB11 CB10 0 0 0 0 0 0 CB9 CB8 CB7 CB6 CB5 CB4 0 0 0 0 0 0 CB3 CB2 CB1 CB0 UID3 UID2 UID1 UID0 (0) (0) (0) (0) See R282h © ORISE Technology Co., Ltd. Proprietary & Confidential 33 JUL. 13, 2007 Preliminary Version: 0.2 Preliminary SPFD5420A SPFD5420A 6.2.30. NVM read data 2 (R281h) R/W W RS CB15 CB14 CB13 CB12 CB11 CB10 1 0 0 0 0 0 CB9 CB8 CB7 CB6 CB5 0 0 0 0 0 CB9 CB8 CB7 CB6 CB5 0 CB4 CB3 CB2 CB1 CB0 VCM VCM VCM VCM VCM 14(0) 13(0) 12(0) 11(0) 10(0) See R282h 6.2.31. NVM read data 3 (R282h) R/W W RS CB15 CB14 CB13 CB12 CB11 CB10 1 0 0 0 0 0 0 0 0 VCM SEL 0 0 CB4 CB3 CB2 CB1 CB0 VCM VCM VCM VCM VCM 24(0) 23(0) 22(0) 21(0) 20(0) UID[3:0]: SPFD5420A SPFD5420A provides a 4-bit identification code UID[3:0] VCM2 [4:0]: These pins are to set the factor for generating VCOMH for user to use. UID[3:0] can be write / read from NVM. when VCMSEL="1". Table 6-39 summarized the the factor of UID can be read out via R280h. VERG1OUT Table 6-39 VCM2[4:0] 5'h00 5'h01 5'h02 5'h03 5'h04 5'h05 5'h06 5'h07 5'h08 5'h09 5'h0A 5'h0B 5'h0C 5'h0D 5'h0E 5'h0F 5'h10 5'h11 5'h12 5'h13 5'h14 5'h15 5'h16 5'h17 5'h18 5'h19 5'h1A 5'h1B 5'h1C 5'h1D 5'h1E 5'h1F VCM1 [4:0]:These pins are to set the factor for generating VCOMH when VCMSEL="0". Table 6-38 summarized the the factor of VERG1OUT Table 6-38 VCM1[4:0] 5'h00 5'h01 5'h02 5'h03 5'h04 5'h05 5'h06 5'h07 5'h08 5'h09 5'h0A 5'h0B 5'h0C 5'h0D 5'h0E 5'h0F 5'h10 5'h11 5'h12 5'h13 5'h14 5'h15 5'h16 5'h17 5'h18 5'h19 5'h1A 5'h1B 5'h1C 5'h1D 5'h1E 5'h1F © ORISE Technology Co., Ltd. Proprietary & Confidential VCOMH voltage VREG1OUT x 0.69 VREG1OUT x 0.70 VREG1OUT x 0.71 VREG1OUT x 0.72 VREG1OUT x 0.73 VREG1OUT x 0.74 VREG1OUT x 0.75 VREG1OUT x 0.76 VREG1OUT x 0.77 VREG1OUT x 0.78 VREG1OUT x 0.79 VREG1OUT x 0.80 VREG1OUT x 0.81 VREG1OUT x 0.82 VREG1OUT x 0.83 VREG1OUT x 0.84 VREG1OUT x 0.85 VREG1OUT x 0.86 VREG1OUT x 0.87 VREG1OUT x 0.88 VREG1OUT x 0.89 VREG1OUT x 0.90 VREG1OUT x 0.91 VREG1OUT x 0.92 VREG1OUT x 0.93 VREG1OUT x 0.94 VREG1OUT x 0.95 VREG1OUT x 0.96 VREG1OUT x 0.97 VREG1OUT x 0.98 VREG1OUT x 0.99 VREG1OUT x 1.00 VCOMH voltage VREG1OUT x 0.69 VREG1OUT x 0.70 VREG1OUT x 0.71 VREG1OUT x 0.72 VREG1OUT x 0.73 VREG1OUT x 0.74 VREG1OUT x 0.75 VREG1OUT x 0.76 VREG1OUT x 0.77 VREG1OUT x 0.78 VREG1OUT x 0.79 VREG1OUT x 0.80 VREG1OUT x 0.81 VREG1OUT x 0.82 VREG1OUT x 0.83 VREG1OUT x 0.84 VREG1OUT x 0.85 VREG1OUT x 0.86 VREG1OUT x 0.87 VREG1OUT x 0.88 VREG1OUT x 0.89 VREG1OUT x 0.90 VREG1OUT x 0.91 VREG1OUT x 0.92 VREG1OUT x 0.93 VREG1OUT x 0.94 VREG1OUT x 0.95 VREG1OUT x 0.96 VREG1OUT x 0.97 VREG1OUT x 0.98 VREG1OUT x 0.99 VREG1OUT x 1.00 VCMSEL: VCMSEL is to select VCM1 or VCM2; When VCMSEL="0", VCM1 is selected while VCMSEL="1", VCM2 is selected. 34 JUL. 13, 2007 Preliminary Version: 0.2 Preliminary SPFD5420A SPFD5420A 6.2.32. Window Horizontal RAM Address Start (R210h) R/W RS W CB15 CB14 CB13 CB12 CB11 CB10 1 0 0 0 0 0 CB9 0 0 CB8 CB7 CB6 CB5 CB4 CB3 CB2 HSA7 HSA6 HSA5 HSA4 HSA3 0 CB1 CB0 HAS HSA1 HSA0 (0) (0) (0) (0) (0) (0)2 (0) (0) CB7 CB6 CB5 CB4 CB3 CB2 CB1 CB0 See R213h. 6.2.33. Window Horziontal RAM Address End (R211h) R/W RS W CB15 CB14 CB13 CB12 CB11 CB10 1 0 0 0 0 0 CB9 0 0 CB8 HEA7 HEA6 HEA5 HEA4 HEA3 HEA2 HEA1 HEA0 0 (1) (1) (1) (1) (1) (1) (1) (1) CB7 CB6 CB5 CB4 CB3 CB2 CB1 CB0 See R213h. 6.2.34. Window Vertical RAM Address Start (R212h) R/W RS W CB15 CB14 CB13 CB12 CB11 CB10 1 0 0 0 0 0 CB9 0 CB8 VSA8 VSA7 VSA6 VSA5 VSA4 VSA3 VSA2 VSA1 VSA0 0 (0) (0) (0) (0) (0) (0) (0) (0) (0) CB8 CB7 CB6 CB5 CB4 CB3 CB2 CB1 CB0 See R213h. 6.2.35. Window Vertical RAM Address End (R213h) R/W RS W CB15 CB14 CB13 CB12 CB11 CB10 1 0 0 0 0 0 CB9 0 VEA8 VEA7 VEA6 VEA5 VEA4 VEA3 VEA2 VEA1 VEA0 0 (1) (1) (1) HSA7-0/HEA7-0: SPFD5420A SPFD5420A provides window access function. Set HSA7-0 and HEA7-0 represent the start address and end 000000h address of the window function in horizontal direction. To use (1) (1) (1) (1) HSA (1) (1) HEA VSA window-accessing function, HSA and HEA bits must be set before starting RAM write operation. Be aware that "00"h HSA7-0< HEA7-0 "EF"h and HEA-HAS>="04h". Window Address Area VSA8-0/VEA8-0: SPFD5420A SPFD5420A provides window access function. Set VSA8-0 and VEA8-0 represent the start address and end address of the window in vertical direction. To VEA use window-accessing function, VSA and VEA bits must be set before GRAM address area starting RAM write operation. Be aware that "00"h VSA8-0< VEA8-0 9'h1AF. Figure 6-24 illustrates the window-accessing function. 6.2.36. Control (R300h to R30Dh) T.B.D. © ORISE Technology Co., Ltd. Proprietary & Confidential 35 JUL. 13, 2007 Preliminary Version: 0.2 1AFEFh Preliminary SPFD5420A SPFD5420A 6.2.37. Base Image Number of Line (R400h) R/W RS W CB15 CB14 CB13 CB12 CB11 CB10 1 GS (0) 0 CB9 CB8 NL5 NL4 NL3 NL2 NL1 NL0 (0) (0) (0) (0) (0) (0) CB7 0 CB6 0 CB5 CB4 CB3 CB2 CB1 CB0 SCN5 SCN4 SCN3 SCN2 SCN1 SCN0 (0) (0) (0) (0) (0) (0) SCN5-0: Set the SCN5-0 bits can specify the starting position of the gate driver. The start p