SPC8106 8106CFG SDU8106B0E SPC8108F0C MEMCS16 IOCS16 -MEMCS16 -IOCS16 16-BIT - Datasheet Archive

 

SPC8106 Technical Manual Issue Date: 04/01/97 Copyright © 1997 S-MOS Systems Inc. All rights reserved. VDC This document,

 

SPC8106 SPC8106 LCD/CRT VGA CONTROLLER SPC8106 SPC8106 Technical Manual Issue Date: 04/01/97 Copyright © 1997 S-MOS Systems Inc. All rights reserved. VDC This document, and any text derived, extracted or transmitted from it, is the sole property of S-MOS Systems Inc. and may not be used, copied, transmitted or otherwise made available to any other person, unless specifically allowed under license agreement with S-MOS Systems Inc. If furnished under a license, this document may be used and copied only in accordance with the terms of such license, and with the inclusion of this copyright notice. No title or ownership of the technology herein is transferred. The information in this document is subject to change without notice and should not be construed as a commitment by S-MOS Systems Inc. This document does not necessarily describe any current planned or future product by S-MOS Systems Inc., nor does it represent any commitment to implement any such product. 411-1.0 S-MOS Systems, Inc. · Tel: (408) 922-0200 · Fax: (408) 922-0238 · http://www.smos.com 1 THIS PAGE INTENTIONALLY BLANK 2 S-MOS Systems, Inc. · Tel: (408) 922-0200 · Fax: (408) 922-0238 · http://www.smos.com 411-1.0 SPC8106 SPC8106 1.0 SPC8106 SPC8106 Technical Manual CUSTOMER SUPPORT INFORMATION Comprehensive Support Tools S-MOS Systems provides to the system designer and computer OEM manufacturer a complete set of resources and tools for the development of VGA Graphics Systems. Evaluation / Demonstration Board · Assembled and fully tested graphics evaluation board with installation guide and schematics · To borrow an evaluation board, please contact your local S-MOS sales representative or contact S-MOS at (408) 922-0200 Ext. 3440 VGA Chip Documentation · Technical manual includes Data Sheet, Application Notes, and Programmer's Reference · To remain on the mailing list for updates to this manual, please FAX the Acknowledgment of Receipt form to (408) 922-0238 Software · Video BIOS · OEM Utilities · User Utilities · Evaluation Software · To download these programs, contact Application Engineering Support for an S-MOS Graphics BBS ID Application Engineering Support Engineering and Sales Support is provided by: Northern California S-MOS Systems, Inc. 150 River Oaks Parkway San Jose, CA 95134 Tel: (408) 922-0200 Fax: (408) 922-0238 Northeast S-MOS Northeast Systems, Inc. 301 Edgewater Place #120 Wakefield, MA 01880 Tel: (617) 246-3600 Fax: (617) 246-5443 411-1.0 North Central S-MOS Systems Inc., North Central 1450 East American Lane, Suite 1550 Schaumburg, IL 60713 Tel: (847) 517-7667 Fax: (847) 517-7601 Southeast S-MOS Southeast Systems, Inc. 4300 Six Forks Road #430 Raleigh, NC 27609 Tel: (919) 781-7667 Fax: (919) 781-6778 S-MOS Systems, Inc. · Tel: (408) 922-0200 · Fax: (408) 922-0238 · http://www.smos.com 3 THIS PAGE INTENTIONALLY BLANK 4 S-MOS Systems, Inc. · Tel: (408) 922-0200 · Fax: (408) 922-0238 · http://www.smos.com 411-1.0 SPC8106 SPC8106 SPC8106 SPC8106 Technical Manual TABLE OF CONTENTS INTRODUCTION SPC8106 SPC8106 Data Sheet SPECIFICATION SPC8106 SPC8106 Hardware Functional Specification PROGRAMMER'S REFERENCE SPC8106 SPC8106 BIOS Functional Specification SPC8106 SPC8106 Programming Notes and Examples UTILITIES Software Utility Disk Installation Guidelines SPC8106 SPC8106 SETFONT Display Utility SPC8106 SPC8106 BOLD Display Utility SPC8106 SPC8106 REVERSE Display Utility SPC8106 SPC8106 PWRSAVE Power Save Utility SPC8106 SPC8106 READCHIP Diagnostic Utility SPC8106 SPC8106 WGS Windows Gray-scale Utility SPC8106 SPC8106 SESHELL Shell Utility SPC8106 SPC8106 SHOWMODE Demonstration Program SPC8106 SPC8106 LCDF Display Utility SPC8106 SPC8106 VRTEXP.EXE Vertical Expand Utility SPC8106 SPC8106 8106CFG 8106CFG Configuration Utility SPC8106 SPC8106 DISPLAY Utility SPC8106 SPC8106 SPRITEST Display Utility SPC8106 SPC8106 HOTDISP Display Utility SPC8106 SPC8106 FLASHROM Utility VESAPD Display Utility DRIVERS SPC8106 SPC8106 Windows 3.1x 16-Color Panning Driver SPC8106 SPC8106 Windows 3.1x 256-Color Driver EVALUATION SDU8106B0E SDU8106B0E Rev 1 Evaluation Board User Manual SPC8106 SPC8106 Current Consumption 411-1.0 S-MOS Systems, Inc. · Tel: (408) 922-0200 · Fax: (408) 922-0238 · http://www.smos.com 5 THIS PAGE INTENTIONALLY BLANK 6 S-MOS Systems, Inc. · Tel: (408) 922-0200 · Fax: (408) 922-0238 · http://www.smos.com 411-1.0 SPC8106 SPC8106 LCD/CRT VGA CONTROLLER Data Sheet Copyright © 1997 S-MOS Systems Inc. All rights reserved. VDC This document, and any text derived, extracted or transmitted from it, is the sole property of S-MOS Systems Inc. and may not be used, copied, transmitted or otherwise made available to any other person, unless specifically allowed under license agreement with S-MOS Systems Inc. If furnished under a license, this document may be used and copied only in accordance with the terms of such license, and with the inclusion of this copyright notice. No title or ownership of the technology herein is transferred. The information in this document is subject to change without notice and should not be construed as a commitment by S-MOS Systems Inc. This document does not necessarily describe any current planned or future product by S-MOS Systems Inc., nor does it represent any commitment to implement any such product. 411-1.0 S-MOS Systems, Inc. · Tel: (408) 922-0200 · Fax: (408) 922-0238 · http://www.smos.com DS-1 THIS PAGE INTENTIONALLY BLANK DS-2 S-MOS Systems, Inc. · Tel: (408) 922-0200 · Fax: (408) 922-0238 · http://www.smos.com 411-1.0 SPC8106 SPC8106 Data Sheet s DESCRIPTION The SPC8106 SPC8106 is a versatile mixed voltage VGA graphics controller capable of driving liquid crystal displays, TFT displays and analog CRT monitors. The controller integrates all LCD interface, sequencing and color modulation logic into one small form factor 144 pin package. With the addition of an industry standard '477 compatible RAMDAC, the SPC8106 SPC8106 will also drive a VGA fixed frequency or multifrequency monitor. The target products for this device are price and power sensitive 80x86 microprocessor based portable personal computer or other specialized LCD systems where 320 x 200 to 640 x 480 x 256 color LCD panel displays are the major design criteria. s FEATURES · Low-power CMOS technology · Hardware VGA compatible · 8- or 16-bit ISA support · Supports one 256K x 16 80ns DRAM (self refresh optional) · 64 x 64 x 2-bit pixel hardware cursor · Two-terminal crystal or external oscillator support · Hardware or software power-down · Video BIOS, software driver and utility support · 144-pin QFP package · 9- or 12-bit color TFT panel interface for 640 x 480 · Single panel or dual panel interface for sizes 320 x 200 to 640 x 480 · On-chip 256 x 12-bit look-up table · 16 gray shades or 4096 colors by FRM · 64 gray shades by FRM and dithering · Two programmable gray-scale weightings: NTSC and Green-Only · Vertical centering and expansion for LCDs · Full CRT support with '477 compatible RAMDAC · Pin Compatible with the SPC8108F0C SPC8108F0C · Mixed voltage 3.3V/5V operation s SYSTEM BLOCK DIAGRAM CLOCKS MONOCHROME 3.3V or 5V ISA BUS 3.3V or 5V LCD PANEL SPC8106 SPC8106 3.3 V or 5V RAMDAC ANALOG 3.3V or 5V CRT DRAM 411-1.0 S-MOS Systems, Inc. · Tel: (408) 922-0200 · Fax: (408) 922-0238 · http://www.smos.com DS-3 Data Sheet SPC8106 SPC8106 s INTERFACE OPTIONS 25.175 MHz 7 pF PDCLK P[7:0] CLOCK /RD /WR R,G,B Bt477 RAMDAC OL[3:0] RS2 477/471 BLANK# HSYNC# VSYNC# MS[2:0] A[9:0] D[0:15] RAS# LCAS# UCAS# WE# /OE CRT MONITOR D[7:0] SUSPEND# IREF D[7:0] MEMCS16 MEMCS16# IOCS16 IOCS16# ALE BHE# P[7:0] PCLK DACRD# DACWR# OL[0] OL[1] OL23 RS2 D477 BLANK# YD LP WF XSCL UD[3:0] LD[3:0] LCDPWR# XSCL2 RS[1:0] CLKI2 SPC8106 SPC8106 LCD DISPLAY SA[1:0] SUSPEND# 32KHz 50% duty YD LP WF XSCL UD[3:0] LD[3:0] LCDPWR# XSCL2 IREFEN# MA[9:0] MD[15:0] RAS# LCAS# UCAS# WE# -MEMCS16 -MEMCS16 -IOCS16 -IOCS16 BALE -SHBE MEMEN IOEN# IOR# IOW# MEMR# MEMW# READY IRQ RESET A[16:0], LA[23:17] D[15:0] CLKI1 ISA BUS 7 pF 2 M CLKO1 2 M 16 Bit -REFRESH AEN -IOR -IOW -SMEMR -SMEMW IOCHRDY IRQ2 RESET DRV SA[16:0], LA[23:17] D[15:0] 7 pF CLKO2 7 pF 28.322 MHz italics = components required for CRT support 256K x 16 DRAM Note: Example implementation, actual may vary. DS-4 S-MOS Systems, Inc. · Tel: (408) 922-0200 · Fax: (408) 922-0238 · http://www.smos.com 411-1.0 SPC8106 SPC8106 Data Sheet s SUPPORTED RESOLUTIONS LCD Display Modes Mode No. Mode Type Font Characters Resolution 0 0+ 0+ 1 1+ 1+ 2 2+ 2+ 3 3+ 3+ 4 5 6 7 7+ 0D 0E 0F 10 11 12 13 100 101 108 Text Text Text Text Text Text Text Text Text Text Text Text Graphics Graphics Graphics Text Text Graphics Graphics Graphics Graphics Graphics Graphics Graphics Graphics Graphics Text 8x8 8 x 14 8 x 16 8x8 8 x 14 8 x 16 8x8 8 x 14 8 x 16 8x8 8 x 14 8 x 16 N/A N/A N/A 8 x 14 8 x 16 N/A N/A N/A N/A N/A N/A N/A N/A N/A 8x8 40 x 25 40 x 25 40 x 25 40 x 25 40 x 25 40 x 25 80 x 25 80 x 25 80 x 25 80 x 25 80 x 25 80 x 25 N/A N/A N/A 80 x 25 80 x 25 N/A N/A N/A N/A N/A N/A N/A N/A N/A 80 x 60 320 x 200 320 x 350 320 x 400 320 x 200 320 x 350 320 x 400 640 x 200 640 x 350 640 x 400 640 x 200 640 x 350 640 x 400 320 x 200 320 x 200 640 x 200 640 x 350 640 x 400 320 x 200 640 x 200 640 x 350 640 x 350 640 x 480 640 x 480 320 x 200 640 x 400 640 x 480 640 x 480 411-1.0 Displayed Gray Pixels Shades 640 x 400 640 x 350 640 x 400 640 x 400 640 x 350 640 x 400 640 x 400 640 x 350 640 x 400 640 x 400 640 x 350 640 x 400 640 x 400 640 x 400 640 x 400 640 x 350 640 x 400 640 x 400 640 x 400 640 x 350 640 x 350 640 x 480 640 x 480 640 x 400 640 x 400 640 x 480 640 x 480 16 16 16 16 16 16 16 16 16 16 16 16 4 4 2 2 2 16 16 2 16 2 16 64 64 64 16 Colors Memory Segment 16 16 16 16 16 16 16 16 16 16 16 16 4 4 2 2 2 16 16 2 16 2 16 256 256 256 16 B800 B800 B800 B800 B800 B800 B800 B800 B800 B800 B800 B800 B800 B800 B800 B000 B000 A000 A000 A000 A000 A000 A000 A000 A000 A000 B800 S-MOS Systems, Inc. · Tel: (408) 922-0200 · Fax: (408) 922-0238 · http://www.smos.com DS-5 Data Sheet SPC8106 SPC8106 CRT Display Modes Mode No. Mode Type Font 0 0+ 0+ 1 1+ 1+ 2 2+ 2+ 3 3+ 3+ 4 5 6 7 7+ 0D 0E 0F 10 11 12 13 100 101 108 Text Text Text Text Text Text Text Text Text Text Text Text Graphics Graphics Graphics Text Text Graphics Graphics Graphics Graphics Graphics Graphics Graphics Graphics Graphics Text 8x8 8 x 14 9 x 16 8x8 8 x 14 9 x 16 8x8 8 x 14 9 x 16 8x8 8 x 14 9 x 16 N/A N/A N/A 8 x 14 9 x 16 N/A N/A N/A N/A N/A N/A N/A N/A N/A 8x8 Characters Resolution 40 x 25 40 x 25 40 x 25 40 x 25 40 x 25 40 x 25 80 x 25 80 x 25 80 x 25 80 x 25 80 x 25 80 x 25 N/A N/A N/A 80 x 25 80 x 25 N/A N/A N/A N/A N/A N/A N/A N/A N/A 80 x 60 320 x 200 320 x 350 360 x 400 320 x 200 320 x 350 360 x 400 640 x 200 640 x 350 720 x 400 640 x 200 640 x 350 720 x 400 320 x 200 320 x 200 640 x 200 640 x 350 720 x 400 320 x 200 640 x 200 640 x 350 640 x 350 640 x 480 640 x 480 320 x 200 640 x 400 640 x 480 640 x 480 Displayed Pixels Colors Memory Segment 640x400 640x350 720x400 640x400 640x350 720x400 640x400 640x350 640x400 640x400 640x350 640x400 640x400 640x400 640x400 640x350 720x400 640x400 640x400 640x350 640x350 640x480 640x480 640x400 640x400 640 x 480 640 x 480 16 16 16 16 16 16 16 16 16 16 16 16 4 4 2 2 2 16 16 2 16 2 16 256 256 256 16 B800 B800 B800 B800 B800 B800 B800 B800 B800 B800 B800 B800 B800 B800 B800 B000 B000 A000 A000 A000 A000 A000 A000 A000 A000 A000 B800 s SUPPORTED LCD INTERFACES 8-Bit Interface Dual Panel Horizontal 640 DS-6 Vertical 400 480 4-Bit Interface Single Panel Single Panel Horizontal Vertical Horizontal Vertical 640 1 to 480 320 480 640 200 240 320 400 480 S-MOS Systems, Inc. · Tel: (408) 922-0200 · Fax: (408) 922-0238 · http://www.smos.com 411-1.0 411-1.0 A[23:0] M D[15:0] MA[9:0] DRAM CONTROL CLKO1 CLKI1 CLKO2 CLKI2 PDCLK D[15:0] 16-BIT 16-BIT BUS CONTROL POW ER SAVE CLOCK GENERATOR DISPLAY MEMORY INTERFACE ADDRESS GENERATOR MEMORY DECODER PORT DECODER MAP3 M AP0 GRAPHICS CONTROLLER CRT CONTROLLER SEQUENCER AUXILIARY PORTS ATTRIBUTE CONTROLLER VGA PORTS LOOK-UP TABLE CRT INTERFACE LCD PANEL INTERFACE HARDWARE CURSOR P[7:0] PCLK HSYNC # VSYNC # BLANK # DACRD # DACW # R OL23 OL0 OL1 D477 RS2 UD[3:0] LD[3:0] XSCL XSCL2 LP YD W F LCDPW # R SPC8106 SPC8106 Data Sheet s BLOCK DIAGRAM S-MOS Systems, Inc. · Tel: (408) 922-0200 · Fax: (408) 922-0238 · http://www.smos.com DS-7 Data Sheet SPC8106 SPC8106 s FUNCTIONAL BLOCK DESCRIPTION The Sequencer The Sequencer generates internal signals to synchronize the operation of the chip as well as the signals to control the timing of the display DRAM. The Sequencer also arbitrates between CPU and video display accesses to the DRAM. It contains registers that allows selection of character font set, control the structure of the video memory and allow write masking of the individual plane of memory. CRT Controller The CRT Controller generates the horizontal and vertical synchronization signals for the CRT, single panel or dual panel LCD display and character and/or pixel addresses for display data from DRAM. CRT Interface The CRT interface aligns CRT signals to the Pixel Clock and generates the I/O Control signals for CPU access to the RAMDAC. Address Generator The Address Generator takes the display and refresh addresses from the CRT Controller and converts them into RAS and CAS addresses for the display DRAM, and multiplexes these display accesses with CPU memory accesses. Attributes Controller The Attributes Controller takes in pixel and attribute information from the Graphics Controller and display DRAM and formats the data into pixel information which then passes through the lookup table. It also controls display character attributes such as blink, underline and horizontal pixel panning. Graphics Controller The Graphics Controller supplies display memory data to the Attributes Controller during display time and provides data translation between the CPU bus and the display memory during CPU read or write access cycles. Display Memory Interface The Display Memory Interface is a bridge by which the chip communicates with the DRAM. It contains buffers that are used to store recently fetched DRAM data. Memory Decoder The Memory Decoder monitors the CPU-bus activity and decodes cycles for the display DRAM. It supplies memory access control signals to the Sequencer. Port Decoder The Port Decoder decodes CPU-bus I/O cycles to provide enable and write strobes for the onchip I/O registers. DS-8 S-MOS Systems, Inc. · Tel: (408) 922-0200 · Fax: (408) 922-0238 · http://www.smos.com 411-1.0 SPC8106 SPC8106 Data Sheet Auxiliary Ports The Auxiliary Ports are I/O registers used to control functions of the chip beyond the basic VGA register set. Registers are included for controlling the LCD interface circuits as well as the power save modes. VGA Ports The VGA Ports contain the Miscellaneous Output Status register and the Video Subsystem Enable register used in VGA mode. Clock Generation The Clock Generation contains oscillator support for external crystals. Power Save The Power Save block contains the logic to implement six software controlled and one hardware controlled power down modes. Lookup Table The Lookup Table consists of a memory array of 256 locations of 12 bits each and hardware to convert VGA palette writes to gray-scale values. LCD Interface The LCD Interface block converts the display video data from the Lookup Table into LCD display data. It also generates control signals necessary to drive single or dual-panel LCD panels. For monochrome LCD panels, the LCD interface block generates a maximum 64 gray shades through frame rate modulation and dithering techniques. For color LCD panels, the LCD interface block generates 256 simultaneous colors from a possible 4096 colors through frame rate modulation. Hardware Cursor The Hardware Cursor block generates a 4 gray shade or color cursor/sprite that can be overlaid on the LCD or CRT display. The cursor is 64 x 64 pixels or optionally expanded to 128 x 128 through pixel replication. 411-1.0 S-MOS Systems, Inc. · Tel: (408) 922-0200 · Fax: (408) 922-0238 · http://www.smos.com DS-9 Data Sheet SPC8106 SPC8106 s DC SPECIFICATIONS Absolute Maximum Ratings Symbol VDD VIN VOUT TOPR TSTG TSOL Parameter Supply Voltage Input Voltage Output Voltage Operating Temperature Storage Temperature Soldering Temperature/Time Rating VSS-0.3 to +7.0 VSS-0.3 to VDD+0.3 VSS-0.3 to VDD+0.3 0 to +70 -65 to +150 260 for 10sec max at lead Units V V V °C °C °C Recommended Operating Conditions Symbol HVDD LVDD VIN TOPR IOPR Parameter Supply Voltage Supply Voltage Input Voltage Operating Temperature Average Current Consumption Condition VSS = 0V VSS = 0V VSS Vcc Core = 3.3V VCC I/O = 5.0V Min Typ Max 4.5 5.0 5.5 3.0 3.3 3.6 VSS -VDD 0 25 70 typical ICore = 52.31 typical IIO = 13.85 Units V V V °C mA Input Specifications Symbol VIL VIH VIL VIH VT+ VTVH VT+ VTVH IIZ CIN RPU2 RPU3 RPD DS-10 DS-10 Parameter Low Level Input Voltage (CMOS inputs) High Level Input Voltage (CMOS inputs) Low Level Input Voltage (TTL inputs) High Level Input Voltage (TTL inputs) Positive-going Threshold (CMOS Schmitt inputs) Negative-going Threshold (CMOS Schmitt inputs) Hysteresis Voltage (CMOS Schmitt inputs) Positive-going Threshold (TTL Schmitt inputs) Negative-going Threshold (TTL Schmitt inputs) Hysteresis Voltage (TTL Schmitt inputs) Input Leakage Current Input Pin Capacitance Pull Up Resistance Pull Up Resistance Pull Down Resistance Condition VDD = MIN VDD = MAX Min Typ VDD = 5.0 V 0.8 2.0 VDD = 5.0 V V 4.0 V 0.8 V 0.3 V VDD = 5.0 VDD = 5.0 V 3.5 VDD = 5.0 VDD = 5.0 Units 1.0 VDD = MIN VDD = MAX Max 3.0 V 0.6 V 0.1 V VDD = MAX VIH = VDD VIL = VSS -1 VDD = 5.0 V VDD = 5.0 V VDD = 5.0 V 50 100 100 1 8 100 200 200 µA 200 400 400 pF k k k S-MOS Systems, Inc. · Tel: (408) 922-0200 · Fax: (408) 922-0238 · http://www.smos.com 411-1.0 SPC8106 SPC8106 Data Sheet Output Specifications Symbol IOL2 Parameter Low Level Output Current IOH2 High Level Output Current IOL3 Low Level Output Current IOH3 High Level Output Current IOL4 Low Level Output Current IOH4 High Level Output Current IOZ Condition VOL=VSS+0.4V 6.0 Units mA TS2 VOH=VDD-0.4V -2.0 mA TS2 VOL=VSS+0.4V 12.0 mA TS3 VOH=VDD-0.4V -4.0 mA TS3 VOL=VSS+0.4V 24.0 mA TS4 VOH=VDD-0.4V -8.0 mA TS4 Output Leakage Current VOH=VDD Min Typ -1 Max 1 µA or VOL=VSS COUT CBID 411-1.0 Output Pin Capacitance Bidirectional Pin Capacitance 8 10 pF pF S-MOS Systems, Inc. · Tel: (408) 922-0200 · Fax: (408) 922-0238 · http://www.smos.com DS-11 DS-11 Data Sheet SPC8106 SPC8106 SPC8106F0C SPC8106F0C IOVSS MS0 MD4 MD11 MD5 MD10 MD6 MD9 MD7 MD8 LCAS# WE# UCAS# RAS# MA8 MA0 MA7 MA1 MA6 MA2 MA5 MA3 IOVDD IOVSS MA4 IREFEN# RS2 DACWR# BLANK# DACRD# VSYNC# HSYNC# D477 OL0 OL1 COREVDD IOVDD LA17 LA18 LA19 LA20 LA21 LA22 LA23 XSCL2 YD VSS XSCL LP COREVDD WF LD0 LD1 LD2 LD3 MA9 LCDPWR# UD0 UD1 UD2 UD3 P0 P1 P2 P3 P4 P5 P6 P7 PCLK OL23 VSS COREVDD A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 IOVSS IOVDD D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 RESET READY PDCLK IOVSS 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 VSS A3 A2 A1 A0 IRQ ALE BHE# IOCS16 IOCS16# MEMCS16 MEMCS16# MEMW# MEMEN MEMR# IOW# IOR# IOEN# COREVDD CLKO1 CLKI1 VSS VSS CLKO2 CLKI2 COREVDD SUSPEND# MS2 MS1 MD0 MD15 MD1 MD14 MD2 MD13 MD3 MD12 IOVDD 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 s SPC8106F0C SPC8106F0C PIN OUTSOURCE: 8110_PINOUT_08.CAN DS-12 DS-12 S-MOS Systems, Inc. · Tel: (408) 922-0200 · Fax: (408) 922-0238 · http://www.smos.com 411-1.0 SPC8106 SPC8106 Data Sheet s PIN DESCRIPTION Key A I O = Analog = Input = Output I/O = Bidirectional P = Power CPU Interface Pin Name A[0:16], LA[17:23] Type Pin # I 104.107, 110.122, 2.4, 5.8 ALE I 102 D[0:15] I/O 125.140 MEMEN I 97 IOR# IOW# MEMR# I I I 94 95 96 MEMW# I 98 IOEN# I 93 READY O 142 RESET I 141 IRQ O 103 MEMCS16 MEMCS16# O 411-1.0 99 Description CPU bus address inputs. In Suspend Mode, the Address inputs are internally masked off. If the value on MD[5] at RESET = 1, then the ALE input pin is used to internally latch LA[19:17] and A[16:2], allowing these address bits to be driven by the processor address bus. If the value on MD[5] at RESET = 0, then standard ISA address timing is assumed, where pins A[0:16], LA[17:23] should be connected to the ISA bus signals SA[0:16], LA[17:23] respectively. ISA Bus Address Latch Enable. In Suspend Mode the ALE input is disabled. If the value on MD[5] at RESET = 1, then the ALE input is used to internally latch LA[19:17] and A[16:2], allowing these address bits to be driven by the processor address bus. In this mode, the processor ADS# output should be connected to this pin. If the value on MD[5] at RESET = 0, then standard ISA address timing is assumed, and only the LA[19:17] inputs are internally latched. 16 bit ISA-Bus data bus. These lines are driven by the chip only during read cycles, and are in a hi-Z state at all other times. In Suspend Mode, these inputs are internally masked off. ISA Bus Memory Enable. This signal should be connected to the REFRESH# signal on the ISA bus. When this signal is low (e.g. during a system memory refresh cycle), memory address decoding is disabled. ISA Bus I/O Read Strobe. In Suspend Mode the IOR# input is disabled. ISA Bus I/O Write Strobe. In Suspend Mode the IOW# input is disabled. ISA Bus System Memory Read Strobe. In Suspend Mode the MEMR# input is disabled. ISA Bus System Memory Write Strobe. In Suspend Mode the MEMW# input is disabled. ISA Bus I/O Enable. This input should be connected to the ISA bus AEN signal. When this signal is high, I/O address decoding is disabled. In Suspend Mode, the IOEN# input is disabled. ISA Bus READY signal. This output is driven low to force the CPU to insert wait states during memory cycles. READY is released to high-Z after a transfer is complete. The active high Reset signal from the CPU clears all internal registers and forces all signals to their inactive state. ISA Bus Vertical Interrupt. When enabled, a Vertical Retrace Interrupt will cause this signal to be driven from a logic 0 state to a logic 1 (rising-edge triggered interrupt). Once set, this interrupt must be cleared by a bit in the CRTC registers. A control bit in the Auxiliary Registers allows this output to be optionally disabled (tristated). This pin also is used for the output of the NAND tree in pin test mode. ISA Bus Memory Chip Select 16. Address inputs LA[23:17] are decoded to drive this output low when a valid memory address (AXXXXh, BXXXXH) appears on the bus. S-MOS Systems, Inc. · Tel: (408) 922-0200 · Fax: (408) 922-0238 · http://www.smos.com DS-13 DS-13 Data Sheet SPC8106 SPC8106 Pin Name IOCS16 IOCS16# Type Pin # O 100 BHE# I 101 Description ISA Bus I/O Chip Select 16. Address inputs A[15:0] and IOEN# are decoded to drive this output low when a valid SPC8106 SPC8106 I/O register address appears on the bus,. Note that I/O addresses 3C6h-3C9h do not result in IOCS16 IOCS16# being driven low (i.e. RAMDAC and internal LUT register reads and writes are 8 bit cycles). ISA Bus Byte High Enable. In Suspend Mode the BHE# input is disabled. Video Memory Interface Pin Name MA[0:9] Type O MD[0:15] I/O RAS# LCAS# (LWE#) O O Pin # 57, 55, 53, 51, 48, 52, 54, 56, 58, 20 81, 79, 77, 75, 70, 68, 66, 64, 63, 65, 67, 69, 74, 76, 78, 80 59 62 UCAS# (CAS#) O 60 WE# (UWE#) O 61 Pin Name CLKI1 Type I Pin # 90 CLKO1 O 91 CLKI2 I 86 CLKO2 O 87 Description Multiplexed row/column address bits for video display memory. Data bits for video display memory. The output drivers of these pins are placed into a high-impedance state when RESET is high, or when the Sequencer is in a reset state. On the falling edge of RESET, the values on MD[3:0] and MD[12:9] are latched into a read-only Auxiliary Register and are available to be read as configuration inputs. Also, the value on MD[8:4] and MD[15:13] are used to configure various hardware options. See "Summary of Configuration Options" on page 18 for details. DRAM Row Address Strobe for single 256Kx16 DRAM. Multiple Function: DRAM Column Address Strobe for low byte (LCAS#). For alternate function see "Multiple Function Pin Descriptions" on page 19. Multiple Function: DRAM Column Address Strobe for high byte (UCAS#). For alternate function see "Multiple Function Pin Descriptions" on page 19. Multiple Function: DRAM Write Enable Strobe (WE#). For alternate function see "Multiple Function Pin Descriptions" on page 19. Clock Inputs DS-14 DS-14 Description This pin, along with CLKO1 is the 25.175 MHz 2-terminal crystal interface when using a 2-terminal crystal as the clock input. If an external oscillator is used as a clock source, then this pin is the clock input. This pin, along with CLKI1 is the 25.175 MHz2-terminal crystal interface when using a 2-terminal crystal as the clock input. If an external oscillator is used as a clock source, then this pin should be left unconnected. This pin, along with CLKO2 is the 28.322 MHz 2-terminal crystal interface when using a 2-terminal crystal as the clock input. If an external oscillator is used as a clock source, then this pin is the clock input. This pin, along with CLKI2 is the 28.322 MHz 2-terminal crystal interface when using a 2-terminal crystal as the clock input. If an external oscillator is used as a clock source, then this pin should be left unconnected. S-MOS Systems, Inc. · Tel: (408) 922-0200 · Fax: (408) 922-0238 · http://www.smos.com 411-1.0 SPC8106 SPC8106 Data Sheet LCD Panel Interface Pin Name YD Type O Pin # 10 LP O 13 XSCL O 12 XSCL2 O 9 UD[0:3] O 22.25 UD[4:7] O 26.29 LD[0:3] O 16.19 LD[4:7] O 30.33 LCDPWR# O 21 WF O 15 411-1.0 Description Vertical Scanning Start Pulse output. A logic 1 on this signal, sampled by the LCD module on the falling edge of LP, is used by the panel row drivers (Y drivers) to indicate the start of the vertical frame. Latch Pulse output. The falling edge of this signal is used to latch a row of display data in the LCD module's column driver shift registers and to turn on the row driver (Y driver) for that line. Shift Clock for LCD data. Display data is clocked out of the chip on the rising edge of this signal, to be shifted into the LCD panel module column drivers (X drivers) on each falling edge. This second shift clock is used together with XSCL in 8-bit single color panel mode to shift in alternate sets of display data. XSCL2 is also used alone as the shift clock in 8-bit dual color panel mode and 4-bit single color panel mode. Upper panel display data for dual panel - dual drive mode. For 8-bit single panelsingle drive mode, these bits are the most significant 4-bits of the 8-bit output data to the panel (data[7:4]). For 4-bit single panel mode, these bits are the 4 bits of data output to the panel. For 16-bit LCD modes, these outputs are the multiplexed upper panel data if MD[7]=1 at RESET, or the lower nibble of the upper panel data if MD[7]=0 at RESET. When MD[7]=0 at RESET, these pins are the upper nibble of the 16-bit LCD mode upper panel data. Lower panel display data for dual panel-dual drive mode. For 8-bit single panelsingle drive mode, these bits are the least significant 4 bits of the 8-bit output data to the panel (data[3:0]). For 4-bit single panel mode, these outputs are driven low. For 16-bit LCD modes, these outputs are the multiplexed lower panel data if MD[7]=1 at RESET, or the lower nibble of the lower panel data if MD[7]=0 at RESET. When MD[7]=0 at RESET, these pins are the upper nibble of the 16-bit LCD mode lower panel data. LCD power control. In normal operation this signal is driven low to enable an external LCD power supply. This signal is driven high when the chip is put into any power save mode, when Auxiliary Register 06 bit 0 is set to 1, or when the Sequencer is in a reset state. It can be used externally to turn off the panel supply voltage and backlight. After a RESET, this signal is held high until the CRTC is programmed and running. LCD Backplane Bias signal. This output toggles once every n LP periods, as programmed in Auxiliary Register [0D]. S-MOS Systems, Inc. · Tel: (408) 922-0200 · Fax: (408) 922-0238 · http://www.smos.com DS-15 DS-15 Data Sheet SPC8106 SPC8106 External CRT/RAMDAC Interface Pin Name P[0:7] Type O Pin # 26.33 PCLK BLANK# O O 34 44 HSYNC# O 41 VSYNC# O 42 DACRD# O 43 DACWR# O 45 RS2 O 46 OL[0:1] I/O 39, 38 OL23 O D477 O IREFEN# O MS[2:0] I/O DS-16 DS-16 Description When MD[7]=1 at RESET, these pins are the Pixel Data outputs. These 8 bits are connected to the pixel select inputs of the external RAMDAC. Pixel Clock. Pixel data is clocked out of the chip on the falling edge of PCLK. Blank output. This output is clocked out on the falling edge of PCLK and is driven low during display blanking periods. Horizontal Sync. This output is clocked out on the falling edge of PCLK and is driven to indicate the horizontal retrace period. The polarity of this signal is determined by a control bit in register 3C2h. Vertical Sync. This output is clocked out on the falling edge of PCLK and is driven to indicate the vertical retrace period. The polarity of this signal is determined by a control bit in register 3C2h. RAMDAC Read Strobe. This signal goes low when a valid read access to the VGA RAMDAC is decoded by the chip. RAMDAC Write Strobe. This signal goes low when a valid write access to the VGA RAMDAC is decoded by the chip. Register Select 2 output. This output should be connected to the RS2 input of the RAMDAC (Bt477 or equivalent). The logic level on this output may be set by setting Auxiliary Register [0B] bit 3. This signal is required to allow CPU access the control and overlay registers of the external RAMDAC. Multiple Function: Overlay Select outputs 1:0 When MD[13]=0 at RESET, these pins are outputs used to provide sprite/HW cursor function on the CRT display. In this case, these outputs should be connected to the OL[0:1] inputs of the RAMDAC (Bt477 or equivalent). They are used by the sprite circuitry to access the overlay registers in the RAMDAC. For alternate function see "Multiple Function Pin Descriptions" on page 19. 35 Overlay Select output 2/3. This output should be connected to both the OL2 and OL3 inputs of the RAMDAC (Bt477 or equivalent). This signal is used by the sprite circuitry to access the overlay registers in the RAMDAC.For alternate function see "Multiple Function Pin Descriptions" on page 19. 40 477 Control Signal. This output should be connected to the 477/471 input of the RAMDAC (Bt477 or equivalent). This signal is used to access the control register of the RAMDAC and to allow it to be powered down. The logic level on this output can be controlled by setting Auxiliary Register [0B] bit 4, and is also controlled by the power save logic. 47 IREF Enable output. This signal is used to control the external current reference source required by the RAMDAC, allowing powering down the analog circuitry when not required. When this signal is driven low, the external current reference should be enabled. When this signal is high, the external current reference should be shut off. 83, 82, 71 Monitor Sense inputs. These signals should be connected to the monitor sense lines from the CRT monitor cable. The status of these bits is readable in Auxiliary Register [08] bits 2:0, and is used by BIOS software to determine the presence and type of monitor connected. Optionally, the SENSE output of the RAMDAC may be connected to one of these inputs to allow the BIOS to read the SENSE signal and detect the monitor. MS[2:1] can be forced low by the DCC2 monitor support bits in Auxiliary Register [10] bits 1:0. S-MOS Systems, Inc. · Tel: (408) 922-0200 · Fax: (408) 922-0238 · http://www.smos.com 411-1.0 SPC8106 SPC8106 Data Sheet Power Save Mode Control Pin Name Type SUSPEND# I Pin # 84 PDCLK 143 I Description A low level on this pin puts the chip into a hardware power down mode. The SUSPEND# signal overrides any software initiated power down modes, and disables the ISA-Bus interface inputs except RESET. Address and Data inputs are also masked when this signal is low. When in Suspend Mode the UD(3:0), LD(3:0), XSCL, XSCL2, LP, YD and WF signals are driven into a high impedance or low state (configurable) and the LCDPWR# signal is driven high. Power Down Clock. This input may be used to provide a low frequency clock for generating refresh in Power Save Modes 4 and Suspend, as an optional alternative to using the pixel clock or MEMEN input as the refresh clock source. This clock input should be driven by either by a 32 kHz 50% duty cycle clock source, or a 64 kHz clock source with a high period as short as possible (but > minimum RAS low pulse width) to minimize DRAM current consumption during refresh. The PDCLK input is used to directly generate the RAS and CAS pulses during Power Save Mode 4 and Suspend. Power Supply Pin Name COREVDD IOVDD VSS IOVSS 411-1.0 Type Pin # P 14, 37, 85, 92, 109 P 1, 50, 73, 124 P 11, 36, 88, 89, 108 P 49, 72, 123, 144 Description VDD supply for core logic. VDD supply for interface pins. VSS supply for core logic. VSS supply for interface pins. S-MOS Systems, Inc. · Tel: (408) 922-0200 · Fax: (408) 922-0238 · http://www.smos.com DS-17 DS-17 Data Sheet SPC8106 SPC8106 Pin Mapping for Various Display Modes Display Mode SPC8106 SPC8106 Pin Name CRT LCD RGBI 12-bit RGB None None VSYNC# HSYNC# None (forced 0) PCLK None (forced 0) None (forced 0) None (forced 0) None (forced 0) None (forced 0) D[3] D[2] D[1] D[0] None None None None None VSYNC# HSYNC# None (forced 0) PCLK R[3] B[3] B[2] B[1] R[2] G[3] G[2] G[1] R[1] B[0] G[0] R[0] TFT 12-bit 9-bit 12-bit AUX[00]b5=1 AUX[00]b5=1 AUX[0B]b1=0 VSYNC# HSYNC# YD LP WF XCSL XCSL2 UD[3] UD[2] UD[1] UD[0] LD[3] LD[2] LD[1] LD[0] OL0 OL1 OL23 VSYNC# HSYNC# None None None None None None None None None None None None None OL0 OL1 OL23 None None YD LP WF XCSL XCSL2 UD[3] UD[2] UD[1] UD[0] LD[3] LD[2] LD[1] LD[0] None None None None None VSYNC# HSYNC# DATAEN PANCLK R[2] B[2] B[1] B[0] R[1] G[2] G[1] G[0] R[0] None None None AUX[0B]b1=1 None None VSYNC# HSYNC# DATAEN PANCLK R[3] B[3] B[2] B[1] R[2] G[3] G[2] G[1] R[1] B[0] G[0] R[0] VSYNC# HSYNC# None None DATAEN PANCLK R[3] B[3] B[2] B[1] R[2] G[3] G[2] G[1] R[1] B[0] G[0] R[0] Mixed Voltage Configurations Core VDD 3.3 V 5.0 V I/O VDD 3.3 V 5.0 V OK OK NO OK Summary of Configuration Options Pin Name MD[3:0] MD[4] MD[5] MD[6] MD[7] MD[8] MD[12:9] MD[13] MD[14] MD[15] value on this pin at falling edge of RESET is used to configure: (1/0) values latched into read-only Aux Reg[0C] bits 3:0 for software use 16-bit I/O interface (1) / 8-bit I/O interface (0) A[19:2] latched internally by ALE (1) / standard ISA bus ALE - A[16:0] not latched (0) 2 CAS, 1 WE type DRAM (1) / 1 CAS, 2 WE type DRAM (0) support 16-bit panel with external logic (1) / support 16-bit panel directly (0) 5 V core operating voltage (1) / 3.3 V core operating voltage (0) values latched into read-only bits 7:4 of Aux Reg[0C] for software use pins 38, 39 used for ext. RC for 32 kHz PDCLK (1) / pins 38, 39 used for OL[1:0] (0) Internal PDCLK doubling disable (1) / enable (0) 3C3h used as video enable port (1) / 46E8h and 102h used as video enable port (0) These inputs have internal pullup resistors. Based on the value of the internal pull-ups, the external pull-down resistors if necessary, should be approximately 15K ohm. This value will provide the correct voltage levels on power-up without loading the DRAM Data lines (VDD = 5.0V). DS-18 DS-18 S-MOS Systems, Inc. · Tel: (408) 922-0200 · Fax: (408) 922-0238 · http://www.smos.com 411-1.0 SPC8106 SPC8106 Data Sheet Multiple Function Pin Descriptions Pin Name Function LCAS#, LWE# LCAS# MD Line Status MD6 = 1 LWE# UCAS#, CAS# UCAS# MD6 = 0 MD6 = 1 WE#, UWE# CAS# WE# UWE# OL0, P320, B0 OL0 P320 B0 OL1, P32I, G0 OL1 P32I G0 MD6 = 0 MD[6] = 1 MD[6] = 0 MD[13] = 0 AUX[00] b6=0 MD[13] = 1 MD[14] = 1 MD[13] = 0 AUX[00] b6=1 MD[13] = 0 AUX[00] b6=0 MD[13] = 1 MD[14] = 1 P[0:3} UD[4:7} MD[7] = 0 P[4:7] MD[7] = 1 LD[4:7] OL23, R0 MD[13] = 0 AUX[00] b6=1 MD[13] = 0 AUX[00] b6=0 MD[13] = 0 AUX[00] b6=1 MD[7] = 1 MD[7] = 0 OL23 R0 P[0:3] P[4:7] 411-1.0 Functional Description DRAM Column Address Strobe (Low Byte) DRAM Write Strobe (Low Byte) DRAM Column Address Strobe (High Byte) DRAM Column Address Strobe DRAM Write Strobe DRAM Write Strobe (High Byte) Overlay Bit 0. Used for CRT HW Cursor/Sprite support. 32 kHz Clock Output. Used with external RC when using external PDCLK support Data bit B0 for 12-bit TFT support Overlay Bit 1. Used for CRT HW Cursor/Sprite support 32 kHz Clock Input. Used with external RC when using external PDCLK support Data bit G0 for 12-bit TFT support Overlay Bit 2. Used for CRT HW Cursor/Sprite support. Data bit R0 for 12-bit TFT support Lower nibble of the CRT pixel data outputs Upper nibble of the 16-bit LCD mode upper panel data Upper nibble of the CRT pixel data outputs Upper nibble of the 16-bit LCD mode lower panel data S-MOS Systems, Inc. · Tel: (408) 922-0200 · Fax: (408) 922-0238 · http://www.smos.com DS-19 DS-19 Data Sheet SPC8106 SPC8106 Illustrated below are the display data output which are output from the UD0 to UD3, LD0/UD4 to LD3/UD7 and the display on the panel: UD3 UD2 UD1 UD0 UD3 UD2 UD1 UD0 LD3 LD2 LD1 LD0 Dual Panel - Top 8-bit Single Panel LD3 LD2 LD1 LD0 Dual Panel - Bottom UD3 UD2 UD1 UD0 4-bit Single Panel s LCD PANEL PIXELS 640 DOTS 1-1 1-2 1-639 1-640 2-1 2 -2 2-639 2-640 240 LINES U P P E R LC D P A N E L 240-1 241-1 240-2 2 40 - 639 240 - 640 241-2 2 41 - 639 241 - 640 4 80 - 639 480 - 640 (TO P V IE W ) 240 LINES LO W E R LC D P A N E L 480-1 DS-20 DS-20 480-2 S-MOS Systems, Inc. · Tel: (408) 922-0200 · Fax: (408) 922-0238 · http://www.smos.com 411-1.0 SPC8106 SPC8106 Data Sheet s MONOCHROME PASSIVE STN LCD PANEL INTERFACE 4-BIT SINGLE PANEL LP : 242 PULSES YD LP WF U D [3:0] LINE 1 LINE 2 LINE 3 LINE 4 LINE 239 LINE 1 LINE 240 LINE 2 LP WF XSCL: 80 CLOCK PERIODS XSCL UD3 1-1 1- 5 1 -317 UD2 1 -2 1-6 1 -318 UD1 1-3 1- 7 1 -319 UD0 1 -4 1 -8 1-320 Exam ple tim ing for a 320 x 240 panel 411-1.0 S-MOS Systems, Inc. · Tel: (408) 922-0200 · Fax: (408) 922-0238 · http://www.smos.com DS-21 DS-21 Data Sheet SPC8106 SPC8106 s MONOCHROME PASSIVE STN LCD PANEL INTERFACE 8-BIT SINGLE PANEL LP: 482 PULSES YD LP UD[3:0] LD[3:0] LINE 1 LINE 2 LINE 3 LINE 4 LINE 479 LINE 480 LINE 1 LINE 2 LP XSCL: 80 CLOCK PERIODS XSCL UD3 1-9 1-633 UD2 1-2 1-10 1-634 UD1 1-3 1-11 1-635 UD0 1-4 1-12 1-636 LD3 1-5 1-13 1-637 LD2 1-6 1-14 1-638 LD1 1-7 1-15 1-639 LD0 DS-22 DS-22 1-1 1-8 1-16 1-640 S-MOS Systems, Inc. · Tel: (408) 922-0200 · Fax: (408) 922-0238 · http://www.smos.com 411-1.0 SPC8106 SPC8106 Data Sheet s MONOCHROME PASSIVE STN LCD PANEL INTERFACE 8-BIT DUAL PANEL LP: 242 PULSES YD LP LINE 1 UD[3:0] LINE 2 LINE 3 LINE 4 LINE 241 LINE 242 LINE 243 LINE 244 LD[3:0] LINE 239 LINE 240 LINE 1 LINE 479 LINE 480 LINE 2 LINE 241 LINE 242 LP XSCL: 160 CLOCK PERIODS XSCL UD3 1-1 1-5 1-637 UD2 1-2 1-6 1-638 UD1 1-3 1-7 1-639 UD0 1-4 1-8 1-640 LD3 241-1 241-5 241-637 LD2 241-2 241-6 241-638 LD1 241-3 241-7 241-639 LD0 241-4 241-8 241-640 411-1.0 S-MOS Systems, Inc. · Tel: (408) 922-0200 · Fax: (408) 922-0238 · http://www.smos.com DS-23 DS-23 Data Sheet SPC8106 SPC8106 s COLOR STN LCD PANEL INTERFACE 4-BIT SINGLE PANEL LP : 242 PULSES YD LP WF U D [3:0] LINE 1 LINE 2 LINE 3 LINE 4 LINE 239 LINE 1 LINE 240 LINE 2 LP WF XSCL2: 240 CLOCK PERIODS XSCL 2 UD3 R1 G2 B3 B319 UD2 G1 B2 R4 R320 UD1 B1 R3 G4 G320 UD0 R2 G3 B4 B320 Exam ple tim ing for a 320 x 240 panel DS-24 DS-24 S-MOS Systems, Inc. · Tel: (408) 922-0200 · Fax: (408) 922-0238 · http://www.smos.com 411-1.0 SPC8106 SPC8106 Data Sheet s COLOR STN LCD PANEL INTERFACE 8-BIT SINGLE PANEL LP: 482 PULSES YD LP UD[3:0] LD[3:0] LINE 1 LINE 2 LINE 3 LINE 4 LINE 479 LINE 480 LINE 1 LINE 2 LP XSCL2: 120 CLOCK PERIODS XSCL2 XSCL: 120 CLOCK PERIODS XSCL UD3 1-R1 1-G1 1-G6 1-B6 1-B11 1-B11 1-R12 1-R12 1-B635 1-B635 1-R636 1-R636 UD2 1-B1 1-R2 1-R7 1-G7 1-G12 1-G12 1-B12 1-B12 1-G636 1-G636 1-B636 1-B636 UD1 1-G2 1-B2 1-B7 1-R8 1-R13 1-R13 1-G13 1-G13 1-R637 1-R637 1-G637 1-G637 UD0 1-R3 1-G3 1-G8 1-B8 1-B13 1-B13 1-R14 1-R14 1-B637 1-B637 1-R638 1-R638 LD3 1-B3 1-R4 1-R9 1-G9 1-G14 1-G14 1-B14 1-B14 1-G638 1-G638 1-B638 1-B638 LD2 1-G4 1-B4 1-B9 1-R10 1-R10 1-R15 1-R15 1-G15 1-G15 1-R639 1-R639 1-G639 1-G639 LD1 1-R5 1-G5 1-G10 1-G10 1-B10 1-B10 1-B15 1-B15 1-R16 1-R16 1-B639 1-B639 1-R640 1-R640 LD0 1-B5 1-R6 1-R11 1-R11 1-G11 1-G11 1-G16 1-G16 1-B16 1-B16 1-G640 1-G640 1-B640 1-B640 411-1.0 S-MOS Systems, Inc. · Tel: (408) 922-0200 · Fax: (408) 922-0238 · http://www.smos.com DS-25 DS-25 Data Sheet SPC8106 SPC8106 s COLOR STN LCD PANEL INTERFACE 8-BIT DUAL PANEL LP: 242 PULSES YD LP LINE 1 UD[3:0] LINE 2 LINE 3 LINE 4 LINE 241 LINE 242 LINE 243 LINE 244 LD[3:0] LINE 239 LINE 240 LINE 1 LINE 479 LINE 480 LINE 2 LINE 241 LINE 242 LP XSCL2: 480 CLOCK PERIODS XSCL2 UD3 1-G2 1-B3 1-R637 1-R637 1-G638 1-G638 1-B639 1-B639 UD2 1-G1 1-B2 1-R4 1-G637 1-G637 1-B638 1-B638 1-R640 1-R640 UD1 1-B1 1-R3 1-G4 1-B637 1-B637 1-R639 1-R639 1-G640 1-G640 UD0 1-R2 1-G3 1-B4 1-R638 1-R638 1-G639 1-G639 1-B640 1-B640 LD3 241-R1 241-R1 241-G2 241-G2 241-B3 241-B3 241-R637 241-R637 241-G638 241-G638 241-B639 241-B639 LD2 241-G1 241-G1 241-B2 241-B2 241-R4 241-R4 241-G637 241-G637 241-B638 241-B638 241-R640 241-R640 LD1 241-B1 241-B1 241-R3 241-R3 241-G4 241-G4 241-B637 241-B637 241-R639 241-R639 241-G640 241-G640 LD0 DS-26 DS-26 1-R1 241-R2 241-R2 241-G3 241-G3 241-B4 241-B4 241-R638 241-R638 241-G639 241-G639 241-B640 241-B640 S-MOS Systems, Inc. · Tel: (408) 922-0200 · Fax: (408) 922-0238 · http://www.smos.com 411-1.0 SPC8106 SPC8106 Data Sheet s COLOR STN LCD PANEL INTERFACE 16-BIT 16-BIT SINGLE PANEL LP: 482 PULSES YD LP UD[7:0] LD[7:0] LINE 1 LINE 2 LINE 3 LINE 4 LINE 479 LINE 480 LINE 1 LINE 2 LP XSCL: 120 CLOCK PERIODS XSCL UD7 1-R1 1-G6 1-B11 1-B11 1-R625 1-R625 1-G630 1-G630 1-B635 1-B635 UD6 1-B1 1-R7 1-G12 1-G12 1-B625 1-B625 1-R631 1-R631 1-G636 1-G636 UD5 1-G2 1-B7 1-R13 1-R13 1-G626 1-G626 1-B631 1-B631 1-R637 1-R637 UD3 1-R3 1-G8 1-B13 1-B13 1-R627 1-R627 1-G632 1-G632 1-B637 1-B637 UD3 1-B3 1-R9 1-G14 1-G14 1-B627 1-B627 1-R633 1-R633 1-G638 1-G638 UD2 1-G4 1-B9 1-R15 1-R15 1-G628 1-G628 1-B633 1-B633 1-R639 1-R639 UD1 1-R5 1-G10 1-G10 1-B15 1-B15 1-R629 1-R629 1-G634 1-G634 1-B639 1-B639 UD0 1-B5 1-R11 1-R11 1-G16 1-G16 1-B629 1-B629 1-R635 1-R635 1-G640 1-G640 LD7 1-G1 1-B6 1-R12 1-R12 1-G625 1-G625 1-B630 1-B630 1-R636 1-R636 LD6 1-R2 1-G7 1-B12 1-B12 1-R626 1-R626 1-G631 1-G631 1-B636 1-B636 LD5 1-B2 1-R8 1-G13 1-G13 1-B626 1-B626 1-R632 1-R632 1-G637 1-G637 LD4 1-G3 1-B8 1-R14 1-R14 1-G627 1-G627 1-B632 1-B632 1-R638 1-R638 LD3 1-R4 1-G9 1-B14 1-B14 1-R628 1-R628 1-G633 1-G633 1-B638 1-B638 LD2 1-B4 1-R10 1-R10 1-G15 1-G15 1-B628 1-B628 1-R634 1-R634 1-G639 1-G639 LD1 1-G5 1-B10 1-B10 1-R16 1-R16 1-G629 1-G629 1-B634 1-B634 1-R640 1-R640 LD0 1-R6 1-G11 1-G11 1-B16 1-B16 1-R630 1-R630 1-G635 1-G635 1-B640 1-B640 411-1.0 S-MOS Systems, Inc. · Tel: (408) 922-0200 · Fax: (408) 922-0238 · http://www.smos.com DS-27 DS-27 Data Sheet SPC8106 SPC8106 s COLOR STN LCD PANEL INTERFACE 16-BIT 16-BIT DUAL PANEL LP: 242 PULSES YD LP LINE 1 UD[7:0] LINE 2 LINE 3 LINE 4 LINE 241 LINE 242 LINE 243 LINE 244 LD[7:0] LINE 239 LINE 240 LINE 1 LINE 479 LINE 480 LINE 2 LINE 241 LINE 242 LP XSCL: 240 CLOCK PERIODS XSCL UD7 1-B3 1-G6 1-R633 1-R633 1-B635 1-B635 1-G638 1-G638 UD6 1-G1 1-R4 1-B6 1-G633 1-G633 1-R636 1-R636 1-B638 1-B638 UD5 1-B1 1-G4 1-R7 1-B633 1-B633 1-G636 1-G636 1-R639 1-R639 UD4 1-R2 1-B4 1-G7 1-R634 1-R634 1-B636 1-B636 1-G639 1-G639 UD3 1-G2 1-R5 1-B7 1-G634 1-G634 1-R637 1-R637 1-B639 1-B639 UD2 1-B2 1-G5 1-R8 1-B634 1-B634 1-G637 1-G637 1-R640 1-R640 UD1 1-R3 1-B5 1-G8 1-R635 1-R635 1-B637 1-B637 1-G640 1-G640 UD0 1-G3 1-R6 1-B8 1-G635 1-G635 1-R638 1-R638 1-B640 1-B640 LD7 241-R1 241-R1 241-B3 241-B3 241-G6 241-G6 241-R633 241-R633 241-B635 241-B635 241-G638 241-G638 LD6 241-G1 241-G1 241-R4 241-R4 241-B6 241-B6 241-G633 241-G633 241-R636 241-R636 241-B638 241-B638 LD5 241-B1 241-B1 241-G4 241-G4 241-R7 241-R7 241-B633 241-B633 241-G636 241-G636 241-R639 241-R639 LD4 241-R2 241-R2 241-B4 241-B4 241-G7 241-G7 241-R634 241-R634 241-B636 241-B636 241-G639 241-G639 LD3 241-G2 241-G2 241-R5 241-R5 241-B7 241-B7 241-G634 241-G634 241-R637 241-R637 241-B639 241-B639 LD2 241-B2 241-B2 241-G5 241-G5 241-R8 241-R8 241-B634 241-B634 241-G637 241-G637 241-R640 241-R640 LD1 241-R3 241-R3 241-B5 241-B5 241-G8 241-G8 241-R635 241-R635 241-B637 241-B637 241-G640 241-G640 LD0 DS-28 DS-28 1-R1 241-G3 241-G3 241-R6 241-R6 241-B8 241-B8 241-G635 241-G635 241-R638 241-R638 241-B640 241-B640 S-MOS Systems, Inc. · Tel: (408) 922-0200 · Fax: (408) 922-0238 · http://www.smos.com 411-1.0 SPC8106 SPC8106 Data Sheet s COLOR STN LCD PANEL INTERFACE 16-BIT 16-BIT SINGLE PANEL WITH EXTERNAL CIRCUIT LP : 482 PULSES YD LP WF P ix el D a ta LINE 1 LINE 2 LINE 3 LINE 4 LINE 479 LINE 480 LINE 1 LINE 2 SPC8106 SPC8106 OUTPUTS LP WF XSCL: 120 CLOCKS XSC L 1-B3 1-B 635 1-G 638 1-B1 1-G4 1-G 636 1-R 639 UD1 1-G2 1-R 5 1-R 637 UD0 1-R 3 1-B5 1-B637 1-B637 1-G640 1-G640 LD3 1-G1 1-R4 1-R636 1-R636 1-B 638 LD2 1-R2 1-B4 1-B636 1-B636 1-G 639 LD1 1-B 2 1-G5 1-G 637 1-R640 1-R640 LD0 1-G3 1-R 6 1-R638 1-R638 UD3 1-R 1 UD2 1-B 639 1-B640 1-B640 1-B635 1-B635 1-B 1 1-G636 1-G636 U D5 1-G2 1-R637 1-R637 EXTERNAL CIRCUIT U D4 1-R 3 1-B 637 (required when MD[7]=1 at reset) UD3 1-B3 1-G 638 UD2 1-G4 1-R 639 UD1 1-R5 1-B 639 UD0 1-B5 1-G640 1-G640 1-G637 1-G637 LD 4 1-G 3 1-R638 1-R638 LD 3 1-R 4 1-B638 1-B638 LD 2 1-B4 1-G639 1-G639 LD 1 1-G5 1-R640 1-R640 LD 0 1-R6 1-B640 1-B640 411-1.0 S-MOS Systems, Inc. · Tel: (408) 922-0200 · Fax: (408) 922-0238 · http://www.smos.com CK 1-B 2 XSCL LD 5 D LD 6 Q 1-R 636 1-B 636 UD[3:0] LD[3:0] 1-G1 1-R 2 FROM SPC8106 SPC8106 LD 7 UD[3:0] LD[3:0] TO16-BIT UD[7:4] PANEL LD[7:4] 1-R1 U D6 16-bit PANEL INPUTS U D7 DS-29 DS-29 Data Sheet SPC8106 SPC8106 s COLOR STN LCD PANEL INTERFACE 16-BIT 16-BIT DUAL PANEL WITH EXTERNAL CIRCUIT LP : 242 PULSES YD LP WF P ix el D a ta LINE 1/241 LINE 2/242 LINE 3/243 LINE 4/244 LINE 239/479 LINE 240/480 LINE 1/241 LINE 2/242 WF XSCL: 240 CLOCKS XSC L UD3 1-R 1 1-G2 1-B 3 1-G 638 1-B 639 UD2 1-G1 1-B2 1-R4 1-B 638 1-R 640 UD1 1-B 1 1-R 3 1-G 4 1-R639 1-R639 1-G640 1-G640 UD0 1-R 2 1-G3 1-B 4 1-G 639 1-B 640 241-R1 241-R1 241-G2 241-G2 241-B3 241-B3 241G638 241G638 241B639 241B639 LD2 241-G1 241-G1 241-B2 241-B2 241-R4 241-R4 241B 638 241R640 241R640 LD1 241-B 241-B 1 241-R 241-R 3 241-B 241-B 4 241R639 241R639 241G640 241G640 LD0 241-R 241-R 2 241-G3 241-G3 241-B 241-B 4 241G639 241G639 241B640 241B640 LD3 U D7 1-R 1 1-G638 1-G638 1-B638 1-B638 1-B1 1-R639 1-R639 U D4 1-R2 1-G639 1-G639 UD3 1-G2 1-B 639 UD2 1-B 2 1-R 640 UD1 1-R3 1-G 640 UD0 1-G3 1-B 640 LD 7 241-R1 241-R1 241-G 241-G 6 38 LD 6 241-G1 241-G1 241-B 241-B 638 (required when MD[7]=1 at reset) LD 3 241-G2 241-G2 241B 639 LD 2 241-B 241-B 2 241R 640 LD 1 241-R3 241-R3 241G640 241G640 LD 0 241-G3 241-G3 241B 640 CK 241-R 241-R 639 241-G 241-G 6 39 S-MOS Systems, Inc. · Tel: (408) 922-0200 · Fax: (408) 922-0238 · http://www.smos.com UD[3:0] LD[3:0] FROM SPC8106 SPC8106 411-1.0 XSCL 241-B1 241-B1 241-R2 241-R2 D LD 5 LD 4 DS-30 DS-30 EXTERNAL CIRCUIT Q 1-G1 U D5 16-BIT 16-BIT PANEL INPUTS U D6 UD[3:0] LD[3:0] TO16-BIT UD[7:4] PANEL LD[7:4] SPC8106 SPC8106 OUTPUTS LP SPC8106 SPC8106 Data Sheet s COLOR TFT PANEL INTERFACE Auxiliary Register [00] bit 5=1 and Auxiliary Register [0B] bit 1=1 HRTC 350 PULSES 61 HRTC PULSES 350 Line Mode VSYNC#* HSYNC#* LINE 1 R [3:0], G [3:0], B[3:0]* 34 HRTC PULSES 400 Line Mode LINE 350 HRTC 400 PULSES VSYNC#* HSYNC#* LINE 1 R[3:0], G [3:0 ], B[3:0]* 480 Line Mode LINE 400 HRTC 480 PULSES 34 HRTC PULSES VSYNC#* HSYNC#* LINE 1 R[3:0], G [3:0 ], B[3:0]* LINE 480 H S Y N C#* (400, 480) H S Y NC#* (35 0) CLOCK: 640 CLOCKS PANCLK* DATAEN* R[3:0] * 1-1 1-2 1-640 G [3:0] * 1-1 1-2 1-640 B [3 :0] * 1-1 1-2 1-640 9-bit panels use data bits [2:0] * Refer to "Pin Mapping for Various Display Modes" on page 15 for actual pin names 411-1.0 S-MOS Systems, Inc. · Tel: (408) 922-0200 · Fax: (408) 922-0238 · http://www.smos.com DS-31 DS-31 Data Sheet SPC8106 SPC8106 s COLOR TFT PANEL INTERFACE Auxiliary Register [00] bit 5=1 and Auxiliary Register [0B] bit 1=0 UP TO 1023 HRTC PULSES 2 ~ 6 5 HRTC PULSES VSYNC#*2 HSYNC#*2 LINE 1 *2 R[3:0], G [3:0 ], B[3:0] LINE 480 H S Y N C#*2 CLOCK: 640 CLOCKS 112 OR 160 CLOCKS PANCLK*2 *1 DATAEN*2 R[3:0] *2 1-1 1-2 1-3 1-4 1-640 2-1 2-2 G [3:0] *2 1-1 1-2 1-3 1-4 1-640 2-1 2-2 B [3 :0] *2 1-1 1-2 1-3 1-4 1-640 2-1 2-2 9-bit panels use data bits [2:0] *1 - This number is controlled by Auxiliary Register [06] bit 2 *2 - Refer to "Pin Mapping for Various Display Modes" on page 15 for actual pin names DS-32 DS-32 S-MOS Systems, Inc. · Tel: (408) 922-0200 · Fax: (408) 922-0238 · http://www.smos.com 411-1.0 SPC8106 SPC8106 Data Sheet s RGB MODE PANEL INTERFACE 12-BIT 12-BIT RGB MODE PANEL 240 HSYNC: PULSES 2 HSYNC: PULSES VSYNC#* HSYNC#* R[3:0], G[3:0], B[3:0]* LINE 1/241 LIN E 2/24 2 L IN E 3 /2 4 3 L IN E 4 /2 4 4 L IN E 2 3 9 / 4 7 9 PCLK : 1280 CLOCKS L IN E 2 4 0 /4 8 0 LIN E 1/24 1 L IN E 2/2 4 2 PCLK : 224 CLOCKS HSYNC#* PCLK* R[3:0]* 1 -1 241-1 1-2 241-2 1-640 2 41-640 2-1 242 -1 2-2 G[3:0]* 1-1 241-1 1-2 241 -2 1-640 2 41-640 2-1 242 -1 2-2 B[3:0]* 1 -1 241-1 1-2 241-2 1-640 2 41-640 2-1 242 -1 2-2 * Refer to "Pin Mapping for Various Display Modes" on page 15 for actual pin names 411-1.0 S-MOS Systems, Inc. · Tel: (408) 922-0200 · Fax: (408) 922-0238 · http://www.smos.com DS-33 DS-33 Data Sheet SPC8106 SPC8106 s RGBI MODE DUAL PANEL INTERFACE RGBI MODE DUAL PANEL HSYNC: PULSES 240 2 HSYNC: PULSES VSYNC#* HSYNC#* I, R, G, B* LIN E 1/24 1 LIN E 2/24 2 LINE 3/243 LINE 4/24 4 L IN E 2 3 9 / 4 7 9 PCLK : 1280 CLOCKS LIN E 24 0/48 0 LIN E 1/24 1 LIN E 2/24 2 PCLK : 224 CLOCKS HSYNC#* PCLK* I, R,G, B* 1-1 241-1 1-2 241-2 1 -640 241-640 2-1 242-1 2-2 * Refer to "Pin Mapping for Various Display Modes" on page 15 for actual pin names DS-34 DS-34 S-MOS Systems, Inc. · Tel: (408) 922-0200 · Fax: (408) 922-0238 · http://www.smos.com 411-1.0 SPC8106 SPC8106 Data Sheet s PACKAGE DIMENSIONS (SPC8106F0C SPC8106F0C) QFP17 QFP17 - 144 pin Unit: mm 22.0±0.4 20.0 ±0.1 73 108 72 20.0 ±0.1 22.0 ±0.4 109 Index 3.0 Max 0.15 ±0.05 144 37 1 0.5 ±0.1 0.2 ±0.1 36 0.1 0~10° 0.5 ±0.2 1.0 Actual Size 411-1.0 S-MOS Systems, Inc. · Tel: (408) 922-0200 · Fax: (408) 922-0238 · http://www.smos.com DS-35 DS-35 S-MOS assumes no responsibility or liability for (1) any errors or inaccuracies contained in the information herein and (2) the use of the information or a portion thereof in any application, including any claim for (a) copyright or patent infringement or (b) direct, indirect, special or consequential damages. There are no warranties extended or granted by this document. The information herein is subject to change without notice from S-MOS. April 1997 Copyright ©1997 S-MOS Systems Inc. All rights reserved. Printed in U.S.A. VDC DS-36 DS-36 S-MOS Systems, Inc. · Tel: (408) 922-0200 · Fax: (408) 922-0238 · http://www.smos.com 411-1.0 SPC8106 SPC8106 LCD/CRT VGA CONTROLLER Hardware Functional Specification Drawing Office No. X12-SP-001-07 X12-SP-001-07 Copyright © 1997 S-MOS Systems Inc. All rights reserved. VDC This document, and any text derived, extracted or transmitted from it, is the sole property of S-MOS Systems Inc. and may not be used, copied, transmitted or otherwise made available to any other person, unless specifically allowed under license agreement with S-MOS Systems Inc. If furnished under a license, this document may be used and copied only in accordance with the terms of such license, and with the inclusion of this copyright notice. No title or ownership of the technology herein is transferred. The information in this document is subject to change without notice and should not be construed as a commitment by S-MOS Systems Inc. This document does not necessarily describe any current planned or future product by S-MOS Systems Inc., nor does it represent any commitment to implement any such product. 411-1.0 S-MOS Systems, Inc. · Tel: (408) 922-0200 · Fax: (408) 922-0238 · http://www.smos.com X12-SP-001-07 X12-SP-001-07 SP1-1 THIS PAGE INTENTIONALLY BLANK SP1-2 S-MOS Systems, Inc. · Tel: (408) 922-0200 · Fax: (408) 922-0238 · http://www.smos.com X12-SP-001-07 X12-SP-001-07 411-1.0 SPC8106 SPC8106 Hardware Functional Specification TABLE OF CONTENTS 1.0 INTRODUCTION 1.1 Scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.0 FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.1 2.2 2.3 2.4 Technology . System . . . Compatibility . Display Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 .10 .11 .11 3.0 OVERVIEW DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.1 3.2 Typical System Implementation Diagram . . . . . . . . . . . . . . . . . . .13 Internal Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . .14 4.0 PINOUT DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.0 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.1 5.2 5.3 5.4 5.5 Configuration Options . . . . . . . Power On / Reset Options . . . . . Multiple Function Pin Descriptions . . Pin Mapping for Various Display Modes Video Memory Interface Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 .22 .23 .24 .24 6.0 D.C. CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.0 A.C. CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13 7.14 7.15 7.16 7.17 7.18 7.19 7.20 7.21 411-1.0 CPU Bus Cycle Timing - 8-bit Memory and I/O . . . . . . . . . . . . . . CPU Bus Cycle Timing - 16-bit Memory . . . . . . . . . . . . . . . . CPU Bus Cycle Timing - 16-bit I/O . . . . . . . . . . . . . . . . . . Bus Cycle Timing - 16-bit Memory (Modified Address Timing) . . . . . . . . CPU Bus Cycle Timing - 16-bit I/O (Modified Address Timing) . . . . . . . . DRAM Read Cycle Timing - Non-Page Mode . . . . . . . . . . . . . . DRAM Read Cycle Timing - Page Mode . . . . . . . . . . . . . . . . DRAM Write Cycle Timing . . . . . . . . . . . . . . . . . . . . . DRAM Refresh Timing I . . . . . . . . . . . . . . . . . . . . . . DRAM Refresh Timing II . . . . . . . . . . . . . . . . . . . . . . RAMDAC Interface Timing . . . . . . . . . . . . . . . . . . . . . Power Save Mode LCD Signal Timing - Software Power Save Modes . . . . Power Save Mode CRT Signal Timing - Software Power Save Modes . . . . Power Save Mode LCD Signal Timing - Hardware Suspend Mode . . . . . . Power Save Mode CRT Signal Timing - Hardware Suspend Mode . . . . . . Clock Input Requirements . . . . . . . . . . . . . . . . . . . . . . LCD Interface Timing - 4-Bit Single Monochrome Panel . . . . . . . . . . LCD Interface Timing - 8-Bit Single/Dual Monochrome Panel . . . . . . . . LCD Interface Timing - 16-Bit Single/Dual, 8-Bit Dual, 4-Bit Single Color Panels LCD Interface Timing - 8-bit Single Color Panel . . . . . . . . . . . . . Interface Timing - TFT Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 .30 .32 .34 .35 .36 .37 .38 .39 .39 .41 .42 .43 .45 .46 .48 .49 .50 .52 .54 .56 S-MOS Systems, Inc. · Tel: (408) 922-0200 · Fax: (408) 922-0238 · http://www.smos.com X12-SP-001-07 X12-SP-001-07 SP1-3 Hardware Functional Specification SPC8106 SPC8106 8.0 LCD INTERFACE OPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 9.0 POWER SAVE MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 9.1 Power Save Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 10.0 SOFTWARE CONSIDERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . 82 10.1 10.2 10.3 10.4 10.5 10.6 Display Modes Supported . . . . . . . . . DoubleScan Support . . . . . . . . . . . Standard VGA Register Considerations . . . . Background . . . . . . . . . . . . . . . I/O Register Summary . . . . . . . . . . . LCD Gray Scale/Color Lookup Table Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 . 83 . 84 . 85 . 89 122 11.0 PIN TEST MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 12.0 PACKAGE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 13.0 KNOWN LIMITATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Appendix A SP1-4 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . 128 S-MOS Systems, Inc. · Tel: (408) 922-0200 · Fax: (408) 922-0238 · http://www.smos.com X12-SP-001-07 X12-SP-001-07 411-1.0 SPC8106 SPC8106 Hardware Functional Specification LIST OF TABLES Table 0-1 Table 0-2 Table 0-3 Table 0-4 Table 0-5 Table 0-6 Table 0-7 Table 0-8 Table 0-9 Table 0-10 Table 0-11 Table 0-12 Table 0-13 Table 0-14 Table 0-15 Table 0-16 Table 0-17 Table 0-18 Table 0-19 Table 0-20 Table 0-21 Table 0-22 Table 0-23 Table 0-24 Table 0-25 Table 0-26 Table 0-27 Table 0-28 Table 0-29 Table 0-30 Table 0-31 Table 0-32 Table 0-33 Table 0-34 Table 0-35 Table 0-36 Table 0-37 Table 0-38 Table 0-39 Table 0-40 Table 0-41 Table 0-42 Table 0-43 Table 0-44 Table 0-45 Table 0-46 Table 0-47 Table 0-48 Table 0-49 Table 0-50 Table 0-51 Table 0-52 411-1.0 CPU Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Video Memory Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LCD Panel Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External CRT/RAMDAC Interface Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Save Mode Control Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mixed Voltage Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Summary of Power On / Reset Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multiple Function Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Display Modes Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Video Memory Interface Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DRAM Configuration Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10x8 DRAM Address Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9x9 DRAM Address Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CPU Bus Cycle Timing - 8-bit Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CPU Bus Cycle Timing - 16-bit Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CPU Bus Cycle Timing - 16-bit I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CPU Bus Cycle Timing - 16-bit Memory, Modified Address Timing . . . . . . . . . . . . . . . . . . CPU Bus Cycle Timing - 16-bit I/O - Modified Address Timing. . . . . . . . . . . . . . . . . . . . . . DRAM Read Cycle Timing - Non-Page Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DRAM Read Cycle Timing - Page Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DRAM Write Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DRAM Refresh Timing I (generated from CLKI, Sequence running . . . . . . . . . . . . . . . . . . DRAM Refresh Timing II (Sequencer stopped) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RAMDAC Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Save Mode LCD Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Save Mode CRT Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Suspend Mode LCD Signal Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Suspend Mode CRT Signal Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Input Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LCD Interface Timing - 4-Bit Single Monochrome Panel . . . . . . . . . . . . . . . . . . . . . . . . . . LCD Interface Timing - 8-Bit Single/Dual Monochrome Panel . . . . . . . . . . . . . . . . . . . . . . LCD Interface Timing - 16-Bit Single/Dual, 8-Bit Dual, 4-Bit Single Color Panels . . . . . . . LCD Interface Timing - 8-bit Single Color Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TFT Interface Timing when AUX[00]b5=1 and AUX[0B]b1=1. . . . . . . . . . . . . . . . . . . . . . . TFT Interface Timing when AUX[00]b5=1 and AUX[0B]b1=0. . . . . . . . . . . . . . . . . . . . . . . Software Power Save Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LCD Only (no CRT attached) - AUX[0B] bits 1,0 = 01 . . . . . . . . . . . . . . . . . . . . . . . . . . . . LCD Only (no CRT attached) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CRT Only (LCD off) - AUX[0B] bits 1,0 = 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CRT Only (LCD off) - AUX[0B] bits 1,0 = 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LCD Display Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CRT Display Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DoubleScan Supported Video Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Display Enable Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Panel Configuration Bit Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PSM4/S Refresh Clock Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . S-MOS Systems, Inc. · Tel: (408) 922-0200 · Fax: (408) 922-0238 · http://www.smos.com X12-SP-001-07 X12-SP-001-07 16 17 18 18 19 21 21 22 22 23 24 24 25 25 25 26 26 26 27 29 31 33 34 35 36 37 38 39 40 41 42 44 45 47 48 49 51 53 55 57 57 71 76 77 78 79 82 83 84 90 92 93 SP1-5 Hardware Functional Specification Table 0-53 Table 0-54 Table 0-55 Table 0-56 Table 0-57 Table 0-58 Table 0-59 Table 0-60 Table 0-61 Table 0-62 Table 0-63 Table 0-64 Table 0-65 Table 0-66 Table 0-67 Table 0-68 SP1-6 SPC8106 SPC8106 Horizontal Non-Display Period Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Sprite Page Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Display Enable Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Clock Select Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Sprite/HW Cursor Address Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Sprite/HW Cursor Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Pixel Bit Memory Packing Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 LCD Lookup Table Function Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Color Mode Writes (AUX[02] bit 6 = 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Color Mode Reads (AUX[02] bit 6 = 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 GS Weighting Modes 0 Writes (AUX[02] bit 6 = 1 and AUX[01] bit 4 = 0) . . . . . . . . . . . . 119 GS Weighting Mode 0 Reads (AUX[02] bit 6 = 0 and AUX[01] bit 4 = 0). . . . . . . . . . . . . 120 GS Weighting Mode 1 Writes (AUX[02] bit 6 = 0 and AUX[01] bit 4 = 1) . . . . . . . . . . . . . 120 GS Weighting Mode 1 Reads (AUX[02] bit 6 = 0 and AUX[01] bit 4 = 1). . . . . . . . . . . . . 120 Palette Location Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Pin Test Input Order in NAND Tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 S-MOS Systems, Inc. · Tel: (408) 922-0200 · Fax: (408) 922-0238 · http://www.smos.com X12-SP-001-07 X12-SP-001-07 411-1.0 SPC8106 SPC8106 Hardware Functional Specification LIST OF FIGURES Figure 1 : Typical System Implementation Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Figure 2 : Typical System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Figure 3 : Pinout Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Figure 4 : CPU Bus Cycle Timing - 8-bit Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Figure 5 : CPU Bus Cycle Timing - 16-bit Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Figure 6 : CPU Bus Cycle Timing - 16-bit I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Figure 7 : CPU Bus Cycle Timing - 16-bit Memory, Modified Address Timing . . . . . . . . . . . . . . . . . . .34 Figure 8 : CPU Bus Cycle Timing - 16-bit I/O - Modified Address Timing . . . . . . . . . . . . . . . . . . . . . . .35 Figure 9 : DRAM Read Cycle Timing - Non-Page Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Figure 10 : DRAM Read Cycle Timing - Page Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 Figure 11 : DRAM Write Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 Figure 12 : DRAM Refresh Timing I (generated from CLKI, Sequence running) . . . . . . . . . . . . . . . . .39 Figure 13 : DRAM Refresh Timing II (Sequencer stopped). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 Figure 14 : RAMDAC Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 Figure 15 : Power Save Mode LCD Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 Figure 16 : Power Save Mode CRT Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 Figure 17 : Suspend Mode LCD Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 Figure 18 : Suspend Mode CRT Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 Figure 19 : Clock Input Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 Figure 20 : LCD Interface Timing - 4-Bit Single Monochrome Panel . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Figure 21 : LCD Interface Timing - 8-Bit Single/Dual Monochrome Panel . . . . . . . . . . . . . . . . . . . . . .50 Figure 22 : LCD Interface Timing - 16-Bit Single/Dual, 8-Bit Dual, 4-Bit Single Color Panels . . . . . . . .52 Figure 23 : LCD Interface Timing - 8-bit Single Color Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 Figure 24 : Interface Timing - TFT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 Figure 25 : 4-bit Single Monochrome Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 Figure 26 : 4-bit Single Color Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 Figure 27 : 8-bit Single Monochrome Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 Figure 28 : 8-bit Dual Monochrome Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 Figure 29 : 8-bit Single Color Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 Figure 30 : 8-bit Dual Color Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 Figure 31 : External Circuit Required for 16-Bit Panel When MD[7]=1 at RESET . . . . . . . . . . . . . . . . .63 Figure 32 : 16-bit Single Color Panel Timing with External Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 Figure 33 : 16-bit Dual Color Panel Timing with External Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 Figure 34 : 16-bit Single Color Panel Timing without External Circuit . . . . . . . . . . . . . . . . . . . . . . . . . .66 Figure 35 : 16-bit Dual Color Panel Timing without External Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . .67 Figure 36 : Color TFT Panel Timing (when AUX[00]b5=1 and AUX[0B]b1=1). . . . . . . . . . . . . . . . . . . .68 Figure 37 : Color TFT Panel Timing (when AUX[00]b5=1 and AUX[0B]b1=0). . . . . . . . . . . . . . . . . . . .69 Figure 38 : 12-bit RGB Mode LCD Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 Figure 39 : RGBI Mode Dual LCD Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 Figure 40 : LCD Gray Scale Lookup Table Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122 Figure 41 : SPC8106 SPC8106 Pin Test Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124 Figure 42 : 144 Pin QFP17 QFP17 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126 411-1.0 S-MOS Systems, Inc. · Tel: (408) 922-0200 · Fax: (408) 922-0238 · http://www.smos.com X12-SP-001-07 X12-SP-001-07 SP1-7 THIS PAGE INTENTIONALLY BLANK SP1-8 S-MOS Systems, Inc. · Tel: (408) 922-0200 · Fax: (408) 922-0238 · http://www.smos.com X12-SP-001-07 X12-SP-001-07 411-1.0 SPC8106 SPC8106 Hardware Functional Specification 1.0 INTRODUCTION 1.1 Scope This is the Functional Specification for the SPC8106 SPC8106 LCD VGA Controller Chip. Included in this document are timing diagrams, AC and DC characteristics, register descriptions, and power management descriptions. This document is intended for two audiences; Video Subsystem Designers and Software Developers. 411-1.0 S-MOS Systems, Inc. · Tel: (408) 922-0200 · Fax: (408) 922-0238 · http://www.smos.com X12-SP-001-07 X12-SP-001-07 SP1-9 Hardware Functional Specification 2.0 FEATURES 2.1 SPC8106 SPC8106 Technology · low power CMOS · 3.3 and 5 volt operation · · 2.2 3.3 V core and 5 V I/O operation · · 5 V core and I/O operation 3.3 V core and I/O operation 144 pin QFP17 QFP17 surface mount package System · 8- or 16-bit ISA CPU data bus interface · programmable 64x64x2-bit hardware sprite, or 64x64x2-bit hardware cursor · two 2-terminal crystal inputs for internal oscillators, maximum 28.322 MHz frequency. External crystal oscillators also supported · interfaces to a single 256Kx16 DRAM (70 ns for 3.3 V I/O and Core, 80 ns for 5 V I/O and Core, 1024x256x16 or 512x512x16). Access to full 512Kbytes of video memory allowed · selectable DRAM interface configurations: 2 CAS/1 WE, or 1 CAS/2 WE · selectable 256 cycle/4 ms or 256 cycle/32 ms DRAM refresh rate, or low power self-refresh mode (for DRAMs supporting self-refresh) · 32 kHz 50% duty cycle power down clock support during Power Save Mode 4 and Suspend mode · one hardware plus six software initiated power save modes · ability to place external RAMDAC in power save mode · low power consumption. · 3C3h and 46E8h video enable registers supported · all output pins (except clock interface) can be tri-stated and driven as inputs to allow board level pin testing SP1-10 SP1-10 S-MOS Systems, Inc. · Tel: (408) 922-0200 · Fax: (408) 922-0238 · http://www.smos.com X12-SP-001-07 X12-SP-001-07 411-1.0 SPC8106 SPC8106 2.3 Hardware Functional Specification Compatibility · support for all standard VGA video modes on LCD or CRT · support for some extended VESA video modes · external VGA RAMDAC (Bt477 or equivalent) required for CRT modes · proprietary internal 256x6 gray scale lookup table provided for monochrome LCD modes · proprietary internal 256x12 color lookup table provided for color LCD modes · programmable hardware mapping of VGA palette-style writes to 64 level LCD gray scale values for monochrome LCD modes · 64 gray shades on monochrome LCD in mode 13h (16 gray shades by FRM + dithering) · hardware vertical expansion of 400 line graphics and text modes on LCD · vertical interrupt function on IRQ pin supported 2.4 Display Support · supports 8-bit 640x480 single panel-single drive and dual panel-dual drive monochrome and color LCD displays · supports 16-bit 640x480 single panel-single drive and dual panel-dual drive color LCD displays · supports 4-bit single panel-single drive monochrome and color LCD displays · additional LCD panel sizes supported via programmable horizontal and vertical panel size configuration registers · supports color 9/12-bit TFT displays, RGBI and 12-bit RGB mode displays · analog CRT monitors supported for standard VGA modes with an external RAMDAC · DoubleScan mode-simultaneous display of CRT and single panel LCD 411-1.0 S-MOS Systems, Inc. · Tel: (408) 922-0200 · Fax: (408) 922-0238 · http://www.smos.com SP1-11 SP1-11 X12-SP-001-07 X12-SP-001-07 Hardware Functional Specification 3.0 SPC8106 SPC8106 OVERVIEW DESCRIPTION The SPC8106 SPC8106 is a 3.3/5 V LCD video controller based on VGA architecture and optimized for driving a 640x480 LCD panel display. VGA standard mode functionality is supported using standard IBM VGA parameters. A proprietary 256 x 6 bit gray scale lookup table is provided to allow remapping of the 64 possible gray shades displayed on a monochrome LCD panel. For color LCD modes, an internal 256x12 bit VGA-style lookup table is provided (4 bits each of R, G, and B). An interface to an external RAMDAC is also provided to allow connecting a standard VGA monitor to the system. The target markets for this device are small, cost sensitive mixed voltage sub-notebook computers, or other specialized consumer products where low cost, low power consumption, low component count, and the ability to run most VGA software on a 640x480 LCD panel display are the major design considerations. This chip is intended to operate mainly in planar graphics modes (e.g. mode 12H), and will display 16 levels of gray, or 64 levels of gray in mode 13h on a monochrome LCD display, or up to 256 colors out of a palette of 4096 colors on a color LCD display. With an external RAMDAC, standard VGA modes are supported on a CRT display. SP1-12 SP1-12 S-MOS Systems, Inc. · Tel: (408) 922-0200 · Fax: (408) 922-0238 · http://www.smos.com X12-SP-001-07 X12-SP-001-07 411-1.0 SPC8106 SPC8106 3.1 Hardware Functional Specification Typical System Implementation Diagram The following figure shows a typical system implementation with SPC8106 SPC8106. 25.175 MHz 7 pF PDCLK P[7:0] PCLK DACRD# DACWR# OL[0] OL[1] OL23 RS2 D477 BLANK# P[7:0] CLOCK /RD /WR OL[3:0] R,G,B Bt477 RAMDAC RS2 477/471 BLANK# RS[1:0] SUSPEND# IREF HSYNC# VSYNC# MS[2:0] A[9:0] D[0:15] RAS# LCAS# UCAS# WE# /OE CRT MONITOR D[7:0] ALE BHE# YD LP WF XSCL UD[3:0] LD[3:0] LCDPWR# XSCL2 SA[1:0] 32KHz 50% duty MEMCS16 MEMCS16# IOCS16 IOCS16# YD LP WF XSCL UD[3:0] LD[3:0] LCDPWR# XSCL2 D[7:0] SUSPEND# SPC8106 SPC8106 MA[9:0] MD[15:0] RAS# LCAS# UCAS# WE# BALE -SHBE CLKI2 IOEN# IOR# IOW# MEMR# MEMW# READY IRQ RESET A[16:0], LA[23:17] D[15:0] LCD DISPLAY IREFEN# MEMEN AEN -IOR -IOW -SMEMR -SMEMW IOCHRDY IRQ2 2 M CLKO1 -REFRESH CLKI1 ISA BUS -MEMCS16 -MEMCS16 -IOCS16 -IOCS16 7 pF 2 M 16 Bit RESET DRV SA[16:0], LA[23:17] D[15:0] 7 pF CLKO2 7 pF 28.322 MHz italics = components required for CRT support 256K x 16 DRAM Figure 1 : Typical System Implementation Diagram Source: 8106f0c_sys_blk_01.can 411-1.0 S-MOS Systems, Inc. · Tel: (408) 922-0200 · Fax: (408) 922-0238 · http://www.smos.com SP1-13 SP1-13 X12-SP-001-07 X12-SP-001-07 X12-SP-001-07 X12-SP-001-07 DRAM CONTROL MA[9:0] MD[15:0] PDCLK CLKO1 CLKI1 CLKO2 CLKI2 D[15:0] POWER SAVE CLOCK GENERATOR MEMORY DECODER PORT DECODER DISPLAY MEMORY INTERFACE ADDRESS GENERATOR MAP 3 MAP 0 GRAPHICS CONTROLLER CRT CONTROLLER SEQUENCER AUXILIARY PORTS ATTRIBUTE CONTROLLER VGA PORTS LOOK-UP TABLE CRT INTERFACE LCD PANEL INTERFACE HARDWARE CURSOR P[7:0] PCLK HSYNC # VSYNC # BLANK # DACRD # DACWR # OL23 OL0 OL1 D477 RS2 UD[3:0] LD[3:0] XSCL LP YD WF LCDPWR # 3.2 16-BIT 16-BIT BUS CONTROL A[23:0] Hardware Functional Specification SPC8106 SPC8106 Internal Block Diagram Figure 2 : Typical System Block Diagram Source: 8108fblk.drw SP1-14 SP1-14 S-MOS Systems, Inc. · Tel: (408) 922-0200 · Fax: (408) 922-0238 · http://www.smos.com 411-1.0 SPC8106 SPC8106 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 IOVSS MS0 MD4 MD11 MD5 MD10 MD6 MD9 MD7 MD8 LCAS# WE# UCAS# RAS# MA8 MA0 MA7 MA1 MA6 MA2 SPC8106 SPC8106 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 COREVDD WF LD0 LD1 LD2 LD3 MA9 LCDPWR# UD0 UD1 UD2 UD3 P0 P1 P2 P3 P4 P5 P6 P7 PCLK OL23 VSS MA5 MA3 IOVDD IOVSS MA4 IREFEN# RS2 DACWR# BLANK# DACRD# VSYNC# HSYNC# D477 OL0 OL1 COREVDD IOVDD LA17 LA18 LA19 LA20 LA21 LA22 LA23 XSCL2 YD VSS XSCL LP 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 COREVDD A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 IOVSS IOVDD D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 RESET READY PDCLK IOVSS MEMCS16 MEMCS16# MEMW# MEMEN MEMR# IOW# IOR# IOEN# COREVDD CLKO1 CLKI1 VSS VSS CLKO2 CLKI2 COREVDD SUSPEND# MS2 MS1 MD0 MD15 MD1 MD14 MD2 MD13 MD3 MD12 IOVDD 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 A2 A1 A0 IRQ ALE BHE# IOCS16 IOCS16# VSS A3 107 PINOUT DIAGRAM 108 4.0 Hardware Functional Specification Figure 3 : Pinout Diagram Source: 8106f0c_po_02.can Some pins have dual use - default configuration is shown. See "Multiple Function Pin Descriptions" on page 23 for details. Package type: 144 pin surface mount QFP17 QFP17 411-1.0 S-MOS Systems, Inc. · Tel: (408) 922-0200 · Fax: (408) 922-0238 · http://www.smos.com SP1-15 SP1-15 X12-SP-001-07 X12-SP-001-07 Hardware Functional Specification 5.0 SPC8106 SPC8106 PIN DESCRIPTION Key C TTL TTLS TSx = = = = CMOS level input TTL level input TTL level input with hysteresis Tri-state CMOS level driver, x denotes driver type - see "D.C. CHARACTERISTICS" on page 26 for rating. TSxUy = Tri-state CMOS level driver with pull up resistor (y=2: 100 k typical., y=3: 200 k typ.), x denotes driver type - see "D.C. CHARACTERISTICS" on page 26 for rating. TSxD = Tri-state CMOS level driver with pull down resistor (200 k typ.), x denotes driver type - see "D.C. CHARACTERISTICS" on page 26 for rating. pins marked with a * in the Type column are outputs in normal operation mode, but for pin test mode, these outputs are placed in a high impedance state and these pins become inputs. Therefore these pins are actually bidirectional, although only the normal output mode is shown in this table. For these pins, the input type for this test mode is shown in parentheses (*). See "PIN TEST MODE" on page 124 for more information. Table 0-1 CPU Interface Pins Pin Name A[0:16], LA[17:23] Type Pin # I 104~107, 110~122, 2~4, 5~8 Drv TTL ALE I 102 TTL D[0:15] I/O 125~140 TTL /TS2 MEMEN I 97 TTLS IOR# I 94 TTLS IOW# I 95 TTLS MEMR# I 96 TTLS Description CPU bus address inputs. In Suspend Mode, the Address inputs are internally masked off. If the value on MD[5] at RESET = 1, then the ALE input pin is used to internally latch LA[19:17] and A[16:2], allowing these address bits to be driven by the processor address bus. If the value on MD[5] at RESET = 0, then standard ISA address timing is assumed, where pins A[0:16], LA[17:23] should be connected to the ISA bus signals SA[0:16], LA[17:23] respectively. ISA Bus Address Latch Enable. In Suspend Mode the ALE input is disabled. If the value on MD[5] at RESET = 1, then the ALE input is used to internally latch LA[19:17] and A[16:2], allowing these address bits to be driven by the processor address bus. In this mode, the processor ADS# output should be connected to this pin. If the value on MD[5] at RESET = 0, then standard ISA address timing is assumed, and only the LA[19:17] inputs are internally latched. 16 bit ISA-Bus data bus. These lines are driven by the chip only during read cycles, and are in a hi-Z state at all other times. In Suspend Mode, these inputs are internally masked off. ISA Bus Memory Enable. This signal should be connected to the REFRESH# signal on the ISA bus. When this signal is low (e.g. during a system memory refresh cycle), memory address decoding is disabled. ISA Bus I/O Read Strobe. In Suspend Mode the IOR# input is disabled. ISA Bus I/O Write Strobe. In Suspend Mode the IOW# input is disabled. ISA Bus System Memory Read Strobe. In Suspend Mode the MEMR# input is disabled. SP1-16 SP1-16 S-MOS Systems, Inc. · Tel: (408) 922-0200 · Fax: (408) 922-0238 · http://www.smos.com X12-SP-001-07 X12-SP-001-07 411-1.0 SPC8106 SPC8106 Hardware Functional Specification Table 0-1 CPU Interface Pins (Continued) Pin Name MEMW# Type Pin # I 98 Drv TTLS IOEN# I 93 TTLS READY O* 142 TS3 (* C) RESET I 141 TTLS IRQ O 103 TS3 99 TS4 (* C) MEMCS16 MEMCS16# O * IOCS16 IOCS16# O* 100 TS4 (* C) BHE# I 101 TTL Description ISA Bus System Memory Write Strobe. In Suspend Mode the MEMW# input is disabled. ISA Bus I/O Enable. This input should be connected to the ISA bus AEN signal. When this signal is high, I/O address decoding is disabled. In Suspend Mode, the IOEN# input is disabled. ISA Bus READY signal. This output is driven low to force the CPU to insert wait states during memory cycles. READY is released to highZ after a transfer is complete. The active high Reset signal from the CPU clears all internal registers and forces all signals to their inactive state. ISA Bus Vertical Interrupt. When enabled, a Vertical Retrace Interrupt will cause this signal to be driven from a logic 0 state to a logic 1 (rising-edge triggered interrupt). Once set, this interrupt must be cleared by a bit in the CRTC registers. A control bit in the Auxiliary Registers allows this output to be optionally disabled (tri-stated). This pin also is used for the output of the NAND tree in pin test mode. ISA Bus Memory Chip Select 16. Address inputs LA[23:17] are decoded to drive this output low when a valid memory address (AXXXXh, BXXXXh) appears on the bus. ISA Bus I/O Chip Select 16. Address inputs A[15:0] and IOEN# are decoded to drive this output low when a valid SPC8106 SPC8106 I/O register address appears on the bus,. Note that I/O addresses 3C6h-3C9h do not result in IOCS16 IOCS16# being driven low (i.e. RAMDAC and internal LUT register reads and writes are 8 bit cycles). ISA Bus Byte High Enable. In Suspend Mode the BHE# input is disabled. Table 0-2 Video Memory Interface Pins Pin Name MA[0:9] Type O* MD[0:15] I/O 411-1.0 Pin # 57, 55, 53, 51, 48, 52, 54, 56, 58, 20 81, 79, 77, 75, 70, 68, 66, 64, 63, 65, 67, 69, 74, 76, 78, 80 Drv TS2 (* C) Description Multiplexed row/column address bits for video display memory. TTL/ Data bits for video display memory. The output drivers of these pins are TS2U2 placed into a high-impedance state when RESET is high, or when the Sequencer is in a reset state. On the falling edge of RESET, the values on MD[3:0] and MD[12:9] are latched into a read-only Auxiliary Register and are available to be read as configuration inputs. Also, the value on MD[8:4] and MD[15:13] are used to configure various hardware options. See "Power On / Reset Options" on page 22 for details. S-MOS Systems, Inc. · Tel: (408) 922-0200 · Fax: (408) 922-0238 · http://www.smos.com SP1-17 SP1-17 X12-SP-001-07 X12-SP-001-07 Hardware Functional Specification SPC8106 SPC8106 Table 0-2 Video Memory Interface Pins (Continued) Pin Name RAS# Type O* Pin # 59 Drv TS3 (* C) TS3 (* C) LCAS# (LWE#) O* 62 UCAS# (CAS#) O* 60 TS3 (* C) WE# (UWE#) O* 61 Description DRAM Row Address Strobe for single 256Kx16 DRAM. TS3 (* C) Multiple Function: DRAM Column Address Strobe for low byte (LCAS#). For alternate function see "Multiple Function Pin Descriptions" on page 23. Multiple Function: DRAM Column Address Strobe for high byte (UCAS#). For alternate function see "Multiple Function Pin Descriptions" on page 23. Multiple Function: DRAM Write Enable Strobe (WE#). For alternate function see "Multiple Function Pin Descriptions" on page 23. Table 0-3 Clock Input Pins Pin Name CLKI1 Type I Pin # 90 Drv C CLKO1 O 91 · CLKI2 I 86 C CLKO2 O 87 · Description This pin, along with CLKO1 is the 25.175 MHz 2-terminal crystal interface when using a 2-terminal crystal as the clock input. If an external oscillator is used as a clock source, then this pin is the clock input. This pin, along with CLKI1 is the 25.175 MHz2-terminal crystal interface when using a 2-terminal crystal as the clock input. If an external oscillator is used as a clock source, then this pin should be left unconnected. This pin, along with CLKO2 is the 28.322 MHz 2-terminal crystal interface when using a 2-terminal crystal as the clock input. If an external oscillator is used as a clock source, then this pin is the clock input. This pin, along with CLKI2 is the 28.322 MHz 2-terminal crystal interface when using a 2-terminal crystal as the clock input. If an external oscillator is used as a clock source, then this pin should be left unconnected. Table 0-4 LCD Panel Interface Pins a Pin Name YD Type O* Pin # 10 Drv TS4 (* C) LP O* 13 TS4 (* C) XSCL O* 12 TS4 (* C) Description Vertical Scanning Start Pulse output. A logic 1 on this signal, sampled by the LCD module on the falling edge of LP, is used by the panel row drivers (Y drivers) to indicate the start of the vertical frame. Latch Pulse output. The falling edge of this signal is used to latch a row of display data in the LCD module's column driver shift registers and to turn on the row driver (Y driver) for that line. Shift Clock for LCD data. Display data is clocked out of the chip on the rising edge of this signal, to be shifted into the LCD panel module column drivers (X drivers) on each falling edge. SP1-18 SP1-18 S-MOS Systems, Inc. · Tel: (408) 922-0200 · Fax: (408) 922-0238 · http://www.smos.com X12-SP-001-07 X12-SP-001-07 411-1.0 SPC8106 SPC8106 Hardware Functional Specification Table 0-4 LCD Panel Interface Pins a (Continued) Pin Name XSCL2 Type O* Pin # 9 UD[0:3] O* 22~25 UD[4:7] O* 26~29 LD[0:3] O* 16~19 LD[4:7] O* 30~33 LCDPWR# O* 21 WF O* 15 Drv TS4 (* C) Description This second shift clock is used together with XSCL in 8-bit single color panel mode to shift in alternate sets of display data. XSCL2 is also used alone as the shift clock in 8-bit dual color panel mode and 4-bit single color panel mode. TS4 Upper panel display data for dual panel - dual drive mode. For 8-bit (* C) single panel-single drive mode, these bits are the most significant 4bits of the 8-bit output data to the panel (data[7:4]). For 4-bit single panel mode, these bits are the 4 bits of data output to the panel. For 16-bit LCD modes, these outputs are the multiplexed upper panel data if MD[7]=1 at RESET, or the lower nibble of the upper panel data if MD[7]=0 at RESET. TS2D When MD[7]=0 at RESET, these pins are the upper nibble of the 16(* C) bit LCD mode upper panel data. TS4 Lower panel display data for dual panel-dual drive mode. For 8-bit (* C) single panel-single drive mode, these bits are the least significant 4 bits of the 8-bit output data to the panel (data[3:0]). For 4-bit single panel mode, these outputs are driven low. For 16-bit LCD modes, these outputs are the multiplexed lower panel data if MD[7]=1 at RESET, or the lower nibble of the lower panel data if MD[7]=0 at RESET. TS2D When MD[7]=0 at RESET, these pins are the upper nibble of the 16(* TTL) bit LCD mode lower panel data. TS2 LCD power control. In normal operation this signal is driven low to (* C) enable an external LCD power supply. This signal is driven high when the chip is put into any power save mode, when Auxiliary Register 06 bit 0 is set to 1, or when the Sequencer is in a reset state. It can be used externally to turn off the panel supply voltage and backlight. After a RESET, this signal is held high until the CRTC is programmed and running. TS4D LCD Backplane Bias signal. This output toggles once every n LP (* C) periods, as programmed in AUX[0D]. a. some of these pins have alternate uses in some display modes. See "Pin Mapping for Various DRAM Configurations" on page 25 Table 0-5 External CRT/RAMDAC Interface Pins Pin Name P[0:7] Type O* Pin # 26~33 Drv TS2D (*TTL) PCLK O* 34 BLANK# O* 44 HSYNC# O* 41 TS2D (* C) TS2D (* C) TS4D (* C) 411-1.0 Description When MD[7]=1 at RESET, these pins are the Pixel Data outputs. These 8 bits are connected to the pixel select inputs of the external RAMDAC. Pixel Clock. Pixel data is clocked out of the chip on the falling edge of PCLK. Blank output. This output is clocked out on the falling edge of PCLK and is driven low during display blanking periods. Horizontal Sync. This output is clocked out on the falling edge of PCLK and is driven to indicate the horizontal retrace period. The polarity of this signal is determined by a control bit in register 3C2h. S-MOS Systems, Inc. · Tel: (408) 922-0200 · Fax: (408) 922-0238 · http://www.smos.com SP1-19 SP1-19 X12-SP-001-07 X12-SP-001-07 Hardware Functional Specification SPC8106 SPC8106 Table 0-5 External CRT/RAMDAC Interface Pins (Continued) Pin Name VSYNC# Type O* Pin # 42 Drv TS4D (* C) DACRD# O* 43 DACWR# O* 45 RS2 O* 46 TS3 (* C) TS3 (* C) TS2D (* C) OL[0:1] I/O 39, 38 OL0 C/ TS2 Description Vertical Sync. This output is clocked out on the falling edge of PCLK and is driven to indicate the vertical retrace period. The polarity of this signal is determined by a control bit in register 3C2h. RAMDAC Read Strobe. This signal goes low when a valid read access to the VGA RAMDAC is decoded by the chip. RAMDAC Write Strobe. This signal goes low when a valid write access to the VGA RAMDAC is decoded by the chip. Register Select 2 output. This output should be connected to the RS2 input of the RAMDAC (Bt477 or equivalent). The logic level on this output may be set by setting AUX[0B] bit 3. This signal is required to allow CPU access the control and overlay registers of the external RAMDAC. Multiple Function: Overlay Select outputs 1:0 OL1 TTLS/ TS2 OL23 O* 35 D477 O* 40 IREFEN# O* 47 MS[2:0] I/O 83, 82, 71 When MD[13]=0 at RESET, these pins are outputs used to provide sprite/HW cursor function on the CRT display. In this case, these outputs should be connected to the OL[0:1] inputs of the RAMDAC (Bt477 or equivalent). They are used by the sprite circuitry to access the overlay registers in the RAMDAC. TS2D (* C) For alternate function see "Multiple Function Pin Descriptions" on page 23. Overlay Select output 2/3. This output should be connected to both the OL2 and OL3 inputs of the RAMDAC (Bt477 or equivalent). This signal is used by the sprite circu