SP600 500VDC 18VDC 15VDC 10MFD 25VDC A114M 240VAC AN8829

Semiconductor July 1998 WN ITHDRA TE ART W P OLE SS OBS NS PROCE SIG DE NO NEW Features File Number 2428.4 Half Bridge 500VDC

SP600 SP600 Semiconductor July 1998 WN ITHDRA TE ART W P OLE SS OBS NS PROCE SIG DE NO NEW Features File Number 2428.4 Half Bridge 500VDC 500VDC Driver · Maximum Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . 500V The SP600 SP600 is a smart power high voltage integrated circuit (HVIC) optimized to drive MOS gated power devices in halfbridge topologies. It provides the necessary control and management for PWM motor drive, power supply, and UPS applications. · Ability to Interface and Drive Standard and Current Sensing N-Channel Power MOSFET/IGBT Devices · Creation and Management of a Floating Power Supply for Upper Rail Drive · Simultaneous Conduction Lockout · Overcurrent Protection Ordering Information · Single Low Current Bias Supply Operation PART · Latch Immune CMOS Logic PACKAGE -40oC to +85oC SP600 SP600 · Peak Drive in Excess of 0.5A Pinout TEMPERATURE 22 Lead Plastic DIP Functional Block Diagram VBS SP600 SP600 (PDIP) TOP VIEW 12 D1U ITRIPSEL 2 VBIAS 3 VDD 4 VSS 5 22 TOP 21 BOT 19 G1U VBIAS 10 RND 3 VDD 20 NC 19 D1U 4 18 G1U VDF IONT LEVEL SHIFT S IOFFT 18 G2U Q R 17 3.5 RBS TRIPU UV LOCK OUT 11 UPPER FAULT 1 + - TRIPL 6 17 G2U CL1 7 16 CL2 G2L 8 15 TRIPU 16 G1L 9 14 PHASE PHASE D1L 10 13 VOUT TOP VDF 11 12 VBS 22 15 CL2 S ITRIPSEL Q 14 3.5 RO R 13 VOUT D1L 10 S BOT CMOS TIMING AND CONTROL 21 FAULT IOFFB VOUT SENSE AND FILTER FAULT 750 RF 1 Q R Q 9 G2L 8 UV LOCK OUT TRIPL + - S 6 CL1 R FILTER G1L LOWER IONB 7 ITRIPSEL S Q R ITRIPSEL 2 1 VSS 5 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. Copyright © Harris Corporation 1998 SP600 SP600 Absolute Maximum Ratings Full Temperature Range, All Voltage Referenced to VSS Unless Otherwise Noted. Note 1, Note 2. Thermal Information Low Voltage Power Supply, VBIAS (Note 1) . . . . . . . . . . . . . . 18VDC 18VDC Floating Low Voltage Boot Strap . . . . . . . . . . . . . . . . . . . . . . 18VDC 18VDC Power Supply to Phase, VBS Low Voltage Signal Pins Fault, ITRIPSEL , VDD, TRIPL , CL1, G2L . . . -0.5VDC to VDD +0.5 G1L, D1L, VDF, TOP, BOT CL2, TRIPU , G1U, G2U, D1U to Phase. . . . -0.5VDC to VBS +0.5 High Voltage Pins Phase, VPHASE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500VDC 500VDC (VBS , VOUT , TRIPU , CL2, G2U and D1U: 0V-18V Higher Than Phase) Dynamic High Voltage Rating Phase, . . . . . . . . . . . . . 10,000V/µs DVPHASE/DT Thermal Resistance JA Plastic DIP Package . . . . . . . . . . . . . . . . . . . . . . . . 75oC/W Maximum Package Power Dissipation at TA = +85oC, PO Plastic DIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500mW Operating Ambient Temperature Range, TA . . . . . . .-25oC to +85oC Storage Temperature Range, TS . . . . . . . . . . . . . . .-40oC to +150oC Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . +265oC NOTES: 1. Care must be taken in the application of VBIAS as not to impose high peak dissipation demands on a relatively small metallized noise dropping resistor (RND). Prolonged high peak currents may result if +15VDC 15VDC is applied abruptly and/or if the local bypass capacitor CDD is large. It is suggested that CDD be 10MFD 10MFD. If it is desirable to switch the 15VDC 15VDC source or if a CDD is larger, additional series impedance may be required. 2. Consult factory for additional package offerings. CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Electrical Specifications (VBIAS = 15V, Pulsed