SN8P1927 DIP48 16-BIT SN8P1907 SSOP48 SN8P1917 SSOP48/LQFP48 SN8P1927X SEG10 - Datasheet Archive

 

8-Bit Micro-Controller with Charge pump Regulator, PGIA, 16-bit ADC SN8P1927 USER'S MANUAL Specification Version 1.0 SONiX 8-Bit

 

SN8P1927 SN8P1927 8-Bit Micro-Controller with Charge pump Regulator, PGIA, 16-bit ADC SN8P1927 SN8P1927 USER'S MANUAL Specification Version 1.0 SONiX 8-Bit Micro-Controller SONIX reserves the right to make change without further notice to any products herein to improve reliability, function or design. SONIX does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. SONIX products are not designed, intended, or authorized for us as components in systems intended, for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SONIX product could create a situation where personal injury or death may occur. Should Buyer purchase or use SONIX products for any such unintended or unauthorized application. Buyer shall indemnify and hold SONIX and its officers, employees, subsidiaries, affiliates and distributors harmless against all claims, cost, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that SONIX was negligent regarding the design or manufacture of the part. SONiX TECHNOLOGY CO., LTD Page 1 Version 1.0 SN8P1927 SN8P1927 8-Bit Micro-Controller with Charge pump Regulator, PGIA, 16-bit ADC AMENDENT HISTORY Version VER 0.1 VER 0.2 VER 0.3 VER 0.4 VER 1.0 Date Jan. 2007 Apr. 2007 Sep 2007 Sep.2007 Sep 2007 Description First issue Brief version. First issue Complete version. Remove DIP48 DIP48 package. Modify "DEVELOPMENT TOOLS" section. Modify "Electrical Characteristic" section about AVE+ voltage. SONiX TECHNOLOGY CO., LTD Page 2 Version 1.0 SN8P1927 SN8P1927 8-Bit Micro-Controller with Charge pump Regulator, PGIA, 16-bit ADC Table of Content AMENDENT HISTORY. 2 1 1 PRODUCT OVERVIEW. 7 1.1 1.2 1.3 1.4 1.5 1.6 1.7 2 2 SELECTION TABLE. 7 MIGRATION TABLE. 7 FEATURES . 8 SYSTEM BLOCK DIAGRAM . 9 PIN ASSIGNMENT . 10 PIN DESCRIPTIONS. 12 PIN CIRCUIT DIAGRAMS. 13 CENTRAL PROCESSOR UNIT (CPU) . 14 2.1 MEMORY MAP. 14 2.1.1 PROGRAM MEMORY (ROM) . 14 2.1.2 CODE OPTION TABLE . 23 2.1.3 DATA MEMORY (RAM). 24 2.1.4 SYSTEM REGISTER. 25 2.2 ADDRESSING MODE . 35 2.2.1 IMMEDIATE ADDRESSING MODE. 35 2.2.2 DIRECTLY ADDRESSING MODE . 35 2.2.3 INDIRECTLY ADDRESSING MODE . 35 2.3 STACK OPERATION. 36 2.3.1 2.3.2 2.3.3 3 3 OVERVIEW . 36 STACK REGISTERS . 37 STACK OPERATION EXAMPLE. 38 RESET . 39 3.1 3.2 3.3 OVERVIEW. 39 POWER ON RESET. 40 WATCHDOG RESET. 40 3.4 BROWN OUT RESET . 41 3.4.1 BROWN OUT DESCRIPTION . 41 3.4.2 THE SYSTEM OPERATING VOLTAGE DECSRIPTION. 42 3.4.3 BROWN OUT RESET IMPROVEMENT. 42 3.5 EXTERNAL RESET . 44 3.6 EXTERNAL RESET CIRCUIT . 44 3.6.1 3.6.2 Simply RC Reset Circuit . 44 Diode & RC Reset Circuit . 45 SONiX TECHNOLOGY CO., LTD Page 3 Version 1.0 SN8P1927 SN8P1927 8-Bit Micro-Controller with Charge pump Regulator, PGIA, 16-bit ADC 3.6.3 3.6.4 3.6.5 4 4 Zener Diode Reset Circuit . 45 Voltage Bias Reset Circuit. 46 External Reset IC. 46 SYSTEM CLOCK . 47 4.1 OVERVIEW. 47 4.2 4.3 4.4 CLOCK BLOCK DIAGRAM . 47 OSCM REGISTER . 48 SYSTEM HIGH CLOCK . 49 4.4.1 INTERNAL HIGH RC. 49 4.4.2 EXTERNAL HIGH CLOCK. 49 4.5 SYSTEM LOW CLOCK . 51 4.5.1 5 5 SYSTEM OPERATION MODE . 53 5.1 5.2 5.3 OVERVIEW. 53 SYSTEM MODE SWITCHING EXAMPLE . 54 WAKEUP . 55 5.3.1 5.3.2 6 6 OVERVIEW. 56 INTEN INTERRUPT ENABLE REGISTER. 56 INTRQ INTERRUPT REQUEST REGISTER . 57 GIE GLOBAL INTERRUPT OPERATION . 57 PUSH, POP ROUTINE . 58 INT0 (P0.0) INTERRUPT OPERATION. 59 T0 INTERRUPT OPERATION . 60 MULTI-INTERRUPT OPERATION. 61 I/O PORT . 62 7.1 7.2 7.3 8 8 OVERVIEW . 55 WAKEUP TIME. 55 INTERRUPT. 56 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 7 7 SYSTEM CLOCK MEASUREMENT . 52 I/O PORT MODE . 62 I/O PULL UP REGISTER . 63 I/O PORT DATA REGISTER . 64 TIMERS . 65 8.1 8.2 8.2.1 8.2.2 WATCHDOG TIMER (WDT) . 65 TIMER 0 (T0) . 67 OVERVIEW . 67 T0M MODE REGISTER. 67 SONiX TECHNOLOGY CO., LTD Page 4 Version 1.0 SN8P1927 SN8P1927 8-Bit Micro-Controller with Charge pump Regulator, PGIA, 16-bit ADC 8.2.3 8.2.4 9 9 T0C COUNTING REGISTER. 68 T0 TIMER OPERATION SEQUENCE . 69 LCD DRIVER . 70 9.1 LCDM1 REGISTER. 70 9.2 9.3 9.4 LCD TIMING . 71 LCD RAM LOCATION . 73 LCD CIRCUIT . 74 10 10 IN SYSTEM PROGRAM ROM . 76 10.1 10.2 10.3 10.4 10.5 11 11 OVERVIEW. 76 ROMADRH/ROMADRL REGISTER. 76 ROMDAH/ROMADL REGISTERS. 76 ROMCNT REGISTERS AND ROMWRT INSTRUCTION . 77 ISP ROM ROUTINE EXAMPLE . 78 CHARGE-PUMP, PGIA AND ADC . 79 11.1 11.2 11.3 OVERVIEW. 79 ANALOG INPUT. 79 VOLTAGE CHARGE PUMP / REGULATOR (CPR) . 80 11.3.1 CPM-Charge Pump Mode Register. 80 11.3.2 CPCKS-Charge Pump Clock Register . 82 11.4 PGIA -PROGRAMMABLE GAIN INSTRUMENTATION AMPLIFIER . 84 11.4.1 AMPM- Amplifier Mode Register. 84 11.4.2 AMPCKS- PGIA CLOCK SELECTION . 85 11.4.3 AMPCHS-PGIA CHANNEL SELECTION . 86 11.4.4 Temperature Sensor (TS). 87 11.5 16-BIT 16-BIT ADC . 90 11.5.1 11.5.2 11.5.3 11.5.4 11.5.5 11.5.6 11.5.7 12 12 ADCM- ADC Mode Register . 90 ADCKS- ADC Clock Register . 93 ADCDL- ADC Low-Byte Data Register . 94 ADCDH- ADC High-Byte Data Register . 94 DFM-ADC Digital Filter Mode Register . 95 LBTM : Low Battery Detect Register . 98 Analog Setting and Application. 99 APPLICATION CIRCUIT. 101 12.1 12.2 THERMOMETER APPLICATION CIRCUIT . 102 13 13 SCALE (LOAD CELL) APPLICATION CIRCUIT . 101 INSTRUCTION SET TABLE. 103 SONiX TECHNOLOGY CO., LTD Page 5 Version 1.0 SN8P1927 SN8P1927 8-Bit Micro-Controller with Charge pump Regulator, PGIA, 16-bit ADC 14 14 DEVELOPMENT TOOLS . 104 14.1 DEVELOPMENT TOOL VERSION . 104 14.1.1 ICE (In circuit emulation) . 104 14.1.2 OTP Writer . 104 14.1.3 IDE (Integrated Development Environment) . 104 14.2 SN8P1927 SN8P1927 DEMO/EV KIT . 105 14.2.1 PCB DESCRIPTION . 105 14.2.2 SN8P1927 SN8P1927 DEMO/EV BOARD CONNECT TO SN8ICE 1K . 107 14.3 TRANSITION BOARD FOR OTP PROGRAMMING . 108 14.3.1 SN8P1927 SN8P1927 TRANSITION BOARD. 108 14.3.2 Connect to MPIII WRITER. 108 14.3.3 Connect to Easy WRITER. 109 14.4 OTP PROGRAMMING PIN TO TRANSITION BOARD MAPPING . 110 14.4.1 The pin assignment of Easy and MP EZ Writer transition board socket:. 110 14.4.2 14.4.3 The pin assignment of Writer V3.0 transition board socket:. 110 SN8P1927 SN8P1927 Series Programming Pin Mapping: . 111 15 15 ELECTRICAL CHARACTERISTIC . 112 15.1 15.2 16 16 ABSOLUTE MAXIMUM RATING . 112 ELECTRICAL CHARACTERISTIC. 112 PACKAGE INFORMATION . 115 16.1 16.2 17 17 SSOP 48 PIN. 115 LQFP 48 PIN . 116 MARKING DEFINITION. 117 17.1 17.2 17.3 17.4 INTRODUCTION . 117 MARKING INDETIFICATION SYSTEM. 117 MARKING EXAMPLE . 118 DATECODE SYSTEM . 118 SONiX TECHNOLOGY CO., LTD Page 6 Version 1.0 SN8P1927 SN8P1927 8-Bit Micro-Controller with Charge pump Regulator, PGIA, 16-bit ADC 1 PRODUCT OVERVIEW 1.1 SELECTION TABLE CHIP Timer ROM RAM Stack LCD I/O ADC T0 TC0 TC1 PWM Buzzer SIO Wakeup Pin no. Package SN8P1907 SN8P1907 2K*16 128*8 8 4*12 V - - 11 16-bit - - 5 SSOP48 SSOP48 SN8P1917 SN8P1917 2K*16 128*8 8 4*12 V - - 13 16-bit - - 5 SSOP48 SSOP48 SN8P1927 SN8P1927 2K*16 128*8 8 4*12 V - - 13 16-bit - - 5 SSOP48/LQFP48 SSOP48/LQFP48 Table 1-1 Selection table of SN8P1927 SN8P1927 serial 1.2 MIGRATION TABLE Item SN8P1907 SN8P1907 PGIA Gain setting 1x, 16x, 32x, 64x, 128x PGIA Temperature Drift No Good Good Good AVE+ Voltage 3.0V only 3.0V or 1.5V 2.0V or 1.5V Double Current Double Current NOT Double Current Consumption Consumption Consumption ADC Reference Voltage V(R+, R-) 0.8V only 0.8V/ 0.4V 0.8V/ 0.6V/ 0.4V Battery Detect Method By ADC only By Comparator or By Comparator or By ADC By ADC Temperature Sensor External Build In Build In Change with Sink Not Change with Sink Not Change with Sink current current current Charge pump clock frequency (CPCKS) 2-Bit Selection 4-Bit Selection 4-Bit Selection Chopper clock frequency (AMPCKS) 2-Bit Selection 3-Bit Selection 3-Bit Selection AVDDR/AVE+ working in slow mode No Yes Yes Operating Current Consumption More Less Less Slow mode Current Consumption More Less Less LCD Bias Voltage 1/2 Bias only 1/3 or 1/2 Bias 1/3 or 1/2 Bias Internal 16M RC Oscillator No Yes Yes P2 [1:0] I/O No Available when Available when Fosc=IHRC Fosc=IHRC OTP Programming Method Parallel Method Serial Method Serial Method In-System Programmer ROM No No Yes ADC Accuracy 14 Bit 14 Bit 13 Bit AVE+ current loading in CPR ON ACM (1.2V) Voltage SN8P1917 SN8P1917 SN8P1927 SN8P1927 1x, 12.5x, 50x, 100x, 200x 1x, 12.5x, 50x, 100x, 200x Table 1-2 SN8P1927 SN8P1927 Migration Table SONiX TECHNOLOGY CO., LTD Page 7 Version 1.0 SN8P1927 SN8P1927 8-Bit Micro-Controller with Charge pump Regulator, PGIA, 16-bit ADC 1.3 FEATURES Two interrupt sources One internal interrupts: T0 One external interrupts: INT0 Single power supply: 2.4V ~5.5V Wakeup: P0, P1 On-chip watchdog timer On-chip charge-pump regulator with 3.8V voltage output and 10mA driven current. On chip regulator with 2.0V/1.5V output voltage AVE+ Loading current consumption will NOT double when CPR ON On-chip 1.2V Band gap reference for battery monitor. On chip Voltage Comparator. Pull-up resisters: P0, P1, P2, P4 Build in ADC Ref. voltage V(R+,R-)= 0.8V/0.6V/0.4V. External interrupt: P0 Memory configuration OTP ROM size: 2K * 16 bits RAM size: 128 * 8 bits (bank 0) 8-levels stack buffer LCD RAM size: 4*12 bits In-System Programmer ROM. I/O pin configuration Input only: P0, P4 Bi-directional: P1, P2 Output only: P5 Powerful instructions Four clocks per instruction cycle All instructions are one word length Most of instructions are 1 cycle only. Maximum instruction cycle is "2". JMP instruction jumps to all ROM area. LCD driver: 1/3 or 1/2 bias voltage. 4 common * 12 segment Dual clock system offers four operating modes All ROM area look-up table function (MOVC) External high clock: RC type up to 10 MHz External high clock: Crystal type up to 8 MHz Normal mode: Both high and low clock active. Programmable Gain Instrumentation Amplifier Slow mode: Low clock only. Gain option: 1x/12.5x/50x/100x/200x Sleep mode: Both high and low clock stop. 16-bit Delta-Sigma ADC with 13-bit noise free Package Two ADC channel configuration: SSOP48/LQFP48 SSOP48/LQFP48 One fully differential channel Two single channels SONiX TECHNOLOGY CO., LTD Page 8 Version 1.0 SN8P1927 SN8P1927 8-Bit Micro-Controller with Charge pump Regulator, PGIA, 16-bit ADC 1.4 SYSTEM BLOCK DIAGRAM INTERNAL HIGH RC PC OTP EXTERNAL HIGH OSC. IR ROM INTERNAL LOW RC LVD (Low Voltage Detector) FLAGS WATCHDOG TIMER TIMING GENERATOR Charge Pump Regulator ALU AVDDCP AVDDR AVE+ PGIA AI+/AI- RAM Comparator ACC INTERRUPT CONTROL P0 16-BIT 16-BIT ADC SYSTEM REGISTERS P2 R+/R- Internal Reference Internal ADC Channel for Battery Detect TIMER & COUNTER P1 LBTIN2/1 P5 P4 Figure 1-1 Simplified system block diagram SONiX TECHNOLOGY CO., LTD Page 9 Version 1.0 SN8P1927 SN8P1927 8-Bit Micro-Controller with Charge pump Regulator, PGIA, 16-bit ADC 1.5 PIN ASSIGNMENT SN8P1927X SN8P1927X SEG4 SEG3 SEG2 SEG1 SEG0 COM3 COM2 COM1 COM0 VLCD R+ RX+ XAI+ AIAVSS ACM ADDR AVE+ AVDDCP C+ VDD C- 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG10 SEG11 SEG11 VPP/RST VSS P5.2 P5.1 P5.0 P4.2/LBTIN2 P4.1/LBTIN1 P4.0 P1.3 P1.2 P1.1 P1.0 P0.0/INT0 VDD XOUT/P2.1 XIN/P2.0 VSS SN8P1927X SN8P1927X SONiX TECHNOLOGY CO., LTD Page 10 Version 1.0 SN8P1927 SN8P1927 8-Bit Micro-Controller with Charge pump Regulator, PGIA, 16-bit ADC SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 COM3 COM2 SN8P1927Q SN8P1927Q SONiX TECHNOLOGY CO., LTD Page 11 P1.1 P1.0 P0.0/INT0 VDD XOUT/P2.1 SIN/P2.0 VSS C- VDD C+ AVDDCP AVE+ 48 47 46 45 44 43 42 41 40 39 38 37 COM1 1 O 36 SEG10 SEG10 COM0 2 35 SEG11 SEG11 VLCD 3 34 VPP/RST R+ 4 33 VSS R- 5 32 P5.2 X+ 6 SN8P1927Q SN8P1927Q 31 P5.1 X- 7 30 P5.0 AI+ 8 29 P4.2/LBTIN2 AI- 9 28 P4.1/LBTIN1 AVSS 10 27 P4.0 ACM 11 26 P1.3 AVDDR 12 25 P1.2 13 14 15 16 17 18 19 20 21 22 23 24 Version 1.0 SN8P1927 SN8P1927 8-Bit Micro-Controller with Charge pump Regulator, PGIA, 16-bit ADC 1.6 PIN DESCRIPTIONS PIN NAME VDD, VSS, AVSS VLCD AVDDR AVE+ ACM AVDDCP R+ RX+ XAI+ AIC+ C- TYPE P P P P P P AI AI AI AI AI AI A A VPP/ RST P, I XIN, XOUT P0.0 / INT0 P1 [3:0] P2 [1:0] P4 [2:0] P5 [2:0] LBTIN1/2 COM [3:0] SEG0 ~ SEG11 SEG11 I, O I I/O I/O I O II O O DESCRIPTION Power supply input pins for digital / analog circuit. LCD Power supply input Regulator power output pin, Voltage=3.8V. Regulator output =3.0V or 1.5V for Sensor. Maximum output current=10 mA Band Gap Voltage output =1.2V Charge Pump Voltage output. ( connect a 10uF or higher capacitor to ground) Positive reference input Negative reference input Positive ADC differential input, a 0.1uF capacitor connect to pin XNegative ADC differential input Positive analog input channel Negative analog input channel Positive capacitor terminal for charge pump regulator Negative capacitor terminal for charge pump regulator OTP ROM programming pin. System reset input pin. Schmitt trigger structure, active "low", normal stay to "high". External High clock oscillator pins. RC mode from XIN. Port 0.0 and shared with INT0 trigger pin (Schmitt trigger) / Built-in pull-up resisters. Port 1.0~Port 1.3 bi-direction pins / wakeup pins/ Built-in pull-up resisters. Port 2.0~Port 2.1 bi-direction pins / Built-in pull-up resisters. Shared with XIN/XOUT Port 4.0~Port 4.2 Input pins/ Built-in pull-up resisters Port 5.0~Port 5.2 output pins Low BatTery detect Input pins shared with P4.1, P4.2 COM0~COM3 LCD driver common port LCD driver segment pins. SONiX TECHNOLOGY CO., LTD Page 12 Version 1.0 SN8P1927 SN8P1927 8-Bit Micro-Controller with Charge pump Regulator, PGIA, 16-bit ADC 1.7 PIN CIRCUIT DIAGRAMS Port 0, Port 4structure: Pull-Up PnUR Pin Input Bus Port 5 structure: Output Latch Pin Output Bus Port1 structure: Pull-Up PnM PnM, PnUR Input Bus Pin Output Latch Output Bus Port2 structure: Pull-Up Oscillator Code Option PnM PnM, PnUR Input Bus Pin Output Latch Output Bus Int. Osc. SONiX TECHNOLOGY CO., LTD Page 13 Version 1.0 SN8P1927 SN8P1927 8-Bit Micro-Controller with Charge pump Regulator, PGIA, 16-bit ADC 2 CENTRAL PROCESSOR UNIT (CPU) 2.1 MEMORY MAP 2.1.1 PROGRAM MEMORY (ROM) 2K words ROM 0000H 0000H 0001H 0001H 0002H 0002H 0003H 0003H 0004H 0004H 0005H 0005H 0006H 0006H 0007H 0007H 0008H 0008H 0009H 0009H . . 000FH 000FH 0010H 0010H 0011H 0011H . . 7FEH 7FFH ROM Reset vector General purpose area User reset vector Jump to user start address Jump to user start address Jump to user start address Reserved Interrupt vector User interrupt vector User program General purpose area SONiX TECHNOLOGY CO., LTD End of user program Reserved Page 14 Version 1.0 SN8P1927 SN8P1927 8-Bit Micro-Controller with Charge pump Regulator, PGIA, 16-bit ADC 2.1.1.1 RESET VECTOR (0000H 0000H) A one-word vector address area is used to execute system reset. Power On Reset Watchdog Rese External Reset After power on reset, external reset or watchdog timer overflow reset, then the chip will restart the program from address 0000h and all system registers will be set as default values. The following example shows the way to define the reset vector in the program memory. Example: Defining Reset Vector ORG JMP . 0 START ORG 10H START: . . ENDP SONiX TECHNOLOGY CO., LTD ; 0000H 0000H ; Jump to user program address. ; 0010H 0010H, The head of user program. ; User program ; End of program Page 15 Version 1.0 SN8P1927 SN8P1927 8-Bit Micro-Controller with Charge pump Regulator, PGIA, 16-bit ADC 2.1.1.2 INTERRUPT VECTOR (0008H 0008H) A 1-word vector address area is used to execute interrupt request. If any interrupt service executes, the program counter (PC) value is stored in stack buffer and jump to 0008h of program memory to execute the vectored interrupt. Users have to define the interrupt vector. The following example shows the way to define the interrupt vector in the program memory. Note: Users have to save and load ACC and PFLAG register by program as interrupt occurrence. Example: Defining Interrupt Vector. The interrupt service routine is following ORG 8. .DATA ACCBUF DS 1 PFLAGBUF DS 1 ; Define ACCBUF for store ACC data. ; Define PFLAGBUF for store PFLAG data. ORG JMP . 0 START ; 0000H 0000H ; Jump to user program address. ORG B0XCH B0MOV B0MOV . . B0MOV B0MOV B0XCH RETI . 8 A, ACCBUF A, PFLAG PFLAGBUF, A ; Interrupt vector. ; Save ACC in a buffer. .CODE A, PFLAGBUF PFLAG, A A, ACCBUF START: . . JMP . ; Save PFLAG register in a buffer. ; Restore PFLAG register from buffer. ; Restore ACC from buffer. ; End of interrupt service routine ; The head of user program. ; User program START ENDP SONiX TECHNOLOGY CO., LTD ; End of user program ; End of program Page 16 Version 1.0 SN8P1927 SN8P1927 8-Bit Micro-Controller with Charge pump Regulator, PGIA, 16-bit ADC Example: Defining Interrupt Vector. The interrupt service routine is following user program. .DATA ACCBUF DS 1 PFLAGBUF DS 1 ; Define ACCBUF for store ACC data. ; Define PFLAGBUF for store PFLAG data. ORG JMP . 0 START ; 0000H 0000H ; Jump to user program address. ORG JMP 8 MY_IRQ ; Interrupt vector. ; 0008H 0008H, Jump to interrupt service routine address. ORG 10H .CODE START: . . . JMP . ; 0010H 0010H, The head of user program. ; User program. START MY_IRQ: B0XCH B0MOV B0MOV . . B0MOV B0MOV B0XCH RETI . A, ACCBUF A, PFLAG PFLAGBUF, A A, PFLAGBUF PFLAG, A A, ACCBUF ENDP ; End of user program. ;The head of interrupt service routine. ; Save ACC in a buffer. ; Save PFLAG register in a buffer. ; Restore PFLAG register from buffer. ; Restore ACC from buffer. ; End of interrupt service routine. ; End of program. Note: It is easy to understand the rules of SONIX program from demo programs given above. These points are as following: 1. The address 0000H 0000H is a "JMP" instruction to make the program starts from the beginning. 2. The address 0008H 0008H is interrupt vector. 3. User's program is a loop routine for main purpose application. SONiX TECHNOLOGY CO., LTD Page 17 Version 1.0 SN8P1927 SN8P1927 8-Bit Micro-Controller with Charge pump Regulator, PGIA, 16-bit ADC 2.1.1.3 LOOK-UP TABLE DESCRIPTION In the ROM's data lookup function, Y register is pointed to middle byte address (bit 8~bit 15) and Z register is pointed to low byte address (bit 0~bit 7) of ROM. After MOVC instruction executed, the low-byte data will be stored in ACC and high-byte data stored in R register. Example: To look up the ROM data located "TABLE1". B0MOV B0MOV MOVC INCMS JMP INCMS NOP @@: TABLE1: Y, #TABLE1$M Z, #TABLE1$L Z @F Y MOVC . DW DW DW . 0035H 0035H 5105H 5105H 2012H 2012H ; To set lookup table1's middle address ; To set lookup table1's low address. ; To lookup data, R = 00H, ACC = 35H ; Increment the index address for next address. ; Z+1 ; Z is not overflow. ; Z overflow (FFH 00), Y=Y+1 ; ; ; To lookup data, R = 51H, ACC = 05H. ; ; To define a word (16 bits) data. Note: The Y register will not increase automatically when Z register crosses boundary from 0xFF to 0x00. Therefore, user must take care such situation to avoid look-up table errors. If Z register overflows, Y register must be added one. The following INC_YZ macro shows a simple method to process Y and Z registers automatically. Example: INC_YZ macro. INC_YZ MACRO INCMS JMP INCMS NOP Z @F ; Z+1 ; Not overflow Y ; Y+1 ; Not overflow @@: ENDM SONiX TECHNOLOGY CO., LTD Page 18 Version 1.0 SN8P1927 SN8P1927 8-Bit Micro-Controller with Charge pump Regulator, PGIA, 16-bit ADC Example: Modify above example by "INC_YZ" macro. B0MOV B0MOV MOVC Y, #TABLE1$M Z, #TABLE1$L INC_YZ @@: TABLE1: MOVC . DW DW DW . 0035H 0035H 5105H 5105H 2012H 2012H ; To set lookup table1's middle address ; To set lookup table1's low address. ; To lookup data, R = 00H, ACC = 35H ; Increment the index address for next address. ; ; To lookup data, R = 51H, ACC = 05H. ; ; To define a word (16 bits) data. The other example of look-up table is to add Y or Z index register by accumulator. Please be careful if "carry" happen. Example: Increase Y and Z register by B0ADD/ADD instruction. B0MOV B0MOV Y, #TABLE1$M Z, #TABLE1$L ; To set lookup table's middle address. ; To set lookup table's low address. B0MOV B0ADD A, BUF Z, A ; Z = Z + BUF. B0BTS1 JMP INCMS NOP FC GETDATA Y ; Check the carry flag. ; FC = 0 ; FC = 1. Y+1. GETDATA: ; ; To lookup data. If BUF = 0, data is 0x0035 ; If BUF = 1, data is 0x5105 ; If BUF = 2, data is 0x2012 MOVC . TABLE1: DW DW DW . 0035H 0035H 5105H 5105H 2012H 2012H SONiX TECHNOLOGY CO., LTD ; To define a word (16 bits) data. Page 19 Version 1.0 SN8P1927 SN8P1927 8-Bit Micro-Controller with Charge pump Regulator, PGIA, 16-bit ADC 2.1.1.4 JUMP TABLE DESCRIPTION The jump table operation is one of multi-address jumping function. Add low-byte program counter (PCL) and ACC value to get one new PCL. The new program counter (PC) points to a series jump instructions as a listing table. It is easy to make a multi-jump program depends on the value of the accumulator (A). When carry flag occurs after executing of "ADD PCL, A", it will not affect PCH register. Users have to check if the jump table leaps over the ROM page boundary or the listing file generated by SONIX assembly software. If the jump table leaps over the ROM page boundary (e.g. from xxFFH to xx00H), move the jump table to the top of next program memory page (xx00H). Here one page mean 256 words. Note: Program counter can't carry from PCL to PCH when PCL is overflow after executing addition instruction. Example: Jump table. ORG 0X0100 0X0100 ; The jump table is from the head of the ROM boundary B0ADD JMP JMP JMP JMP PCL, A A0POINT A1POINT A2POINT A3POINT ; PCL = PCL + ACC, the PCH can't be changed. ; ACC = 0, jump to A0POINT ; ACC = 1, jump to A1POINT ; ACC = 2, jump to A2POINT ; ACC = 3, jump to A3POINT In following example, the jump table starts at 0x00FD. When execute B0ADD PCL, A. If ACC = 0 or 1, the jump table points to the right address. If the ACC is larger then 1 will cause error because PCH doesn't increase one automatically. We can see the PCL = 0 when ACC = 2 but the PCH still keep in 0. The program counter (PC) will point to a wrong address 0x0000 and crash system operation. It is important to check whether the jump table crosses over the boundary (xxFFH to xx00H). A good coding style is to put the jump table at the start of ROM boundary (e.g. 0100H 0100H). Example: If "jump table" crosses over ROM boundary will cause errors. ROM Address . . . 0X00FD 0X00FD 0X00FE 0X00FE 0X00FF 0X00FF 0X0100 0X0100 0X0101 0X0101 . . B0ADD JMP JMP JMP JMP PCL, A A0POINT A1POINT A2POINT A3POINT SONiX TECHNOLOGY CO., LTD ; PCL = PCL + ACC, the PCH can't be changed. ; ACC = 0 ; ACC = 1 ; ACC = 2 jump table cross boundary here ; ACC = 3 Page 20 Version 1.0 SN8P1927 SN8P1927 8-Bit Micro-Controller with Charge pump Regulator, PGIA, 16-bit ADC SONIX provides a macro for safe jump table function. This macro will check the ROM boundary and move the jump table to the right position automatically. The side effect of this macro maybe wastes some ROM size. Example: If "jump table" crosses over ROM boundary will cause errors. @JMP_A MACRO IF JMP ORG ENDIF ADD ENDM VAL ($+1) !& 0XFF00 0XFF00) !!= ($+(VAL) !& 0XFF00 0XFF00) ($ | 0XFF) ($ | 0XFF) PCL, A Note: "VAL" is the number of the jump table listing number. Example: "@JMP_A" application in SONIX macro file called "MACRO3.H". B0MOV @JMP_A JMP JMP JMP JMP JMP A, BUF0 5 A0POINT A1POINT A2POINT A3POINT A4POINT ; "BUF0" is from 0 to 4. ; The number of the jump table listing is five. ; ACC = 0, jump to A0POINT ; ACC = 1, jump to A1POINT ; ACC = 2, jump to A2POINT ; ACC = 3, jump to A3POINT ; ACC = 4, jump to A4POINT If the jump table position is across a ROM boundary (0x00FF~0x0100), the "@JMP_A" macro will adjust the jump table routine begin from next RAM boundary (0x0100). Example: "@JMP_A" operation. ; Before compiling program. ROM address 0X00FD 0X00FD 0X00FE 0X00FE 0X00FF 0X00FF 0X0100 0X0100 0X0101 0X0101 B0MOV @JMP_A JMP JMP JMP JMP JMP A, BUF0 5 A0POINT A1POINT A2POINT A3POINT A4POINT ; "BUF0" is from 0 to 4. ; The number of the jump table listing is five. ; ACC = 0, jump to A0POINT ; ACC = 1, jump to A1POINT ; ACC = 2, jump to A2POINT ; ACC = 3, jump to A3POINT ; ACC = 4, jump to A4POINT A, BUF0 5 A0POINT A1POINT A2POINT A3POINT A4POINT ; "BUF0" is from 0 to 4. ; The number of the jump table listing is five. ; ACC = 0, jump to A0POINT ; ACC = 1, jump to A1POINT ; ACC = 2, jump to A2POINT ; ACC = 3, jump to A3POINT ; ACC = 4, jump to A4POINT ; After compiling program. ROM address 0X0100 0X0100 0X0101 0X0101 0X0102 0X0102 0X0103 0X0103 0X0104 0X0104 B0MOV @JMP_A JMP JMP JMP JMP JMP SONiX TECHNOLOGY CO., LTD Page 21 Version 1.0 SN8P1927 SN8P1927 8-Bit Micro-Controller with Charge pump Regulator, PGIA, 16-bit ADC 2.1.1.5 CHECKSUM CALCULATION The last ROM address are reserved area. User should avoid these addresses (last address) when calculate the Checksum value. Example: The demo program shows how to calculated Checksum from 00H to the end of user's code. MOV B0MOV MOV B0MOV CLR CLR A,#END_USER_CODE$L END_ADDR1, A ; Save low end address to end_addr1 A,#END_USER_CODE$M END_ADDR2, A ; Save middle end address to end_addr2 Y ; Set Y to 00H Z ; Set Z to 00H MOVC B0BSET ADD MOV ADC JMP FC DATA1, A A, R DATA2, A END_CHECK ; Clear C flag ; Add A to Data1 INCMS JMP JMP Z @B Y_ADD_1 ; Z=Z+1 ; If Z != 00H calculate to next address ; If Z = 00H increase Y MOV CMPRS JMP MOV CMPRS JMP JMP A, END_ADDR1 A, Z AAA A, END_ADDR2 A, Y AAA CHECKSUM_END ; If Yes, check if Y = middle end address ; If Not jump to checksum calculate ; If Yes checksum calculated is done. INCMS NOP JMP Y ; Increase Y @B ; Jump to checksum calculate @@: ; Add R to Data2 ; Check if the YZ address = the end of code AAA: END_CHECK: ; Check if Z = low end address ; If Not jump to checksum calculate Y_ADD_1: CHECKSUM_END: . . END_USER_CODE: SONiX TECHNOLOGY CO., LTD ; Label of program end Page 22 Version 1.0 SN8P1927 SN8P1927 8-Bit Micro-Controller with Charge pump Regulator, PGIA, 16-bit ADC 2.1.2 CODE OPTION TABLE Code Option High_Clk Watch_Dog Security INT_16K_RC Low Power Content IHRC 4M X'tal Enable Disable Enable Disable Always_ON By_CPUM Enable Disable Function Description High speed internal 16MHz RC. XIN/XOUT become to P2.0/P2.1 bi-direction I/O pins. Standard crystal /resonator (e.g. 4M) for external high clock oscillator. Enable Watchdog function Disable Watchdog function Enable ROM code Security function Disable ROM code Security function Force Watch Dog Timer clock source come from INT 16K RC. Also INT 16K RC never stop both in power down and green mode that means Watch Dog Timer will always enable both in power down and green mode. Enable or Disable internal 16K(@ 3V) RC clock by CPUM register Enable Low Power function to save Operating current Disable Low Power function Note: 1. In high noisy environment, set Watch_Dog as "Enable" and INT_16K_RC as "Always_ON" is strongly recommended. 2. Fcpu code option is only available for High Clock. Fcpu of slow mode is Flosc/4. 3. In high noisy environment, disable "Low Power" is strongly recommended. 4. The side effect is to increase the lowest valid working voltage level if enable "Low Power" code option. 5. Enable "Low Power" option will reduce operating current except in slow mode. SONiX TECHNOLOGY CO., LTD Page 23 Version 1.0 SN8P1927 SN8P1927 8-Bit Micro-Controller with Charge pump Regulator, PGIA, 16-bit ADC 2.1.3 DATA MEMORY (RAM) 128 X 8-bit RAM 000h BANK 0 BANK 15 07Fh 080h 0FFh F00h F0Bh SONiX TECHNOLOGY CO., LTD RAM location General purpose area . . System register . End of bank 0 area LCD RAM area . End of LCD Ram Page 24 ; 000h~07Fh of Bank 0 = To store general ; purpose data (128 bytes). ; 080h~0FFh of Bank 0 = To store system ; registers (128 bytes). ; Bank 15 = To store LCD display data ; (12 bytes). ; Version 1.0 SN8P1927 SN8P1927 8-Bit Micro-Controller with Charge pump Regulator, PGIA, 16-bit ADC 2.1.4 SYSTEM REGISTER 2.1.4.1 SYSTEM REGISTER TABLE 0 1 2 3 4 5 6 7 8 9 A B C D E F - LCDM1 - - - - - - - - - - PEDGE 8 - - R Z Y - PFLAG RBAN K 9 AMPM AMPCHS AMPCK S ADCM ADCKS CPM CPCKS DFM A B C D E F ADCDL ADCDH LBTM - - - - - - - - - - - - - - - - - - - - - - - - - P1M P2M - - - - - INTRQ INTEN OSCM - - - PCL PCH P0 P1 P2 - P4 P5 - - T0M T0C - - - - - STKP - - - @YZ - - - - - - - ROMADRH ROMADRL ROMDAH ROMDAL ROMCNT - P1UR P2UR - STK7L STK7H STK6L STK6H 2.1.4.2 STK5L STK5H STK4L STK4H STK3L STK3H STK2L STK2H STK1L STK1H STK0L STK0H SYSTEM REGISTER DESCRIPTION Y, Z = PFLAG = AMPM = AMPCKS = ADCKS = CPCKS = ADCDL = PNM = PN = INTEN = LCDM1= T0M = T0C = LBTM= Working, @YZ and ROM addressing register ROM page and special flag register PGIA mode register PGIA clock selection ADC clock selection Charge pump clock selection ADC low-byte data buffer Port N input/output mode register Port N data buffer Interrupt enable register LCD mode register Timer 0 mode register Timer 0 counting register Low Battery Detect Register R= AMPCHS = ADCM = CPM = DFM = ADCDH = PNUR = INTRQ = OSCM = PCH, PCL = STK0~STK7 = @YZ = STKP = ROMADRH/L= ROMDAH/L= ROMCNT= SONiX TECHNOLOGY CO., LTD Page 25 Working register and ROM look-up data buffer PGIA channel selection ADC's mode register Charge pump mode Decimation filter mode ADC high-byte data buffer Port N pull-up register Interrupt request register Oscillator mode register Program counter Stack 0 ~ stack 7 buffer RAM YZ indirect addressing index pointer Stack pointer buffer ISP ROM Address ISP ROM Data ISP ROM Counter Version 1.0 SN8P1927 SN8P1927 8-Bit Micro-Controller with Charge pump Regulator, PGIA, 16-bit ADC 2.1.4.3 Address 082H 083H 084H 086H 087H 089H 090H 091H 092H 093H 094H 095H 096H 097H 098H 099H 09AH 0A0H 0A1H 0A2H 0A3H 0A4H 0BFH 0C1H 0C2H 0C8H 0C9H 0CAH 0CEH 0CFH 0D0H 0D1H 0D2H 0D4H 0D5H 0D8H 0D9H 0DFH 0E1H 0E2H 0E7H 0F0H 0F1H 0F2H 0F3H 0F4H 0F5H 0F6H 0F7H 0F8H 0F9H 0FAH 0FBH BIT DEFINITION of SYSTEM REGISTER Bit7 Bit6 Bit5 Bit4 RBIT7 RBIT6 RBIT5 RBIT4 ZBIT7 ZBIT6 ZBIT5 ZBIT4 YBIT7 YBIT6 YBIT5 YBIT4 LCDBNK BGRENB FDS1 FDS0 ADCKS7 ADCKS6 ADCKS5 ADCKS4 ACMENB AVDDRENB AVESEL AVENB ADCB7 ADCB6 ADCB5 ADCB4 ADCB15 ADCB15 ADCB14 ADCB14 ADCB13 ADCB13 ADCB12 ADCB12 - Bit3 Bit2 Bit1 RBIT3 RBIT2 RBIT1 ZBIT3 ZBIT2 ZBIT1 YBIT3 YBIT2 YBIT1 C DC RBNKS3 RBNKS2 RBNKS1 LCDENB LCDBIAS LCDRATE GS2 GS1 GS0 CHS2 CHS1 AMPCKS2 AMPCKS1 IRVS RVS1 RVS0 ADCKS3 ADCKS2 ADCKS1 CPSTS CPAUTO CPON CPCKS3 CPCKS2 CPCKS1 WRS0 ADCB3 ADCB2 ADCB1 ADCB11 ADCB11 ADCB10 ADCB10 ADCB9 LBTO P41IO P41IO Bit0 RBIT0 ZBIT0 YBIT0 Z RBNKS0 LCDCLK AMPENB CHS0 AMPCKS0 ADCENB ADCKS0 CPRENB CPCKS0 DRDY ADCB0 ADCB8 LBTENB R/W R/W R/W R/W R/W R/W R/W R/W R/W W R/W W R/W W R/W R R R/W R Z Y PFLAG RBANK LCDM1 AMPM AMPCHS AMPCKS ADCM ADCKS CPM CPCKS DFM ADCDL ADCDH LBTM R/W R/W R/W R/W W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R R/W R/W R/W R/W W W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W ROMADRH ROMADRL ROMDAH ROMDAL ROMCNT PEDGE P1M P2M INTRQ INTEN OSCM PCL PCH P0 P1 P2 P4 P5 T0M T0C STKP P1UR P2UR @YZ STK7L STK7H STK6L STK6H STK5L STK5H STK4L STK4H STK3L STK3H STK2L STK2H VPPCHK ROMADR14 ROMADR14 ROMADR13 ROMADR13 ROMADR12 ROMADR12 ROMADR11 ROMADR11 ROMADR10 ROMADR10 ROMADR9 ROMADR8 ROMADR7 ROMADR6 ROMADR5 ROMADR4 ROMADR3 ROMADR2 ROMADR1 ROMADR0 ROMDA15 ROMDA15 ROMDA14 ROMDA14 ROMDA13 ROMDA13 ROMDA12 ROMDA12 ROMDA11 ROMDA11 ROMDA10 ROMDA10 ROMDA9 ROMDA8 ROMDA7 ROMDA6 ROMDA5 ROMDA4 ROMDA3 ROMDA2 ROMDA1 ROMDA0 ROMCNT7 ROMCNT6 ROMCNT5 ROMCNT4 ROMCNT3 ROMCNT2 ROMCNT1 ROMCNT0 PEDGEN WTCKS PC7 T0ENB T0C7 GIE @YZ7 S7PC7 S6PC7 S5PC7 S4PC7 S3PC7 S2PC7 - WDRST PC6 T0RATE2 T0C6 @YZ6 S7PC6 S6PC6 S5PC6 S4PC6 S3PC6 S2PC6 - P00G1 P00G1 P00G0 P00G0 P13M T0IRQ T0IEN WDARTE CPUM0 PC5 PC4 PC3 P13 T0RATE1 T0RATE0 T0C5 T0C4 T0C3 STKPB3 P13R @YZ5 @YZ4 @YZ3 S7PC5 S7PC4 S7PC3 S6PC5 S6PC4 S6PC3 S5PC5 S5PC4 S5PC3 S4PC5 S4PC4 S4PC3 S3PC5 S3PC4 S3PC3 S2PC5 S2PC4 S2PC3 - P12M CLKMD PC2 PC10 P12 P42 P52 T0C2 STKPB2 P12R @YZ2 S7PC2 S7PC10 S7PC10 S6PC2 S6PC10 S6PC10 S5PC2 S5PC10 S5PC10 S4PC2 S4PC10 S4PC10 S3PC2 S3PC10 S3PC10 S2PC2 S2PC10 S2PC10 P11M P21M STPHX PC1 PC9 P11 P21 P41 P51 T0C1 STKPB1 P11R P21R @YZ1 S7PC1 S7PC9 S6PC1 S6PC9 S5PC1 S5PC9 S4PC1 S4PC9 S3PC1 S3PC9 S2PC1 S2PC9 P10M P20M P00IRQ P00IRQ P00IEN P00IEN PC0 PC8 P00 P10 P20 P40 P50 T0C0 STKPB0 P10R P20R @YZ0 S7PC0 S7PC8 S6PC0 S6PC8 S5PC0 S5PC8 S4PC0 S4PC8 S3PC0 S3PC8 S2PC0 S2PC8 SONiX TECHNOLOGY CO., LTD Page 26 Name Version 1.0 SN8P1927 SN8P1927 8-Bit Micro-Controller with Charge pump Regulator, PGIA, 16-bit ADC 0FCH 0FDH 0FEH 0FFH S1PC7 S0PC7 - S1PC6 S0PC6 - S1PC5 S0PC5 - S1PC4 S1PC3 S0PC4 S0PC3 S1PC2 S1PC10 S1PC10 S0PC2 S0PC10 S0PC10 S1PC1 S1PC9 S0PC1 S0PC9 S1PC0 S1PC8 S0PC0 S0PC8 R/W R/W R/W R/W STK1L STK1H STK0L STK0H Note: 1. To avoid system error, make sure to put all the "0" and "1" as it indicates in the above table. 2. All of register names had been declared in SN8ASM assembler. 3. One-bit name had been declared in SN8ASM assembler with "F" prefix code. 4. "b0bset", "b0bclr", "bset", "bclr" instructions are only available to the "R/W" registers. SONiX TECHNOLOGY CO., LTD Page 27 Version 1.0 SN8P1927 SN8P1927 8-Bit Micro-Controller with Charge pump Regulator, PGIA, 16-bit ADC 2.1.4.4 ACCUMULATOR The ACC is an 8-bit data register responsible for transferring or manipulating data between ALU and data memory. If the result of operating is zero (Z) or there is carry (C or DC) occurrence, then these flags will be set to PFLAG register. ACC is not in data memory (RAM), so ACC can't be access by "B0MOV" instruction during the instant addressing mode. Example: Read and write ACC value. ; Read ACC data and store in BUF data memory MOV BUF, A ; Write a immediate data into ACC MOV A, #0FH ; Write ACC data from BUF data memory MOV A, BUF The system doesn't store ACC and PFLAG value when interrupt executed. ACC and PFLAG data must be saved to other data memories by program. Example: Protect ACC and working registers. .DATA ACCBUF DS 1 PFLAGBUF DS 1 ; Define ACCBUF for store ACC data. ; Define PFLAGBUF for store PFLAG data. B0XCH B0MOV B0MOV . . B0MOV B0MOV B0XCH RETI ; Save ACC in a buffer. .CODE INT_SERVICE: A, ACCBUF A, PFLAG PFLAGBUF, A A, PFLAGBUF PFLAG, A A, ACCBUF ; Save PFLAG register in a buffer. ; Restore PFLAG register from buffer. ; Restore ACC from buffer. ; Exit interrupt service vector Note: To save and re-load ACC data, users must use "B0XCH" instruction, or else the PFLAG Register might be modified by ACC operation. SONiX TECHNOLOGY CO., LTD Page 28 Version 1.0 SN8P1927 SN8P1927 8-Bit Micro-Controller with Charge pump Regulator, PGIA, 16-bit ADC 2.1.4.5 PROGRAM FLAG The PFLAG register contains the arithmetic status of ALU operation, C, DC, Z bits indicate the result status of ALU operation. 086H PFLAG Read/Write After reset Bit 7 - Bit 6 - Bit 5 - Bit 4 - Bit 3 - Bit 2 C R/W 0 Bit 1 DC R/W 0 Bit 0 Z R/W 0 Bit 2 C: Carry flag 1 = Addition with carry, subtraction without borrowing, rotation with shifting out logic "1", comparison result 0. 0 = Addition without carry, subtraction with borrowing signal, rotation with shifting out logic "0", comparison result < 0. Bit 1 DC: Decimal carry flag 1 = Addition with carry from low nibble, subtraction without borrow from high nibble. 0 = Addition without carry from low nibble, subtraction with borrow from high nibble. Bit 0 Z: Zero flag 1 = The result of an arithmetic/logic/branch operation is zero. 0 = The result of an arithmetic/logic/branch operation is not zero. Note: Refer to instruction set table for detailed information of C, DC and Z flags. SONiX TECHNOLOGY CO., LTD Page 29 Version 1.0 SN8P1927 SN8P1927 8-Bit Micro-Controller with Charge pump Regulator, PGIA, 16-bit ADC 2.1.4.6 PROGRAM COUNTER The program counter (PC) is a 11-bit binary counter separated into the high-byte 3 and the low-byte 8 bits. This counter is responsible for pointing a location in order to fetch an instruction for kernel circuit. Normally, the program counter is automatically incremented with each instruction during program execution. Besides, it can be replaced with specific address by executing CALL or JMP instruction. When JMP or CALL instruction is executed, the destination address will be inserted to bit 0 ~ bit 10. PC After reset Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 PC10 PC9 - - - - - 0 0 Bit 8 PC8 Bit 7 PC7 Bit 6 PC6 Bit 5 PC5 Bit 4 PC4 Bit 3 PC3 Bit 2 PC2 Bit 1 PC1 Bit 0 PC0 0 0 0 0 0 0 0 0 0 PCH PCL ONE ADDRESS SKIPPING There are nine instructions (CMPRS, INCS, INCMS, DECS, DECMS, BTS0, BTS1, B0BTS0, B0BTS1) with one address skipping function. If the result of these instructions is true, the PC will add 2 steps to skip next instruction. If the condition of bit test instruction is true, the PC will add 2 steps to skip next instruction. FC C0STEP ; To skip, if Carry_flag = 1 ; Else jump to C0STEP. C0STEP: B0BTS1 JMP . . NOP A, BUF0 FZ C1STEP ; Move BUF0 value to ACC. ; To skip, if Zero flag = 0. ; Else jump to C1STEP. C1STEP: B0MOV B0BTS0 JMP . . NOP If the ACC is equal to the immediate data or memory, the PC will add 2 steps to skip next instruction. C0STEP: CMPRS JMP . . NOP A, #12H C0STEP SONiX TECHNOLOGY CO., LTD ; To skip, if ACC = 12H. ; Else jump to C0STEP. Page 30 Version 1.0 SN8P1927 SN8P1927 8-Bit Micro-Controller with Charge pump Regulator, PGIA, 16-bit ADC If the destination increased by 1, which results overflow of 0xFF to 0x00, the PC will add 2 steps to skip next instruction. INCS instruction: C0STEP: INCS JMP . . NOP BUF0 C0STEP ; Jump to C0STEP if ACC is not zero. INCMS JMP . . NOP BUF0 C0STEP ; Jump to C0STEP if BUF0 is not zero. INCMS instruction: C0STEP: If the destination decreased by 1, which results underflow of 0x00 to 0xFF, the PC will add 2 steps to skip next instruction. DECS instruction: C0STEP: DECS JMP . . NOP BUF0 C0STEP ; Jump to C0STEP if ACC is not zero. DECMS JMP . . NOP BUF0 C0STEP ; Jump to C0STEP if BUF0 is not zero. DECMS instruction: C0STEP: SONiX TECHNOLOGY CO., LTD Page 31 Version 1.0 SN8P1927 SN8P1927 8-Bit Micro-Controller with Charge pump Regulator, PGIA, 16-bit ADC MULTI-ADDRESS JUMPING Users can jump around the multi-address by either JMP instruction or ADD M, A instruction (M = PCL) to activate multi-address jumping function. Program counter can't carry to PCH when PCL overflow automatically after executing addition instructions. Users have to take care program counter result and adjust PCH value by program. For jump table or others applications, users have to calculate PC value to avoid PCL overflow making PC error and program executing error. Note: Program counter can't carry to PCH when PCL overflow automatically after executing addition instructions. Users have to take care program counter result and adjust PCH value by program. Example: If PC = 0323H 0323H (PCH = 03H, PCL = 23H) ; PC = 0323H 0323H MOV B0MOV . A, #28H PCL, A ; Jump to address 0328H 0328H MOV B0MOV . A, #00H PCL, A ; Jump to address 0300H 0300H ; PC = 0328H 0328H Example: If PC = 0323H 0323H (PCH = 03H, PCL = 23H) ; PC = 0323H 0323H B0ADD JMP JMP JMP JMP . . PCL, A A0POINT A1POINT A2POINT A3POINT SONiX TECHNOLOGY CO., LTD ; PCL = PCL + ACC, the PCH cannot be changed. ; If ACC = 0, jump to A0POINT ; ACC = 1, jump to A1POINT ; ACC = 2, jump to A2POINT ; ACC = 3, jump to A3POINT Page 32 Version 1.0 SN8P1927 SN8P1927 8-Bit Micro-Controller with Charge pump Regulator, PGIA, 16-bit ADC 2.1.4.7 Y, Z REGISTERS The Y and Z registers are the 8-bit buffers. There are three major functions of these registers. can be used as general working registers can be used as RAM data pointers with @YZ register can be used as ROM data pointer with the MOVC instruction for look-up table 084H Y Read/Write After reset Bit 7 YBIT7 R/W - Bit 6 YBIT6 R/W - Bit 5 YBIT5 R/W - Bit 4 YBIT4 R/W - Bit 3 YBIT3 R/W - Bit 2 YBIT2 R/W - Bit 1 YBIT1 R/W - Bit 0 YBIT0 R/W - 083H Z Read/Write After reset Bit 7 ZBIT7 R/W - Bit 6 ZBIT6 R/W - Bit 5 ZBIT5 R/W - Bit 4 ZBIT4 R/W - Bit 3 ZBIT3 R/W - Bit 2 ZBIT2 R/W - Bit 1 ZBIT1 R/W - Bit 0 ZBIT0 R/W - Example: Uses Y, Z register as the data pointer to access data in the RAM address 025H of bank0. B0MOV B0MOV B0MOV Y, #00H Z, #25H A, @YZ ; To set RAM bank 0 for Y register ; To set location 25H for Z register ; To read a data into ACC Example: Uses the Y, Z register as data pointer to clear the RAM data. B0MOV B0MOV Y, #0 Z, #07FH ; Y = 0, bank 0 ; Z = 7FH, the last address of the data memory area CLR @YZ ; Clear @YZ to be zero DECMS JMP Z CLR_YZ_BUF ; Z ­ 1, if Z= 0, finish the routine ; Not zero CLR @YZ CLR_YZ_BUF: END_CLR: ; End of clear general purpose data memory area of bank 0 . SONiX TECHNOLOGY CO., LTD Page 33 Version 1.0 SN8P1927 SN8P1927 8-Bit Micro-Controller with Charge pump Regulator, PGIA, 16-bit ADC 2.1.4.8 R REGISTERS R register is an 8-bit buffer. There are two major functions of the register. Can be used as working register For store high-byte data of look-up table (MOVC instruction executed, the high-byte data of specified ROM address will be stored in R register and the low-byte data will be stored in ACC). 082H R Read/Write After reset Bit 7 RBIT7 R/W - Bit 6 RBIT6 R/W - Bit 5 RBIT5 R/W - Bit 4 RBIT4 R/W - Bit 3 RBIT3 R/W - Bit 2 RBIT2 R/W - Bit 1 RBIT1 R/W - Bit 0 RBIT0 R/W - Note: Please refer to the "LOOK-UP TABLE DESCRIPTION" about R register look-up table application. SONiX TECHNOLOGY CO., LTD Page 34 Version 1.0 SN8P1927 SN8P1927 8-Bit Micro-Controller with Charge pump Regulator, PGIA, 16-bit ADC 2.2 ADDRESSING MODE 2.2.1 IMMEDIATE ADDRESSING MODE The immediate addressing mode uses an immediate data to set up the location in ACC or specific RAM. Example: Move the immediate data 12H to ACC. MOV A, #12H ; To set an immediate data 12H into ACC. Example: Move the immediate data 12H to R register. B0MOV R, #12H ; To set an immediate data 12H into R register. Note: In immediate addressing mode application, the specific RAM must be 0x80~0x87 working register. 2.2.2 DIRECTLY ADDRESSING MODE The directly addressing mode moves the content of RAM location in or out of ACC. Example: Move 0x12 RAM location data into ACC. B0MOV A, 12H ; To get a content of RAM location 0x12 of bank 0 and save in ACC. Example: Move ACC data into 0x12 RAM location. B0MOV 12H, A ; To get a content of ACC and save in RAM location 12H of bank 0. 2.2.3 INDIRECTLY ADDRESSING MODE The indirectly addressing mode is to access the memory by the data pointer registers (Y/Z). Example: Indirectly addressing mode with @YZ register. B0MOV B0MOV B0MOV Y, #0 Z, #12H A, @YZ SONiX TECHNOLOGY CO., LTD ; To clear Y register to access RAM bank 0. ; To set an immediate data 12H into Z register. ; Use data pointer @YZ reads a data from RAM location ; 012H into ACC. Page 35 Version 1.0 SN8P1927 SN8P1927 8-Bit Micro-Controller with Charge pump Regulator, PGIA, 16-bit ADC 2.3 STACK OPERATION 2.3.1 OVERVIEW The stack buffer has 8-level. These buffers are designed to push and pop up program counter's (PC) data when interrupt service routine and "CALL" instruction are executed. The STKP register is a pointer designed to point active level in order to push or pop up data from stack buffer. The STKnH and STKnL are the stack buffers to store program counter (PC) data. RET / RETI CALL / INTERRUPT STACK Buffer High Byte STACK Buffer Low Byte STKP = 7 STK7H STK7L STKP = 6 STKP - 1 PCL STACK Level STKP + 1 PCH STK6H STK6L STKP = 5 STK5H STKP STK5L STKP STKP = 4 STK4L STKP = 3 STK3H STK3L STKP = 2 STK2H STK2L STKP = 1 STK1H STK1L STKP = 0 SONiX TECHNOLOGY CO., LTD STK4H STK0H STK0L Page 36 Version 1.0 SN8P1927 SN8P1927 8-Bit Micro-Controller with Charge pump Regulator, PGIA, 16-bit ADC 2.3.2 STACK REGISTERS The stack pointer (STKP) is a 3-bit register to store the address used to access the stack buffer, 11-bit data memory (STKnH and STKnL) set aside for temporary storage of stack addresses. The two stack operations are writing to the top of the stack (push) and reading from the top of stack (pop). Push operation decrements the STKP and the pop operation increments each time. That makes the STKP always point to the top address of stack buffer and write the last program counter value (PC) into the stack buffer. The program counter (PC) value is stored in the stack buffer before a CALL instruction executed or during interrupt service routine. Stack operation is a LIFO type (Last in and first out). The stack pointer (STKP) and stack buffer (STKnH and STKnL) are located in the system register area bank 0. 0DFH STKP Read/Write After reset Bit 7 GIE R/W 0 Bit 6 - Bit 5 - Bit 4 - Bit[2:0] Bit 2 STKPB2 R/W 1 Bit 1 STKPB1 R/W 1 Bit 0 STKPB0 R/W 1 STKPBn: Stack pointer (n = 0 ~ 2) Bit 7 Bit 3 - GIE: Global interrupt control bit. 0 = Disable. 1 = Enable. Please refer to the interrupt chapter. Example: Stack pointer (STKP) reset, we strongly recommended to clear the stack pointer in the beginning of the program. MOV B0MOV A, #00000111B 00000111B STKP, A 0F0H~0FFH STKnH Read/Write After reset Bit 7 - Bit 6 - Bit 5 - Bit 4 - Bit 3 - Bit 2 SnPC10 R/W 0 Bit 1 SnPC9 R/W 0 Bit 0 SnPC8 R/W 0 0F0H~0FFH STKnL Read/Write After reset Bit 7 SnPC7 R/W 0 Bit 6 SnPC6 R/W 0 Bit 5 SnPC5 R/W 0 Bit 4 SnPC4 R/W 0 Bit 3 SnPC3 R/W 0 Bit 2 SnPC2 R/W 0 Bit 1 SnPC1 R/W 0 Bit 0 SnPC0 R/W 0 STKn = STKnH , STKnL (n = 7 ~ 0) SONiX TECHNOLOGY CO., LTD Page 37 Version 1.0 SN8P1927 SN8P1927 8-Bit Micro-Controller with Charge pump Regulator, PGIA, 16-bit ADC 2.3.3 STACK OPERATION EXAMPLE The two kinds of Stack-Save operations refer to the stack pointer (STKP) and write the content of program counter (PC) to the stack buffer are CALL instruction and interrupt service. Under each condition, the STKP decreases and points to the next available stack location. The stack buffer stores the program counter about the op-code address. The Stack-Save operation is as the following table. Stack Level 0 1 2 3 4 5 6 7 8 >8 STKPB2 STKP Register STKPB1 STKPB0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 1 0 1 0 1 0 1 0 1 0 Stack Buffer High Byte Low Byte Free STK0H STK1H STK2H STK3H STK4H STK5H STK6H STK7H - Free STK0L STK1L STK2L STK3L STK4L STK5L STK6L STK7L - Description Stack Over, error There are Stack-Restore operations correspond to each push operation to restore the program counter (PC). The RETI instruction uses for interrupt service routine. The RET instruction is for CALL instruction. When a pop operation occurs, the STKP is incremented and points to the next free stack location. The stack buffer restores the last program counter (PC) to the program counter registers. The Stack-Restore operation is as the following table. Stack Level 8 7 6 5 4 3 2 1 0 STKP Register STKPB2 STKPB1 STKPB0 1 0 0 0 0 1 1 1 1 SONiX TECHNOLOGY CO., LTD 1 0 0 1 1 0 0 1 1 1 0 1 0 1 0 1 0 1 Stack Buffer High Byte Low Byte STK7H STK6H STK5H STK4H STK3H STK2H STK1H STK0H Free Page 38 STK7L STK6L STK5L STK4L STK3L STK2L STK1L STK0L Free Description - Version 1.0 SN8P1927 SN8P1927 8-Bit Micro-Controller with Charge pump Regulator, PGIA, 16-bit ADC 3 RESET 3.1 OVERVIEW The system would be reset in three conditions as following. Power on reset Watchdog reset Brown out reset External reset When any reset condition occurs, all system registers keep initial status, program stops and program counter is cleared. After reset status released, the system boots up and program starts to execute from ORG 0. Finishing any reset sequence needs some time. The system provides complete procedures to make the power on reset successful. For different oscillator types, the reset time is different. That causes the VDD rise rate and start-up time of different oscillator is not fixed. RC type oscillator's start-up time is very short, but the crystal type is longer. Under client terminal application, users have to take care the power on reset time for the master terminal requirement. The reset timing diagram is as following. VDD Power LVD Detect Level VSS VDD External Reset VSS External Reset Low Detect External Reset High Detect Watchdog Overflow Watchdog Normal Run Watchdog Reset Watchdog Stop System Normal Run System Status System Stop Power On Delay Time SONiX TECHNOLOGY CO., LTD External Reset Delay Time Page 39 Watchdog Reset Delay Time Version 1.0 SN8P1927 SN8P1927 8-Bit Micro-Controller with Charge pump Regulator, PGIA, 16-bit ADC 3.2 POWER ON RESET The power on reset depend no LVD operation for most power-up situations. The power supplying to system is a rising curve and needs some time to achieve the normal voltage. Power on reset sequence is as following. Power-up: System detects the power voltage up and waits for power stable. External reset: System checks external reset pin status. If external reset pin is not high level, the system keeps reset status and waits external reset pin released. System initialization: All system registers is set as initial conditions and system is ready. Oscillator warm up: Oscillator operation is successfully and supply to system clock. Program executing: Power on sequence is finished and program executes from ORG 0. 3.3 WATCHDOG RESET Watchdog reset is a system protection. In normal condition, system works well and clears watchdog timer by program. Under error condition, system is in unknown situation and watchdog can't be clear by program before watchdog timer overflow. Watchdog timer overflow occurs and the system is reset. After watchdog reset, the system restarts and returns normal mode. Watchdog reset sequence is as following. Watchdog timer status: System checks watchdog timer overflow status. If watchdog timer overflow occurs, the system is reset. System initialization: All system registers is set as initial conditions and system is ready. Oscillator warm up: Oscillator operation is successfully and supply to system clock. Program executing: Power on sequence is finished and program executes from ORG 0. Watchdog timer application note is as following. Before clearing watchdog timer, check I/O status and check RAM contents can improve system error. Don't clear watchdog timer in interrupt vector and interrupt service routine. That can improve main routine fail. Clearing watchdog timer program is only at one part of the program. This way is the best structure to enhance the watchdog timer function. Note: Please refer to the "WATCHDOG TIMER" about watchdog timer detail information. SONiX TECHNOLOGY CO., LTD Page 40 Version 1.0 SN8P1927 SN8P1927 8-Bit Micro-Controller with Charge pump Regulator, PGIA, 16-bit ADC 3.4 BROWN OUT RESET 3.4.1 BROWN OUT DESCRIPTION The brown out reset is a power dropping condition. The power drops from normal voltage to low voltage by external factors (e.g. EFT interference or external loading changed). The brown out reset would make the system not work well or executing program error. VDD System Work Well Area V1 V2 V3 System Work Error Area VSS Brown Out Reset Diagram The power dropping might through the voltage range that's the system dead-band. The dead-band means the power range can't offer the system minimum operation power requirement. The above diagram is a typical brown out reset diagram. There is a serious noise under the VDD, and VDD voltage drops very deep. There is a dotted line to separate the system working area. The above area is the system work well area. The below area is the system work error area called dead-band. V1 doesn't touch the below area and not effect the system operation. But the V2 and V3 is under the below area and may induce the system error occurrence. Let system under dead-band includes some conditions. DC application: The power source of DC application is usually using battery. When low battery condition and MCU drive any loading, the power drops and keeps in dead-band. Under the situation, the power won't drop deeper and not touch the system reset voltage. That makes the system under dead-band. AC application: In AC power application, the DC power is regulated from AC power source. This kind of power usually couples with AC noise that makes the DC power dirty. Or the external loading is very heavy, e.g. driving motor. The loading operating induces noise and overlaps with the DC power. VDD drops by the noise, and the system works under unstable power situation. The power on duration and power down duration are longer in AC application. The system power on sequence protects the power on successful, but the power down situation is like DC low battery condition. When turn off the AC power, the VDD drops slowly and through the dead-band for a while. SONiX TECHNOLOGY CO., LTD Page 41 Version 1.0 SN8P1927 SN8P1927 8-Bit Micro-Controller with Charge pump Regulator, PGIA, 16-bit ADC 3.4.2 THE SYSTEM OPERATING VOLTAGE DECSRIPTION To improve the brown out reset needs to know the system minimum operating voltage which is depend on the system executing rate and power level. Different system executing rates have different system minimum operating voltage. The electrical characteristic section shows the system voltage to executing rate relationship. System Mini. Operating Voltage. Vdd (V) Normal Operating Area Dead-Band Area Reset Area System Reset Voltage. System Rate (Fcpu) Normally the system operation voltage area is higher than the system reset voltage to VDD, and the reset voltage is decided by LVD detect level. The system minimum operating voltage rises when the system executing rate upper even higher than system reset voltage. The dead-band definition is the system minimum operating voltage above the system reset voltage. 3.4.3 BROWN OUT RESET IMPROVEMENT How to improve the brown reset condition? There are some methods to improve brown out reset as following. LVD reset Watchdog reset Reduce the system executing rate External reset circuit. (Zener diode reset circuit, Voltage bias reset circuit, External reset IC) Note: 1. The " Zener diode reset circuit", "Voltage bias reset circuit" and "External reset IC" can completely improve the brown out reset, DC low battery and AC slow power down conditions. 2. For AC power application and enhance EFT performance, the system clock is 4MHz/4 (1 mips) and use external reset (" Zener diode reset circuit", "Voltage bias reset circuit", "External reset IC"). The structure can improve noise effective and get good EFT characteristic. SONiX TECHNOLOGY CO., LTD Page 42 Version 1.0 SN8P1927 SN8P1927 8-Bit Micro-Controller with Charge pump Regulator, PGIA, 16-bit ADC LVD reset: VDD Power LVD Detect Voltage VSS Power is below LVD Detect Voltage and System Reset. System Normal Run System Status System Stop Power On Delay Time The LVD (low voltage detector) is built-in Sonix 8-bit MCU to be brown out reset protection. When the VDD drops and is below LVD detect voltage, the LVD would be triggered, and the system is reset. The LVD detect level is different by each MCU. The LVD voltage level is a point of voltage and not easy to cover all dead-band range. Using LVD to improve brown out reset is depend on application requirement and environment. If the power variation is very deep, violent and trigger the LVD, the LVD can be the protection. If the power variation can touch the LVD detect level and make system work error, the LVD can't be the protection and need to other reset methods. More detail LVD information is in the electrical characteristic section. Watchdog reset: The watchdog timer is a protection to make sure the system executes well. Normally the watchdog timer would be clear at one point of program. Don't clear the watchdog timer in several addresses. The system executes normally and the watchdog won't reset system. When the system is under dead-band and the execution error, the watchdog timer can't be clear by program. The watchdog is continuously counting until overflow occurrence. The overflow signal of watchdog timer triggers the system to reset, and the system return to normal mode after reset sequence. This method also can improve brown out reset condition and make sure the system to return normal mode. If the system reset by watchdog and the power is still in dead-band, the system reset sequence won't be successful and the system stays in reset status until the power return to normal range. Reduce the system executing rate: If the system rate is fast and the dead-band exists, to reduce the system executing rate can improve the dead-band. The lower system rate is with lower minimum operating voltage. Select the power voltage that's no dead-band issue and find out the mapping system rate. Adjust the system rate to the value and the system exits the dead-band issue. This way needs to modify whole program timing to fit the application requirement. External reset circuit: The external reset methods also can improve brown out reset and is the complete solution. There are three external reset circuits to improve brown out reset including "Zener diode reset circuit", "Voltage bias reset circuit" and "External reset IC". These three reset structures use external reset signal and control to make sure the MCU be reset under power dropping and under dead-band. The external reset information is described in the next section. SONiX TECHNOLOGY CO., LTD Page 43 Version 1.0 SN8P1927 SN8P1927 8-Bit Micro-Controller with Charge pump Regulator, PGIA, 16-bit ADC 3.5 EXTERNAL RESET External reset pin is Schmitt Trigger structure and low level active. The system is running when reset pin is high level voltage input. The reset pin receives the low voltage and the system is reset. The external reset operation actives in power on and normal running mode. During system power-up, the external reset pin must be high level input, or the system keeps in reset status. External reset sequence is as following. External reset: System checks external reset pin status. If external reset pin is not high level, the system keeps reset status and waits external reset pin released. System initialization: All system registers is set as initial conditions and system is ready. Oscillator warm up: Oscillator operation is successfully and supply to system clock. Program executing: Power on sequence is finished and program executes from ORG 0. The external reset can reset the system during power on duration, and good external reset circuit can protect the system to avoid working at unusual power condition, e.g. brown out reset in AC power application. 3.6 EXTERNAL RESET CIRCUIT 3.6.1 Simply RC Reset Circuit VDD R1 47K ohm R2 RST 100 ohm MCU C1 0.1uF VSS VCC GND This is the basic reset circuit, and only includes R1 and C1. The RC circuit operation makes a slow rising signal into reset pin as power up. The reset signal is slower than VDD power up timing, and system occurs a power on signal from the timing difference. Note: The reset circuit is no any protection against unusual power or brown out reset. SONiX TECHNOLOGY CO., LTD Page 44 Version 1.0 SN8P1927 SN8P1927 8-Bit Micro-Controller with Charge pump Regulator, PGIA, 16-bit ADC 3.6.2 Diode & RC Reset Circuit VDD R1 47K ohm DIODE R2 RST MCU 100 ohm C1 0.1uF VSS VCC GND This is the better reset circuit. The R1 and C1 circuit operation is like the simply reset circuit to make a power on signal. The reset circuit has a simply protection against unusual power. The diode offers a power positive path to conduct higher power to VDD. It is can make reset pin voltage level to synchronize with VDD voltage. The structure can improve slight brown out reset condition. Note: The R2 100 ohm resistor of "Simply reset circuit" and "Diode & RC reset circuit" is necessary to limit any current flowing into reset pin from external capacitor C in the event of reset pin breakdown due to Electrostatic Discharge (ESD) or Electrical Over-stress (EOS). 3.6.3 Zener Diode Reset Circuit VDD R1 33K ohm E R2 B 10K ohm Vz Q1 C RST MCU R3 40K ohm VSS VCC GND The zener diode reset circuit is a simple low voltage detector and can improve brown out reset condition completely. Use zener voltage to be the active level. When VDD voltage level is above "Vz + 0.7V", the C terminal of the PNP transistor outputs high voltage and MCU operates normally. When VDD is below "Vz + 0.7V", the C terminal of the PNP transistor outputs low voltage and MCU is in reset mode. Decide the reset detect voltage by zener specification. Select the right zener voltage to conform the application. SONiX TECHNOLOGY CO., LTD Page 45 Version 1.0 SN8P1927 SN8P1927 8-Bit Micro-Controller with Charge pump Regulator, PGIA, 16-bit ADC 3.6.4 Voltage Bias Reset Circuit VDD R1 47K ohm E B Q1 C R2 10K ohm RST MCU R3 2K ohm VSS VCC GND The voltage bias reset circuit is a low cost voltage detector and can improve brown out reset condition completely. The operating voltage is not accurate as zener diode reset circuit. Use R1, R2 bias voltage to be the active level. When VDD voltage level is above or equal to "0.7V x (R1 + R2) / R1", the C terminal of the PNP transistor outputs high voltage and MCU operates normally. When VDD is below "0.7V x (R1 + R2) / R1", the C terminal of the PNP transistor outputs low voltage and MCU is in reset mode. Decide the reset detect voltage by R1, R2 resistances. Select the right R1, R2 value to conform the application. In the circuit diagram condition, the MCU's reset pin level varies with VDD voltage variation, and the differential voltage is 0.7V. If the VDD drops and the voltage lower than reset pin detect level, the system would be reset. If want to make the reset active earlier, set the R2 > R1 and the cap between VDD and C terminal voltage is larger than 0.7V. The external reset circuit is with a stable current through R1 and R2. For power consumption issue application, e.g. DC power system, the current must be considered to whole system power consumption. Note: Under unstable power condition as brown out reset, "Zener diode rest circuit" and "Voltage bias reset circuit" can protects system no any error occurrence as power dropping. When power drops below the reset detect voltage, the system reset would be triggered, and then system executes reset sequence. That makes sure the system work well under unstable power situation. 3.6.5 External Reset IC VDD VDD Bypass Capacitor 0.1uF Reset IC RST RST MCU VSS VSS VCC GND SONiX TECHNOLOGY CO., LTD Page 46 Version 1.0 SN8P1927 SN8P1927 8-Bit Micro-Controller with Charge pump Regulator, PGIA, 16-bit ADC 4 SYSTEM CLOCK 4.1 OVERVIEW The micro-controller is a dual clock system. There are high-speed clock and low-speed clock. The high-speed clock is generated from the external oscillator circuit or on-chip 16MHz high-speed RC oscillator circuit (IHRC 16MHz). The low-speed clock is generated from on-chip low speed RC oscillator circuit (ILRC 16KHz@3V, 32KHz@5V) Both the high-speed clock and the low-speed clock can be system clock (Fosc). The system clock in slow mode is divided by 4 to be the instruction cycle (Fcpu). Normal Mode (High Clock): Fcpu = Fhosc / 4, (Fhosc= 4M/8M crystal) Fcpu = Fhosc / 16, (Fhosc=IHRC) Slow Mode (Low Clock): Fcpu = Flosc/4. 4.2 CLOCK BLOCK DIAGRAM STPHX XIN XOUT HOSC Fhosc. CLKMD Fcpu = Fhosc/4 (Fhosc=4M crystal) Fcpu = Fhosc/16 (Fhosc=IHRC) Fosc Fcpu Fosc CPUM[1:0] Flosc. Fcpu = Flosc/4 HOSC: High_Clk code option. Fhosc: External high-speed clock / Internal high-speed RC clock. Flosc: Internal low-speed RC clock .(About 16KHz@3V, 32KHz@5V) Fosc: System clock source. Fcpu: Instruction cycle. SONiX TECHNOLOGY CO., LTD Page 47 Version 1.0 SN8P1927 SN8P1927 8-Bit Micro-Controller with Charge pump Regulator, PGIA, 16-bit ADC 4.3 OSCM REGISTER The OSCM register is an oscillator control register. It controls oscillator status, system mode. 0CAH OSCM Read/Write After reset Bit 7 WTCKS R/W 0 Bit 6 WDRST R/W 0 Bit 5 WDRATE R/W 0 Bit 4 - Bit 3 CPUM0 R/W 0 Bit 2 CLKMD R/W 0 Bit 1 STPHX R/W 0 Bit 0 0 - Bit 1 STPHX: External high-speed oscillator control bit. 0 = External high-speed oscillator free run. 1 = External high-speed oscillator free run stop. Internal low-speed RC oscillator is still running. Bit 2 CLKMD: System high/Low clock mode control bit. 0 = Normal (dual) mode. System clock is high clock. 1 = Slow mode. System clock is external low clock. Bit[4:3] CPUM0: CPU operating mode control bits. 0 = normal. 1 = sleep (power down) mode. Bit5 WDRATE: Watchdog timer rate select bit. 0 = FCPU ÷ 214 1 = FCPU ÷ 28 Bit6 WDRST: Watchdog timer reset bit. 0 = No reset 1 = clear the watchdog timer's counter. (The detail information is in watchdog timer chapter.) Bit7 WTCKS: Watchdog clock source select bit. 0 = FCPU 1 = internal RC low clock. WTCKS WTRATE CLKMD Watchdog Timer Overflow Time 0 0 0 0 1 0 1 0 1 - 0 0 1 1 - 1 / ( fcpu ÷ 214 ÷ 16 ) = 293 ms, Fosc=3.58MHz 1 / ( fcpu ÷ 28 ÷ 16 ) = 500 ms, Fosc=32768Hz 1 / ( fcpu ÷ 214 ÷ 16 ) = 65.5s, Fosc=16KHz@3V 1 / ( fcpu ÷ 28 ÷ 16 ) = 1s, Fosc=16KHz@3V 1 / ( 16K ÷ 512 ÷ 16 ) ~ 0.5s @3V Example: Stop high-speed oscillator B0BSET FSTPHX ; To stop external high-speed oscillator only. Example: When entering the power down mode (sleep mode), both high-speed oscillator and internal low-speed oscillator will be stopped. B0BSET FCPUM0 SONiX TECHNOLOGY CO., LTD ; To stop external high-speed oscillator and internal low-speed ; oscillator called power down mode (sleep mode). Page 48 Version 1.0 SN8P1927 SN8P1927 8-Bit Micro-Controller with Charge pump Regulator, PGIA, 16-bit ADC 4.4 SYSTEM HIGH CLOCK The system high clock is from internal 16MHz oscillator RC type or external oscillator. The high clock type is controlled by "High_Clk" code option. High_Clk Code Option IHRC 4M Description The high clock is internal 16MHz oscillator RC type. XIN and XOUT pins are general purpose I/O pins. The high clock is external oscillator. The typical frequency is 4MHz. 4.4.1 INTERNAL HIGH RC The chip is built-in RC type internal high clock (16MHz) controlled by "IHRC_16M" code options. In "IHRC_16M" mode, the system clock is from internal 16MHz RC type oscillator and XIN / XOUT pins are general-purpose I/O pins. IHRC: High clock is internal 16MHz oscillator RC type. XIN/XOUT pins are general purpose I/O pins. 4.4.2 EXTERNAL HIGH CLOCK External high clock includes three modules (Crystal/Ceramic, RC and external clock signal). The high clock oscillator module is controlled by High_Clk code option. The start up time of crystal/ceramic and RC type oscillator is different. RC type oscillator's start-up time is very short, but the crystal's is longer. The oscillator start-up time decides reset time length. 4MHz Crystal SONiX TECHNOLOGY CO., LTD 4MHz Ceramic Page 49 Version 1.0 SN8P1927 SN8P1927 8-Bit Micro-Controller with Charge pump Regulator, PGIA, 16-bit ADC 4.4.2.1 CRYSTAL/CERAMIC Crystal/Ceramic devices are driven by XIN, XOUT pins. For high/normal/low frequency, the driving currents are different. High_Clk code option supports different frequencies. 4M option is for normal speed (ex. 4MHz). XIN CRYSTAL C 20pF XOUT MCU C VDD 20pF VSS VCC GND Note: Connect the Crystal/Ceramic and C as near as possible to the XIN/XOUT/VSS pins of micro-controller. 4.4.2.2 EXTERNAL CLOCK SIGNAL Selecting external clock signal input to be system clock is by RC option of High_Clk code option. The external clock signal is input from XIN pin. XOUT pin is general purpose I/O pin. SONiX TECHNOLOGY CO., LTD Page 50 Version 1.0 SN8P1927 SN8P1927 8-Bit Micro-Controller with Charge pump Regulator, PGIA, 16-bit ADC 4.5 SYSTEM LOW CLOCK The system low clock source is the internal low-speed oscillator built in the micro-controller. The low-speed oscillator uses RC type oscillator circuit. The frequency is affected by the voltage and temperature of the system. In common condition, the frequency of the RC oscillator is about 16KHz at 3V and 32KHz at 5V. The relation between the RC frequency and voltage is as the following figure. Internal Low RC Frequency 45.00 40.80 Freq. (KHz) 40.00 38.08 35.00 35.40 32.52 30.00 29.20 25.96 25.00 ILRC 22.24 20.00 15.00 14.72 16.00 17.24 18.88 10.64 10.00 7.52 5.00 0.00 2.1 2.5 3 3.1 3.3 3.5 4 4.5 5 5.5 6 6.5 7 VDD (V) The internal low RC supports watchdog clock source and system slow mode controlled by CLKMD. Flosc = Internal low RC oscillator (about 16KHz @3V, 32KHz @5V). Slow mode Fcpu = Flosc / 4 There are two conditions to stop internal low RC. One is power down mode, and the other is green mode of 32K mode and watchdog disable. If system is in 32K mode and watchdog disable, only 32K oscillator actives and system is under low power consumption. Example: Stop internal low-speed oscillator by power down mode. B0BSET FCPUM0 ; To stop external high-speed oscillator and internal low-speed ; oscillator called power down mode (sleep mode). Note: The internal low-speed clock can't be turned off individually. It is controlled by CPUM0 bits of OSCM register. SONiX TECHNOLOGY CO., LTD Page 51 Version 1.0 SN8P1927 SN8P1927 8-Bit Micro-Controller with Charge pump Regulator, PGIA, 16-bit ADC 4.5.1 SYSTEM CLOCK MEASUREMENT Under design period, the users can measure system clock speed by software instruction cycle (Fcpu). This way is useful in Low clock mode. Example: Fcpu instruction cycle of external oscillator. B0BSET P1M.0 ; Set P1.0 to be output mode for outputting Fcpu toggle signal. B0BSET B0BCLR JMP P1.0 P1.0 @B ; Output Fcpu toggle signal in low-speed clock mode. ; Measure the Fcpu frequency by oscilloscope. @@: SONiX TECHNOLOGY CO., LTD Page 52 Version 1.0 SN8P1927 SN8P1927 8-Bit Micro-Controller with Charge pump Regulator, PGIA, 16-bit ADC 5 SYSTEM OPERATION MODE 5.1 OVERVIEW The chip is featured with low power consumption by switching around four different modes as following. High-speed mode Low-speed mode Power-down mode (Sleep mode) Power Down Mode (Sleep Mode) P0, P1 Wake-up Function Active. External Reset Circuit Active. CPUM0 = 1. CLKMD = 1 Normal Mode CLKMD = 0 Slow Mode System Mode Switching Diagram Operating mode description MODE EHOSC IHRC ILRC CPU instruction T0 timer Watchdog timer Internal interrupt External interrupt Wakeup source POWER DOWN REMARK (SLEEP) Running By STPHX Stop Running By STPHX Stop Running Running Stop Executing Executing Stop *Active *Active Inactive * Active if T0ENB=1 By Watch_Dog By Watch_Dog By Watch_Dog Refer to code option Code option Code option Code option description All active All active All inactive All active All active All inactive P0, P1, Reset NORMAL SLOW EHOSC: External high clock IHRC: Internal high clock (16M RC oscillator) ILRC: Internal low clock (16K RC oscillator at 3V, 32K at 5V) SONiX TECHNOLOGY CO., LTD Page 53 Version 1.0 SN8P1927 SN8P1927 8-Bit Micro-Controller with Charge pump Regulator, PGIA, 16-bit ADC 5.2 SYSTEM MODE SWITCHING EXAMPLE Example: Switch normal/slow mode to power down (sleep) mode. B0BSET FCPUM0 ; Set CPUM0 = 1. Note: During the sleep, only the wakeup pin and reset can wakeup the system back to the normal mode. Example: Switch normal mode to slow mode. B0BSET B0BSET FCLKMD FSTPHX ;To set CLKMD = 1, Change the system into slow mode ;To stop external high-speed oscillator for power saving. Example: Switch slow mode to normal mode (The external high-speed oscillator is still running). B0BCLR FCLKMD ;To set CLKMD = 0 Example: Switch slow mode to normal mode (The external high-speed oscillator stops). If external high clock stop and program want to switch back normal mode. It is necessary to delay at least 10mS for external clock stable. B0BCLR ; Turn on the external high-speed oscillator. MOV B0MOV DECMS JMP A, #27 Z, A Z @B ; If VDD = 5V, internal RC=32KHz (typical) will delay B0BCLR @@: FSTPHX FCLKMD ; 0.125ms X 81 = 10.125ms for external clock stable ; ; Change the system back to the normal mode - SONiX TECHNOLOGY CO., LTD Page 54 Version 1.0 SN8P1927 SN8P1927 8-Bit Micro-Controller with Charge pump Regulator, PGIA, 16-bit ADC 5.3 WAKEUP 5.3.1 OVERVIEW Under power down mode (sleep mode) , program doesn't execute. The wakeup trigger can wake the system up to normal mode. The wakeup trigger sources are external trigger (P0, P1 level change) Power down mode is waked up to normal mode. The wakeup trigger is only external trigger (P0, P1 level change) 5.3.2 WAKEUP TIME When the system is in power down mode (sleep mode), the high clock oscillator stops. When waked up from power down mode, MCU waits for 2048 external high-speed oscillator clocks as the wakeup time to stable the oscillator circuit. After the wakeup time, the system goes into the normal mode. The value of the wakeup time is as the following. The Wakeup time = 1/Fosc * 2048 (sec) + high clock start-up time Note: The high clock start-up time is depended on the VDD and oscillator type of high clock. Example: In power down mode (sleep mode), the system is waked up. After the wakeup time, the system goes into normal mode. The wakeup time is as the following. The wakeup time = 1/Fosc * 2048 = 0.512 ms (Fosc = 4MHz) The total wakeup time = 0.512 ms + oscillator start-up time SONiX TECHNOLOGY CO., LTD Page 55 Version 1.0 SN8P1927 SN8P1927 8-Bit Micro-Controller with Charge pump Regulator, PGIA, 16-bit ADC 6 INTERRUPT 6.1 OVERVIEW This MCU provides three interrupt sources, including one internal interrupt (T0) and one external interrupt (INT0). The external interrupt can wakeup the chip while the system is switched from power down mode to high-speed normal mode. Once interrupt service is executed, the GIE bit in STKP register will clear to "0" for stopping other interrupt request. On the contrast, when interrupt service exits, the GIE bit will set to "1" to accept the next interrupts' request. All of the interrupt request signals are stored in INTRQ register. INTEN Interrupt Enable Register INTRQ INT0 Trigger P00IRQ P00IRQ 2-Bit T0 Time Out Latchs Interrupt Interrupt Vector Address (0008H 0008H) Enable T0IRQ Global Interrupt Request Signal Gating Note: The GIE bit must enable during all interrupt operation. 6.2 INTEN INTERRUPT ENABLE REGISTER INTEN is the interrupt request control register including one internal interrupts, one external interrupts enable control bits. One of the register to be set "1" is to enable the interrupt request function. Once of the interrupt occur, the stack is incremented and program jump to ORG 8 to execute interrupt service routines. The program exits the interrupt service routine when the returning interrupt service routine instruction (RETI) is executed. 0C9H INTEN Read/Write After reset Bit 7 - Bit 6 - Bit 5 - Bit 4 T0IEN R/W 0 Bit 0 Bit 2 - Bit 1 - Bit 0 P00IEN P00IEN R/W 0 P00IEN P00IEN: External P0.0 interrupt (INT0) control bit. 0 = Disable INT0 interrupt function. 1 = Enable INT0 interrupt function. Bit 4 Bit 3 - T0IEN: T0 timer interrupt control bit. 0 = Disable T0 interrupt function. 1 = Enable T0 interrupt function. SONiX TECHNOLOGY CO., LTD Page 56 Version 1.0 SN8P1927 SN8P1927 8-Bit Micro-Controller with Charge pump Regulator, PGIA, 16-bit ADC 6.3 INTRQ INTERRUPT REQUEST REGISTER INTRQ is the interrupt request flag register. The register includes all interrupt request indication flags. Each one of the interrupt requests occurs, the bit of the INTRQ register would be set "1". The INTRQ value needs to be clear by programming after detecting the flag. In the interrupt vector of program, users know the any interrupt requests occurring by the register and do the routine corresponding of the interrupt request. 0C8H INTRQ Read/Write After reset Bit 7 - Bit 6 - Bit 5 - Bit 4 T0IRQ R/W 0 Bit 0 Bit 2 - Bit 1 - Bit 0 P00IRQ P00IRQ R/W 0 P00IRQ P00IRQ: External P0.0 interrupt (INT0) request flag. 0 = None INT0 interrupt request. 1 = INT0 interrupt request. Bit 4 Bit 3 - T0IRQ: T0 timer interrupt request flag. 0 = None T0 interrupt request. 1 = T0 interrupt request. 6.4 GIE GLOBAL INTERRUPT OPERATION GIE is the global interrupt control bit. All interrupts start work after the GIE = 1 It is necessary for interrupt service request. One of the interrupt requests occurs, and the program counter (PC) points to the interrupt vector (ORG 8) and the stack add 1 level. 0DFH STKP Read/Write After reset Bit 7 Bit 7 GIE R/W 0 Bit 6 - Bit 5 - Bit 4 - Bit 3 - Bit 2 STKPB2 R/W 1 Bit 1 STKPB1 R/W 1 Bit 0 STKPB0 R/W 1 GIE: Global interrupt control bit. 0 = Disable global interrupt. 1 = Enable global interrupt. Example: Set global interrupt control bit (GIE). B0BSET FGIE ; Enable GIE Note: The GIE bit must enable during all interrupt operation. SONiX TECHNOLOGY CO., LTD Page 57 Version 1.0 SN8P1927 SN8P1927 8-Bit Micro-Controller with Charge pump Regulator, PGIA, 16-bit ADC 6.5 PUSH, POP ROUTINE When any interrupt occurs, system will jump to ORG 8 and execute interrupt service routine. It is necessary to save ACC, PFLAG data. The chip doesn't have any special instructions to process ACC, PFLAG registers when into interrupt service routine. Users have to save ACC, PFLAG by program, Using "B0XCH" to save/load ACC buffer, "B0MOV" to save/load PFLAG and avoid main routine error after interrupt service routine finishing. Note: To save/load ACC data, users must be "B0XCH" instruction, or else the PFLAG register might be modified by ACC operation. Example: Store ACC and PAFLG data by program when interrupt service routine executed. .DATA ACCBUF DS 1 PFLAGBUF DS 1 ; ACCBUF is ACC data buffer. ; PFLAGBUF is PFLAG data buffer. .CODE ORG JMP 0 START ORG JMP 8 INT_SERVICE ORG 10H START: . INT_SERVICE: B0XCH B0MOV B0MOV . . B0MOV B0MOV B0XCH A, ACCBUF A, PFLAG PFLAGBUF, A ; Save PFLAG to PFLAGBUF buffer. A, PFLAGBUF PFLAG, A A, ACCBUF ; Load PFLAG from PFLAGBUF buffer. ; Load ACC from ACCBUF buffer. RETI . ENDP SONiX TECHNOLOGY CO., LTD ; Save ACC to ACCBUF buffer. ; Exit interrupt service vector Page 58 Version 1.0 SN8P1927 SN8P1927 8-Bit Micro-Controller with Charge pump Regulator, PGIA, 16-bit ADC 6.6 INT0 (P0.0) INTERRUPT OPERATION When the INT0 trigger occurs, the P00IRQ P00IRQ will be set to "1" no matter the P00IEN P00IEN is enable or disable. If the P00IEN P00IEN = 1 and the trigger event P00IRQ P00IRQ is also set to be "1". As the result, the system will execute the interrupt vector (ORG 8). If the P00IEN P00IEN = 0 and the trigger event P00IRQ P00IRQ is still set to be "1". Moreover, the system won't execute interrupt vector even when the P00IRQ P00IRQ is set to be "1". Users need to be cautious with the operation under multi-interrupt situation. Note: The interrupt trigger direction of P0.0 is control by PEDGE register. 0BFH PEDGE Bit 7 PEDGEN R/W Bit 6 - Bit 5 - Bit 4 P00G1 P00G1 R/W Bit 3 P00G0 P00G0 R/W Bit 2 - Bit 1 - Bit7 PEDGEN: Interrupt and wakeup trigger edge control bit. 0 = Disable edge trigger function. Port 0: Low-level wakeup trigger and falling edge interrupt trigger. Port 1: Low-level wakeup trigger. 1 = Enable edge trigger function. P0.0: Both Wakeup and interrupt trigger are controlled by P00G1 P00G1 and P00G0 P00G0 bits. Port 1: Wakeup trigger is Level change (falling or rising edge). Bit[4:3] Bit 0 - P00G[1:0]: Port 0.0 edge select bits. 00 = reserved, 01 = falling edge 10 = rising edge, 11 = rising/falling bi-direction. Example: Setup INT0 interrupt request and bi-direction edge trigger. MOV B0MOV A, #98H PEDGE, A ; Set INT0 interrupt trigger as bi-direction edge. B0BSET B0BCLR B0BSET FP00IEN FP00IEN FP00IRQ FP00IRQ FGIE ; Enable INT0 interrupt service ; Clear INT0 interrupt request flag ; Enable GIE Example: INT0 interrupt service routine. ORG JMP 8 INT_SERVICE ; Interrupt vector INT_SERVICE: . ; Push routine to save ACC and PFLAG to buffers. B0BTS1 JMP FP00IRQ FP00IRQ EXIT_INT ; Check P00IRQ P00IRQ ; P00IRQ P00IRQ = 0, exit interrupt vector B0BCLR . . FP00IRQ FP00IRQ ; Reset P00IRQ P00IRQ ; INT0 interrupt service routine EXIT_INT: . ; Pop routine to load ACC and PFLAG from buffers. RETI ; Exit interrupt vector SONiX TECHNOLOGY CO., LTD Page 59 Version 1.0 SN8P1927 SN8P1927 8-Bit Micro-Controller with Charge pump Regulator, PGIA, 16-bit ADC 6.7 T0 INTERRUPT OPERATION When the T0C counter occurs overflow, the T0IRQ will be set to "1" however the T0IEN is enable or disable. If the T0IEN = 1, the trigger event will make the T0IRQ to be "1" and the system enter interrupt vector. If the T0IEN = 0, the trigger event will make the T0IRQ to be "1" but the system will not enter interrupt vector. Users need to care for the operation under multi-interrupt situation. Example: T0 interrupt request setup. B0BCLR B0BCLR MOV B0MOV MOV B0MOV