SN54LVT125 SN74LVT125 SCBS133D MIL-STD-883C JESD-17 LVT125 SCBD002B - Datasheet Archive

 

3.3-V ABT QUADRUPLE BUS BUFFERS WITH 3-STATE OUTPUTS SCBS133D ­ MAY 1992 ­ REVISED JULY 1995 D D D D D D 1OE 1A 1Y 2OE 2A

 

SN54LVT125 SN54LVT125, SN74LVT125 SN74LVT125 3.3-V ABT QUADRUPLE BUS BUFFERS WITH 3-STATE OUTPUTS SCBS133D SCBS133D ­ MAY 1992 ­ REVISED JULY 1995 D D D D D D 1OE 1A 1Y 2OE 2A 2Y GND 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4OE 4A 4Y 3OE 3A 3Y SN54LVT125 SN54LVT125 . . . FK PACKAGE (TOP VIEW) 1A 1OE NC VCC 4OE D SN54LVT125 SN54LVT125 . . . J PACKAGE SN74LVT125 SN74LVT125 . . . D, DB, OR PW PACKAGE (TOP VIEW) 1Y NC 2OE NC 2A 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 4A NC 4Y NC 3OE GND NC 3Y 3A D State-of-the-Art Advanced BiCMOS Technology (ABT) Design for 3.3-V Operation and Low-Static Power Dissipation Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC ) Support Unregulated Battery Operation Down to 2.7 V Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C ESD Protection Exceeds 2000 V Per MIL-STD-883C MIL-STD-883C, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 JESD-17 Bus-Hold Data Inputs Eliminate the Need for External Pullup Resistors Support Live Insertion Package Options Include Plastic Small-Outline (D), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW) Packages, Ceramic Chip Carriers (FK), and Ceramic (J) DIPs 2Y D NC ­ No internal connection description These bus buffers are designed specifically for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment. The LVT125 LVT125 feature independent line drivers with 3-state outputs. Each output is in the high-impedance state when the associated output-enable (OE) input is high. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN74LVT125 SN74LVT125 is available in TI's shrink small-outline package (DB), which provides the same I/O pin count and functionality of standard small-outline packages in less than half the printed-circuit-board area. The SN54LVT125 SN54LVT125 is characterized for operation over the full military temperature range of ­ 55°C to 125°C. The SN74LVT125 SN74LVT125 is characterized for operation from ­ 40°C to 85°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright © 1995, Texas Instruments Incorporated UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 1 SN54LVT125 SN54LVT125, SN74LVT125 SN74LVT125 3.3-V ABT QUADRUPLE BUS BUFFERS WITH 3-STATE OUTPUTS SCBS133D SCBS133D ­ MAY 1992 ­ REVISED JULY 1995 FUNCTION TABLE (each buffer) INPUTS OE A OUTPUT Y L H H L L L H X Z logic symbol 1OE 1A 2OE 2A 3OE 3A 4OE 4A 1 2 4 5 logic diagram (positive logic) EN 1 3 6 1Y 1A 9 13 12 11 1 2 3 1Y 2Y 10 8 1OE 2OE 4 3Y 2A 5 6 2Y 4Y 3OE This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. 3A 4OE 4A 10 9 8 3Y 13 12 11 4Y Pin numbers shown are for the D, DB, J, and PW packages. absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ­ 0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ­ 0.5 V to 7 V Voltage range applied to any output in the high state or power-off state, VO (see Note 1) . . . . ­ 0.5 V to 7 V Current into any output in the low state, IO: SN54LVT125 SN54LVT125 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA SN74LVT125 SN74LVT125 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Current into any output in the high state, IO (see Note 2): SN54LVT125 SN54LVT125 . . . . . . . . . . . . . . . . . . . . . . . . . 48 mA SN74LVT125 SN74LVT125 . . . . . . . . . . . . . . . . . . . . . . . . . 64 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ­ 50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ­ 50 mA Maximum power dissipation at TA = 55°C (in still air) (see Note 3): D package . . . . . . . . . . . . . . . . . . . . 1.25 W DB or PW package . . . . . . . . . . . . . 0.5 W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ­ 65°C to 150°C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This current flows only when the output is in the high state and VO > VCC. 3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils. For more information, refer to the Package Thermal Considerations application note in the 1994 ABT Advanced BiCMOS Technology Data Book, literature number SCBD002B SCBD002B. 2 POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 SN54LVT125 SN54LVT125, SN74LVT125 SN74LVT125 3.3-V ABT QUADRUPLE BUS BUFFERS WITH 3-STATE OUTPUTS SCBS133D SCBS133D ­ MAY 1992 ­ REVISED JULY 1995 recommended operating conditions (see Note 4) SN54LVT125 SN54LVT125 SN74LVT125 SN74LVT125 MIN MAX MIN MAX 2.7 3.6 2.7 3.6 UNIT VCC VIH Supply voltage VIL VI Low-level input voltage 0.8 0.8 Input voltage 5.5 5.5 V IOH IOL High-level output current ­ 24 ­ 32 mA 48 64 mA t /v Input transition rise or fall rate 10 10 ns / V 85 °C High-level input voltage 2 Low-level output current Outputs enabled TA Operating free-air temperature NOTE 4: Unused control inputs must be held high or low to prevent them from floating. ­ 55 2 125 ­ 40 V V V electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOH SN54LVT125 SN54LVT125 TYP MAX TEST CONDITIONS VCC = 2.7 V, VCC = MIN to MAX, II = ­18 mA IOH = ­100 µA VCC = 2.7 V, MIN IOH = ­ 8 mA IOH = ­ 24 mA VCC = 3 V VCC = 2 7 V 2.7 VOL VCC = 3 V ­1.2 VCC ­ 0.2 2.4 ­1.2 VCC ­ 0.2 2.4 IOH = ­ 32 mA IOL = 100 µA 0.2 0.2 0.5 0.5 0.4 0.4 IOL = 32 mA IOL = 48 mA 0.5 0.5 VCC = 3.6 V VI = VCC or GND VI = VCC Ioff VCC = 0, VI = 0 VI or VO = 0 to 4.5 V II(hold) I(h ld) VCC = 3 V VI = 0.8 V VI = 2 V IOZH IOZL VCC = 3.6 V, VCC = 3.6 V, 0.55 10 ±1 1 Data inputs 10 ±1 Control inputs 1 ­5 Data inputs 75 75 ­75 ­75 µA µA 5 ­5 µA ­5 5 µA 0.12 0.19 0.12 0.19 Outputs low 4.5 7 4.5 7 0.12 0.19 0.12 0.19 Outputs disabled ICC§ VCC = 3 V to 3.6 V, One input at VCC ­ 0.6 V, Other inputs at VCC or GND Ci VI = 3 V or 0 VO = 3 V or 0 Co µA ­5 ± 100 Outputs high IO = 0, V 0.55 VO = 3 V VO = 0.5 V VCC = 3.6 V, VI = VCC or GND V 2 IOL = 24 mA IOL = 16 mA VCC = 0 or MAX, ICC UNIT V 2 IOL = 64 mA VI = 5.5 V II SN74LVT125 SN74LVT125 TYP MAX MIN 0.3 0.2 mA mA 4 4 pF 8 8 pF All typical values are at VCC = 3.3 V, TA = 25°C. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. § This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 3 SN54LVT125 SN54LVT125, SN74LVT125 SN74LVT125 3.3-V ABT QUADRUPLE BUS BUFFERS WITH 3-STATE OUTPUTS SCBS133D SCBS133D ­ MAY 1992 ­ REVISED JULY 1995 switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) SN54LVT125 SN54LVT125 PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 3.3 V ± 0.3 V SN74LVT125 SN74LVT125 VCC = 2.7 V A tPZH tPZL OE tPHZ tPLZ OE 4.7 1 2.7 4 4.5 4.1 5.1 1 2.9 3.9 4.9 1 4.9 6.2 1 3.4 4.7 6 1.1 4.9 6.7 1.1 3.4 4.7 6.5 1.8 5.3 5.9 1.8 3.7 5.1 5.7 1.3 Y 4.2 1 Y MAX 1 Y MAX VCC = 2.7 V MIN tPLH tPHL MIN VCC = 3.3 V ± 0.3 V MIN TYP MAX 4.7 4.2 1.3 2.6 4.5 4 All typical values are at VCC = 3.3 V, TA = 25°C. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 4 POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 MIN UNIT MAX ns ns ns SN54LVT125 SN54LVT125, SN74LVT125 SN74LVT125 3.3-V ABT QUADRUPLE BUS BUFFERS WITH 3-STATE OUTPUTS SCBS133D SCBS133D ­ MAY 1992 ­ REVISED JULY 1995 PARAMETER MEASUREMENT INFORMATION 6V S1 500 From Output Under Test TEST Open GND CL = 50 pF (see Note A) S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 6V GND 500 2.7 V LOAD CIRCUIT FOR OUTPUTS 1.5 V Timing Input 0V tw tsu 2.7 V Input 1.5 V th 2.7 V 1.5 V 1.5 V Data Input 1.5 V 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 2.7 V Input 1.5 V 0V 1.5 V 1.5 V VOL tPLH tPHL VOH Output 1.5 V 1.5 V VOL 1.5 V 0V tPLZ Output Waveform 1 S1 at 6 V (see Note B) VOH Output 1.5 V tPZL tPHL tPLH 2.7 V Output Control 1.5 V Output Waveform 2 S1 at GND (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 1.5 V tPZH 3V VOL + 0.3 V VOL tPHZ 1.5 V VOH ­ 0.3 V VOH [0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2.5 ns, tf 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 5 SN54LVT125 SN54LVT125, SN74LVT125 SN74LVT125 3.3-V ABT QUADRUPLE BUS BUFFERS WITH 3-STATE OUTPUTS SCBS133D SCBS133D ­ MAY 1992 ­ REVISED JULY 1995 6 POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. 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