SN74LVCZ32240A 32BIT SCES421 A114-A SN74LVCZ32240AGKER ZC240A SCBA004 - Datasheet Archive

 

32BIT BUFFER/DRIVER WITH 3STATE OUTPUTS SCES421 ­ JANUARY 2003 D Member of the Texas Instruments D D D D D Supports

 

SN74LVCZ32240A SN74LVCZ32240A 32BIT 32BIT BUFFER/DRIVER WITH 3STATE OUTPUTS SCES421 SCES421 ­ JANUARY 2003 D Member of the Texas Instruments D D D D D Supports Mixed-Mode Signal Operation on Widebus+ Family Operates From 2.7 V to 3.6 V Inputs Accept Voltages to 5.5 V Max tpd of 4.2 ns at 3.3 V Ioff and Power-Up 3-State Support Hot Insertion GKE PACKAGE (TOP VIEW) 1 2 3 4 5 All Ports (5-V Input/Output Voltage With 3.3-V VCC) Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 ­ 2000-V Human-Body Model (A114-A A114-A) ­ 1000-V Charged-Device Model (C101) D D terminal assignments 6 1 2 3 4 5 6 A A 1Y2 1Y1 1OE 2OE 1A1 1A2 B B 1Y4 1Y3 GND GND 1A3 1A4 C C 2Y2 2Y1 2A2 D 2Y2 2Y3 1VCC GND 2A1 D 1VCC GND 2A3 2A4 E 3Y2 3Y1 GND GND 3A1 3A2 F 3Y4 3Y3 3A4 4Y2 4Y1 1VCC GND 3A3 G 1VCC GND 4A1 4A2 H 4Y3 4Y4 4OE 3OE 4A4 4A3 J 5Y2 5Y1 5OE 6OE 5A1 5A2 E F G H J K 5Y4 5Y3 GND GND 5A3 5A4 K L 6Y2 6Y1 6A2 M 6Y4 6Y3 2VCC GND 6A1 L 2VCC GND 6A3 6A4 M N 7Y2 7Y1 GND GND 7A1 7A2 N P 7Y4 7Y3 7A4 R 8Y2 8Y1 2VCC GND 7A3 P 2VCC GND 8A1 8A2 R T 8Y3 8Y4 8OE 7OE 8A4 8A3 T description/ordering information This 32-bit buffer/driver is designed for 2.7-V to 3.6-V VCC operation. The SN74LVCZ32240A SN74LVCZ32240A is designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The device can be used as eight 4-bit buffers, four 8-bit buffers, two 16-bit buffers, or one 32-bit buffer. This device provides inverting outputs. ORDERING INFORMATION TA PACKAGE ORDERABLE PART NUMBER TOP-SIDE MARKING ­40°C to 85°C LFBGA ­ GKE Tape and reel SN74LVCZ32240AGKER SN74LVCZ32240AGKER ZC240A ZC240A Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus+ is a trademark of Texas Instruments. Copyright 2003, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 1 SN74LVCZ32240A SN74LVCZ32240A 32BIT 32BIT BUFFER/DRIVER WITH 3STATE OUTPUTS SCES421 SCES421 ­ JANUARY 2003 description/ordering information (continued) Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment. During power up or power down, when VCC is between 0 and 1.5 V, the device is in the high-impedance state. However, to ensure the high-impedance state above 1.5 V, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. This device is fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down (VCC = 0 V). The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. FUNCTION TABLE (each 4-bit buffer) INPUTS OE OUTPUT Y L H L L L H H 2 A X Z POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 SN74LVCZ32240A SN74LVCZ32240A 32BIT 32BIT BUFFER/DRIVER WITH 3STATE OUTPUTS SCES421 SCES421 ­ JANUARY 2003 logic diagram (positive logic) 1OE 1A1 1A2 1A3 1A4 2OE 2A1 2A2 2A3 2A4 5OE 5A1 5A2 5A3 5A4 6OE 6A1 6A2 6A3 6A4 A3 3OE A5 A2 A6 A1 B5 B2 B6 B1 1Y1 3A1 1Y2 3A2 1Y3 3A3 1Y4 3A4 A4 4OE C5 C2 C6 C1 D5 D2 D6 D1 2Y1 4A1 2Y2 4A2 2Y3 4A3 2Y4 4A4 J3 7OE J5 J2 J6 J1 K5 K2 K6 K1 5Y1 7A1 5Y2 7A2 5Y3 7A3 5Y4 7A4 J4 8OE L5 L2 L6 L1 M5 M2 M6 M1 6Y1 8A1 6Y2 8A2 6Y3 8A3 6Y4 8A4 POST OFFICE BOX 655303 H4 E5 E2 E6 E1 F5 F2 F6 F1 3Y1 3Y2 3Y3 3Y4 H3 G5 G2 G6 G1 H6 H1 H5 H2 4Y1 4Y2 4Y3 4Y4 T4 N5 N2 N6 N1 P5 P2 P6 P1 7Y1 7Y2 7Y3 7Y4 T3 R5 R2 R6 R1 T6 T1 T5 T2 · DALLAS, TEXAS 75265 8Y1 8Y2 8Y3 8Y4 3 SN74LVCZ32240A SN74LVCZ32240A 32BIT 32BIT BUFFER/DRIVER WITH 3STATE OUTPUTS SCES421 SCES421 ­ JANUARY 2003 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ­0.5 V to 6.5 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ­0.5 V to 6.5 V Voltage range applied to any output in the high-impedance or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ­0.5 V to 6.5 V Voltage range applied to any output in the high or low state, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ­0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ­50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ­50 mA Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through each VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA Package thermal impedance, JA (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ­65°C to 150°C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The value of VCC is provided in the recommended operating conditions table. 3. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 4) MIN MAX 2.7 3.6 VCC VIH Supply voltage VIL VI Low-level input voltage VO Output voltage High-level output current High le el o tp t c rrent VCC = 2.7 V VCC = 3 V ­12 IOH Low-level output current Lo le el o tp t c rrent VCC = 2.7 V VCC = 3 V 12 IOL t/v Input transition rise or fall rate t/VCC TA Power-up ramp rate 150 Operating free-air temperature ­40 UNIT High-level input voltage VCC = 2.7 V to 3.6 V VCC = 2.7 V to 3.6 V 2 V V 0.8 V 0 5.5 V High or low state 0 3-state 0 VCC 5.5 V Input voltage ­24 24 10 mA mA ns/V µs/V 85 °C NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004 SCBA004. 4 POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 SN74LVCZ32240A SN74LVCZ32240A 32BIT 32BIT BUFFER/DRIVER WITH 3STATE OUTPUTS SCES421 SCES421 ­ JANUARY 2003 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN 2.7 V to 3.6 V IOH = ­100 µA VCC­0.2 2.2 2.7 V VOH TYP VCC IOH = ­12 mA 12 3V UNIT V 2.4 3V IOH = ­24 mA IOL = 100 µA MAX 2.2 2.7 V to 3.6 V 0.2 IOL = 12 mA IOL = 24 mA 2.7 V 0.4 3V 0.55 II Ioff VI = 0 to 5.5 V VI or VO = 5.5 V 3.6 V ±5 µA 0 ±5 µA IOZ VO = 0 to 5.5 V 3.6 V ±5 µA IOZPU VO = 0.5 V to 2.5 V, OE = don't care 0 to 1.5 V ±5 µA IOZPD VO = 0.5 V to 2.5 V, OE = don't care 1.5 V to 0 ±5 µA ICC VI = VCC or GND 3.6 V VI 5.5 V IO = 0 VOL ICC Ci 200 36V 3.6 One input at VCC ­ 0.6 V, Other inputs at VCC or GND 2.7 V to 3.6 V VI = VCC or GND VO = VCC or GND Co 200 100 V A µA µA 3.3 V 4.5 pF 3.3 V 6 pF All typical values are at VCC = 3.3 V, TA = 25°C. This applies in the disabled state only. switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) FROM (INPUT) TO (OUTPUT) tpd A ten tdis PARAMETER VCC = 2.7 V VCC = 3.3 V ± 0.3 V UNIT MIN MAX MIN MAX Y 1 4.5 1 4.2 ns OE Y 1.5 5 1.5 4.7 ns OE Y 1.5 6.2 1.5 5.9 ns switching characteristics over recommended operating free-air temperature range, CL = 30 pF (unless otherwise noted) (see Figure 1) FROM (INPUT) TO (OUTPUT) tpd A Y ten OE tdis OE PARAMETER POST OFFICE BOX 655303 VCC = 2.7 V VCC = 3.3 V ± 0.3 V UNIT MIN MAX MIN MAX 1 4.4 1 4.1 ns Y 1 4.8 1 4.5 ns Y 1.4 5.9 1.4 5.6 ns · DALLAS, TEXAS 75265 5 SN74LVCZ32240A SN74LVCZ32240A 32BIT 32BIT BUFFER/DRIVER WITH 3STATE OUTPUTS SCES421 SCES421 ­ JANUARY 2003 operating characteristics, TA = 25°C TEST CONDITIONS PARAMETER Cpd d 6 Outputs enabled Power Po er dissipation capacitance per buffer/driver b ffer/dri er POST OFFICE BOX 655303 Outputs disabled · DALLAS, TEXAS 75265 VCC = 3.3 V TYP UNIT 31 f = 10 MHz MH 3.5 pF SN74LVCZ32240A SN74LVCZ32240A 32BIT 32BIT BUFFER/DRIVER WITH 3STATE OUTPUTS SCES421 SCES421 ­ JANUARY 2003 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V ± 0.3 V 2 × VCC S1 500 From Output Under Test Open TEST CL = 30 pF or 50 pF (see Note A) 500 S1 tpd tPLZ/tPZL tPHZ/tPZH GND Open 2 × VCC GND LOAD CIRCUIT tw VCC Timing Input VCC/2 VCC/2 VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC/2 VCC/2 0V tPLH Output Control (low-level enabling) tPLZ VCC VCC/2 tPZH VOH VCC/2 VOL VCC/2 0V Output Waveform 1 S1 at 2 × VCC (see Note B) tPHL VCC/2 VCC VCC/2 tPZL VCC Input VOLTAGE WAVEFORMS PULSE DURATION th VCC Data Input VCC/2 0V 0V tsu Output VCC VCC/2 Input Output Waveform 2 S1 at GND (see Note B) VOL + 0.3 V VOL tPHZ VCC/2 VOH VOH ­ 0.3 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2 ns, tf 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 7 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. 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