SN54LVC540A SN74LVC540A SCAS297M A114-A SN74LVC540ADW SN74LVC540ADWR - Datasheet Archive

 

OCTAL BUFFERS/DRIVERS WITH 3STATE OUTPUTS SCAS297M - JANUARY 1993 - REVISED AUGUST 2003 D D D D OE1 A1 A2 A3 A4 A5 A6 A7 A8 GND 1

 

SN54LVC540A SN54LVC540A, SN74LVC540A SN74LVC540A OCTAL BUFFERS/DRIVERS WITH 3STATE OUTPUTS SCAS297M SCAS297M - JANUARY 1993 - REVISED AUGUST 2003 D D D D OE1 A1 A2 A3 A4 A5 A6 A7 A8 GND 1 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 VCC OE2 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 20 2 11 SN54LVC540A SN54LVC540A . . . FK PACKAGE (TOP VIEW) description/ordering information 4 3 2 1 20 19 18 5 17 6 16 7 15 8 A3 A4 A5 A6 A7 The SN54LVC540A SN54LVC540A octal buffer/driver is designed for 2.7-V to 3.6-V VCC operation, and the SN74LVC540A SN74LVC540A octal buffer/driver is designed for 1.65-V to 3.6-V VCC operation. OE2 D SN54LVC540A SN54LVC540A . . . J OR W PACKAGE SN74LVC540A SN74LVC540A . . . DB, DGV, DW, NS, OR PW PACKAGE (TOP VIEW) Operate From 1.65 V to 3.6 V Inputs Accept Voltages to 5.5 V Max tpd of 5.3 ns at 3.3 V Typical VOLP (Output Ground Bounce) 2 V at VCC = 3.3 V, TA = 25°C Support Mixed-Mode Signal Operation on All Ports (5-V Input/Output Voltage With 3.3-V VCC) Ioff Supports Partial-Power-Down Mode Operation Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds JESD 22 - 2000-V Human-Body Model (A114-A A114-A) - 1000-V Charged-Device Model (C101) A2 A1 OE1 VCC D D D D 14 9 10 11 12 13 A8 GND Y8 Y7 Y6 These devices are ideal for driving bus lines or buffer memory address registers. These devices feature inputs and outputs on opposite sides of the package that facilitate printed circuit board layout. Y1 Y2 Y3 Y4 Y5 ORDERING INFORMATION ORDERABLE PART NUMBER PACKAGE TA TOP-SIDE MARKING Tube of 25 SN74LVC540ADW SN74LVC540ADW Reel of 2000 SN74LVC540ADWR SN74LVC540ADWR SOP - NS Reel of 2000 SN74LVC540ANSR SN74LVC540ANSR LVC540A LVC540A SSOP - DB Reel of 2000 SN74LVC540ADBR SN74LVC540ADBR LC540A LC540A Tube of 70 SN74LVC540APW SN74LVC540APW Reel of 2000 SN74LVC540APWR SN74LVC540APWR Reel of 250 SN74LVC540APWT SN74LVC540APWT TVSOP - DGV Reel of 2000 SN74LVC540ADGVR SN74LVC540ADGVR LC540A LC540A CDIP - J Tube of 20 SNJ54LVC540AJ SNJ54LVC540AJ SNJ54LVC540AJ SNJ54LVC540AJ CFP - W Tube of 85 SNJ54LVC540AW SNJ54LVC540AW SNJ54LVC540AW SNJ54LVC540AW LCCC - FK Tube of 55 SNJ54LVC540AFK SNJ54LVC540AFK SOIC - DW -40°C to 85°C TSSOP - PW -55 C 125°C -55°C to 125 C LVC540A LVC540A LC540A LC540A SNJ54LVC540AFK SNJ54LVC540AFK Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2003, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. On products compliant to MILPRF38535 MILPRF38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 1 SN54LVC540A SN54LVC540A, SN74LVC540A SN74LVC540A OCTAL BUFFERS/DRIVERS WITH 3STATE OUTPUTS SCAS297M SCAS297M - JANUARY 1993 - REVISED AUGUST 2003 description/ordering information (continued) The 3-state control gate is a 2-input AND gate with active-low inputs so that, if either output-enable (OE1 or OE2) input is high, all outputs are in the high-impedance state. Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment. These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. FUNCTION TABLE INPUTS OE1 OE2 A OUTPUT Y L L L H L L H L H X X Z X H X Z logic diagram (positive logic) OE1 OE2 A1 1 19 2 18 To Seven Other Channels 2 POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 Y1 SN54LVC540A SN54LVC540A, SN74LVC540A SN74LVC540A OCTAL BUFFERS/DRIVERS WITH 3STATE OUTPUTS SCAS297M SCAS297M - JANUARY 1993 - REVISED AUGUST 2003 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 6.5 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 6.5 V Voltage range applied to any output in the high-impedance or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 6.5 V Voltage range applied to any output in the high or low state, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA Package thermal impedance, JA (see Note 3): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92°C/W DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to 150°C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The value of VCC is provided in the recommended operating conditions table. 3. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 4) SN54LVC540A SN54LVC540A SN74LVC540A SN74LVC540A MIN MAX MIN MAX 2 3.6 1.65 3.6 Operating VCC VIH Supply voltage High-level input voltage Data retention only 1.5 Low-level input voltage VI VO Output voltage 0.65 × VCC 1.7 2 V 2 0.35 × VCC VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V Input voltage V 1.5 VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VCC = 1.65 V to 1.95 V VIL UNIT 0.7 0.8 V 0.8 IOL High-level output current Low-level output current 5.5 0 5.5 V High or low state IOH 0 0 0 VCC 5.5 0 3-state VCC 5.5 V VCC = 1.65 V VCC = 2.3 V VCC = 2.7 V VCC = 3 V -4 -8 -12 -12 -24 mA -24 VCC = 1.65 V VCC = 2.3 V VCC = 2.7 V VCC = 3 V 0 4 8 12 12 24 mA 24 TA Operating free-air temperature -55 125 -40 85 °C NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004 SCBA004. POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 3 SN54LVC540A SN54LVC540A, SN74LVC540A SN74LVC540A OCTAL BUFFERS/DRIVERS WITH 3STATE OUTPUTS SCAS297M SCAS297M - JANUARY 1993 - REVISED AUGUST 2003 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS 2.7 V to 3.6 V IOH = -4 mA IOH = -8 mA SN74LVC540A SN74LVC540A TYP MAX MIN 1.65 V to 3.6 V IOH = -100 µA A VOH SN54LVC540A SN54LVC540A TYP MAX VCC MIN VCC-0.2 VCC-0.2 1.65 V 1.2 2.3 V 1.7 2.7 V 2.4 2.4 2.2 V 2.2 3V IOH = -24 mA 2.2 3V IOH = -12 mA 2.2 1.65 V to 3.6 V IOL = 100 µA A UNIT 0.2 2.7 V to 3.6 V 0.2 IOL = 4 mA IOL = 8 mA 1.65 V 0.45 2.3 V 0.7 IOL = 12 mA IOL = 24 mA 2.7 V 0.4 0.4 3V 0.55 0.55 II VI = 0 to 5.5 V 3.6 V ±5 ±5 µA Ioff VI or VO = 5.5 V ±10 µA IOZ VO = 0 to 5.5 V ±15 ±10 µA 10 10 ICC VI = VCC or GND 3.6 V VI 5.5 V 10 10 ICC One input at VCC - 0.6 V, Other inputs at VCC or GND 500 500 Ci VI = VCC or GND VOL 0 3.6 V IO = 0 3.6 V 2.7 V to 3.6 V V µA A µA 3.3 V Co VO = VCC or GND All typical values are at VCC = 3.3 V, TA = 25°C. This applies in the disabled state only. 4 4 pF 3.3 V 5.5 5.5 pF switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) SN54LVC540A SN54LVC540A PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 2.7 V MIN UNIT A ten OE tdis OE POST OFFICE BOX 655303 MAX MIN MAX Y tpd 4 VCC = 3.3 V ± 0.3 V 7.1 1 5.3 ns Y 8 1 6.6 ns Y 8.2 1 7.4 ns · DALLAS, TEXAS 75265 SN54LVC540A SN54LVC540A, SN74LVC540A SN74LVC540A OCTAL BUFFERS/DRIVERS WITH 3STATE OUTPUTS SCAS297M SCAS297M - JANUARY 1993 - REVISED AUGUST 2003 switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) SN74LVC540A SN74LVC540A PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 1.8 V ± 0.15 V VCC = 2.5 V ± 0.2 V MIN A ten OE tdis OE MIN Y 1 16.4 Y 1 16.5 Y 1 15.9 VCC = 3.3 V ± 0.3 V UNIT MAX MIN MAX MIN MAX 1 7.8 1 7.1 1.4 5.3 ns 1 10.5 1 8 1.1 6.6 ns 1 9 1 8.2 1.8 7.4 ns 1 tpd MAX VCC = 2.7 V ns tsk(o) operating characteristics, TA = 25°C TEST CONDITIONS PARAMETER Cpd Power dissipation capacitance per buffer/driver Outputs enabled Outputs disabled VCC = 1.8 V TYP VCC = 2.5 V TYP VCC = 3.3 V TYP 63 f = 10 MHz POST OFFICE BOX 655303 56 31 3 3 3 UNIT · DALLAS, TEXAS 75265 pF 5 SN54LVC540A SN54LVC540A, SN74LVC540A SN74LVC540A OCTAL BUFFERS/DRIVERS WITH 3STATE OUTPUTS SCAS297M SCAS297M - JANUARY 1993 - REVISED AUGUST 2003 PARAMETER MEASUREMENT INFORMATION RL From Output Under Test CL (see Note A) VLOAD Open S1 TEST RL S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH GND Open VLOAD GND LOAD CIRCUIT INPUTS VCC 1.8 V ± 0.15 V 2.5 V ± 0.2 V 2.7 V 3.3 V ± 0.3 V VM VI tr/tf VCC VCC 2.7 V 2.7 V 2 ns 2 ns 2.5 ns 2.5 ns VLOAD CL RL V VCC/2 VCC/2 1.5 V 1.5 V 2 × VCC 2 × VCC 6V 6V 30 pF 30 pF 50 pF 50 pF 1 k 500 500 500 0.15 V 0.15 V 0.3 V 0.3 V VI Timing Input VM 0V tw tsu VI Input VM VM th VI Data Input VM VM 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VI VM Input VM 0V tPLH tPHL VOH VM Output VM VOL tPHL Output Waveform 1 S1 at VLOAD (see Note B) tPLH VM VM VM 0V tPLZ tPZL VLOAD/2 VM VM VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Output Waveform 2 S1 at GND (see Note B) VOL + V VOL tPHZ tPZH VOH Output VI Output Control VM VOH - V VOH 0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 . D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms 6 POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 MECHANICAL DATA MCFP006B MCFP006B - JANUARY 1995 - REVISED JULY 2003 W (R-GDFP-F20 R-GDFP-F20) CERAMIC DUAL FLATPACK Base and Seating Plane 0.300 (7,62) 0.245 (6,22) 0.045 (1,14) 0.026 (0,66) 0.009 (0,23) 0.004 (0,10) 0.100 (2,54) 0.045 (1,14) 0.320 (8,13) MAX 1 0.022 (0,56) 0.015 (0,38) 20 0.050 (1,27) 0.540 (13,72) MAX 0.005 (0,13) MIN 4 Places 10 11 0.370 (9,40) 0.250 (6,35) 0.370 (9,40) 0.250 (6,35) 4040180-4 /D 07/03 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a ceramic lid using glass frit. Index point is provided on cap for terminal identification only. Falls within Mil-Std 1835 GDFP2-F20 GDFP2-F20 POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 MECHANICAL DATA MLCC006B MLCC006B ­ OCTOBER 1996 FK (S-CQCC-N*) LEADLESS CERAMIC CHIP CARRIER 28 TERMINAL SHOWN 18 17 16 15 14 13 NO. OF TERMINALS * 12 A B 11 20 MAX MIN MAX 20 0.342 (8,69) 0.358 (9,09) 0.307 (7,80) 0.358 (9,09) 28 19 MIN 0.442 (11,23) 0.458 (11,63) 0.406 (10,31) 0.458 (11,63) 10 21 9 22 8 44 0.640 (16,26) 0.660 (16,76) 0.495 (12,58) 0.560 (14,22) 23 7 52 0.739 (18,78) 0.761 (19,32) 0.495 (12,58) 0.560 (14,22) 24 6 68 0.938 (23,83) 0.962 (24,43) 0.850 (21,6) 0.858 (21,8) 84 1.141 (28,99) 1.165 (29,59) 1.047 (26,6) 1.063 (27,0) B SQ A SQ 25 5 26 27 28 1 2 3 4 0.080 (2,03) 0.064 (1,63) 0.020 (0,51) 0.010 (0,25) 0.020 (0,51) 0.010 (0,25) 0.055 (1,40) 0.045 (1,14) 0.045 (1,14) 0.035 (0,89) 0.045 (1,14) 0.035 (0,89) 0.028 (0,71) 0.022 (0,54) 0.050 (1,27) 4040140 / D 10/96 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a metal lid. The terminals are gold plated. Falls within JEDEC MS-004 MS-004 POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 MECHANICAL DATA MPDS006C MPDS006C ­ FEBRUARY 1996 ­ REVISED AUGUST 2000 DGV (R-PDSO-G*) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,40 0,23 0,13 24 13 0,07 M 0,16 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 0°­8° 1 0,75 0,50 12 A Seating Plane 0,15 0,05 1,20 MAX PINS * 0,08 14 16 20 24 38 48 56 A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 DIM 4073251/E 4073251/E 08/00 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side. Falls within JEDEC: 24/48 Pins ­ MO-153 MO-153 14/16/20/56 Pins ­ MO-194 MO-194 POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 MECHANICAL DATA MSSO002E MSSO002E ­ JANUARY 1995 ­ REVISED DECEMBER 2001 DB (R-PDSO-G*) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°­8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS * 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-150 MO-150 POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 MECHANICAL DATA MTSS001C MTSS001C ­ JANUARY 1995 ­ REVISED FEBRUARY 1999 PW (R-PDSO-G*) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°­ 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS * 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153 MO-153 POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Applications Amplifiers amplifier.ti.com Audio www.ti.com/audio Data Converters dataconverter.ti.com Automotive www.ti.com/automotive DSP dsp.ti.com Broadband www.ti.com/broadband Interface interface.ti.com Digital Control www.ti.com/digitalcontrol Logic logic.ti.com Military www.ti.com/military Power Mgmt power.ti.com Optical Networking www.ti.com/opticalnetwork Microcontrollers microcontroller.ti.com Security www.ti.com/security Telephony www.ti.com/telephony Video & Imaging www.ti.com/video Wireless www.ti.com/wireless Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265 Copyright 2004, Texas Instruments Incorporated