SN74LVC2952A SCAS311H A114-A SN74LVC2952ADW SN74LVC2952ADWR SN74LVC2952ANSR - Datasheet Archive

 

OCTAL BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS SCAS311H ­ JANUARY 1993 ­ REVISED AUGUST 2002 D D D D D D D D D

 

SN74LVC2952A SN74LVC2952A OCTAL BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS SCAS311H SCAS311H ­ JANUARY 1993 ­ REVISED AUGUST 2002 D D D D D D D D D Operates From 1.65 V to 3.6 V Inputs Accept Voltages to 5.5 V Max tpd of 8.2 ns at 3.3 V Typical VOLP (Output Ground Bounce) 2 V at VCC = 3.3 V, TA = 25°C Supports Mixed-Mode Signal Operation on All Ports (5-V Input/Output Voltage With 3.3-V VCC) Ioff Supports Partial-Power-Down Mode Operation Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds JESD 22 ­ 2000-V Human-Body Model (A114-A A114-A) ­ 1000-V Charged-Device Model (C101) DB, DW, NS, OR PW PACKAGE (TOP VIEW) B8 B7 B6 B5 B4 B3 B2 B1 OEAB CLKAB CLKENAB GND 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 VCC A8 A7 A6 A5 A4 A3 A2 A1 OEBA CLKBA CLKENBA description/ordering information This octal bus transceiver and register is designed for 1.65-V to 3.6-V VCC operation. The SN74LVC2952A SN74LVC2952A consists of two 8-bit back-to-back registers that store data flowing in both directions between two bidirectional buses. Data on the A or B bus is stored in the registers on the low-to-high transition of the clock (CLKAB or CLKBA) input, provided that the clock-enable (CLKENAB or CLKENBA) input is low. Taking the output-enable (OEAB or OEBA) input low accesses the data on either port. Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. ORDERING INFORMATION PACKAGE ORDERABLE PART NUMBER Tube SN74LVC2952ADW SN74LVC2952ADW Tape and reel SN74LVC2952ADWR SN74LVC2952ADWR SOP ­ NS Tape and reel SN74LVC2952ANSR SN74LVC2952ANSR LVC2952A LVC2952A SSOP ­ DB Tape and reel SN74LVC2952ADBR SN74LVC2952ADBR LE952A LE952A TSSOP ­ PW Tape and reel SN74LVC2952APWR SN74LVC2952APWR LE952A LE952A TA SOIC ­ DW ­40°C to 85°C TOP-SIDE MARKING LVC2952A LVC2952A Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2002, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 1 SN74LVC2952A SN74LVC2952A OCTAL BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS SCAS311H SCAS311H ­ JANUARY 1993 ­ REVISED AUGUST 2002 FUNCTION TABLE INPUTS CLKENAB OUTPUT B CLKAB OEAB A H X L X X H or L L X L L L L L L H H B0 B0 X X H X Z A-to-B data flow is shown; B-to-A data flow is similar, but uses CLKENBA, CLKBA, and OEBA. Level of B before the indicated steady-state input conditions were established logic diagram (positive logic) CLKENAB CLKAB OEAB CLKENBA CLKBA OEBA 11 10 9 13 14 15 C1 A1 16 8 1D C1 1D To Seven Other Channels 2 POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 B1 SN74LVC2952A SN74LVC2952A OCTAL BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS SCAS311H SCAS311H ­ JANUARY 1993 ­ REVISED AUGUST 2002 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ­0.5 V to 6.5 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ­0.5 V to 6.5 V Voltage range applied to any output in the high-impedance or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ­0.5 V to 6.5 V Voltage range applied to any output in the high or low state, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ­0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ­50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ­50 mA Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA Package thermal impedance, JA (see Note 3): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63°C/W DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ­65°C to 150°C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The value of VCC is provided in the recommended oprating conditions table. 3. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 4) MIN VCC Supply voltage VIH Operating High-level input voltage Data retention only VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VCC = 1.65 V to 1.95 V VIL VI VO IOH IOL t/v Low-level input voltage MAX 1.65 3.6 1.5 V 0.65 × VCC V 1.7 2 0.35 × VCC 0.7 VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V Input voltage UNIT V 0.8 0 V 0 3-state Output voltage 5.5 High or low state 0 VCC 5.5 V VCC = 1.65 V VCC = 2.3 V VCC = 2.7 V VCC = 3 V High-level High level output current ­4 ­12 ­8 ­24 VCC = 1.65 V VCC = 2.3 V 4 VCC = 2.7 V VCC = 3 V Low-level Low level output current mA 12 Input transition rise or fall rate 8 mA 24 10 ns/V TA Operating free-air temperature ­40 85 °C NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004 SCBA004. POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 3 SN74LVC2952A SN74LVC2952A OCTAL BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS SCAS311H SCAS311H ­ JANUARY 1993 ­ REVISED AUGUST 2002 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC 1.65 V to 3.6 V IOH = ­100 µA IOH = ­4 mA 1.65 V UNIT 2.4 3V IOH = ­24 mA IOL = 100 µA 2.2 3V IOH = ­12 mA 12 MAX 1.7 2.7 V TYP VCC­0.2 1.2 2.3 V IOH = ­8 mA VOH MIN 2.2 V II Ioff IOZ ICC ICC Ci 0.45 2.3 V 0.7 2.7 V 0.4 3V 0.55 VI = 0 to 5.5 V VI or VO = 5.5 V 3.6 V ±5 µA 0 ±10 µA VO = 0 to 5.5 V VI = VCC or GND 3.6 V VI 5.5 V§ Control inputs 0.2 1.65 V IOL = 12 mA IOL = 24 mA VOL 1.65 V to 3.6 V IOL = 4 mA IOL = 8 mA 3.6 V ±10 µA IO = 0 One input at VCC ­ 0.6 V, Other inputs at VCC or GND Control inputs 10 3.6 36V 10 2.7 V to 3.6 V VI = VCC or GND 500 V µA µA 3.3 V pF 3.3 V Cio A or B ports VO = VCC or GND All typical values are at VCC = 3.3 V, TA = 25°C. For I/O ports, the parameter IOZ includes the input leakage current. § This applies in the disabled state only. 5 8.5 pF timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) VCC = 1.8 V ± 0.15 V MIN fclock tw Clock frequency MAX ¶ VCC = 2.5 V ± 0.2 V MIN MAX ¶ VCC = 2.7 V MIN MAX VCC = 3.3 V ± 0.3 V MIN 150 150 ¶ ¶ 3.3 3.3 Data before CLK high ¶ ¶ 1.7 1.3 CLKEN before CLK high ¶ ¶ 1.3 1.1 Data after CLK high ¶ ¶ 1.8 Setup time th Hold time CLKEN after CLK high ¶ 1.4 1.1 ¶ This information was not available at the time of publication. 4 MHz 1.1 ¶ Pulse duration, CLK high or low tsu UNIT MAX POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 ns ns ns SN74LVC2952A SN74LVC2952A OCTAL BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS SCAS311H SCAS311H ­ JANUARY 1993 ­ REVISED AUGUST 2002 switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) tdis VCC = 2.5 V ± 0.2 V TO (OUTPUT) CLKAB or CLKBA B or A A or B A or B VCC = 2.7 V OE fmax tpd ten VCC = 1.8 V ± 0.15 V FROM (INPUT) OE PARAMETER MIN MAX MIN MAX MIN MAX 150 VCC = 3.3 V ± 0.3 V MIN UNIT MAX 150 MHz 8.8 1 8.2 ns 9 1 7.8 ns 8.8 1 7.8 ns 1 ns tsk(o) This information was not available at the time of publication. operating characteristics, TA = 25°C TEST CONDITIONS PARAMETER Cpd Power dissipation capacitance per transceiver Outputs enabled Outputs disabled VCC = 1.8 V TYP VCC = 2.5 V TYP VCC = 3.3 V TYP f = 10 MHz 79 41 UNIT pF This information was not available at the time of publication. POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 5 SN74LVC2952A SN74LVC2952A OCTAL BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS SCAS311H SCAS311H ­ JANUARY 1993 ­ REVISED AUGUST 2002 PARAMETER MEASUREMENT INFORMATION RL From Output Under Test CL (see Note A) VLOAD Open S1 TEST RL S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH GND Open VLOAD GND LOAD CIRCUIT INPUTS VCC 1.8 V ± 0.15 V 2.5 V ± 0.2 V 2.7 V 3.3 V ± 0.3 V VM VI tr/tf VCC VCC 2.7 V 2.7 V 2 ns 2 ns 2.5 ns 2.5 ns VLOAD CL RL V VCC/2 VCC/2 1.5 V 1.5 V 2 × VCC 2 × VCC 6V 6V 30 pF 30 pF 50 pF 50 pF 1 k 500 500 500 0.15 V 0.15 V 0.3 V 0.3 V VI Timing Input VM 0V tw tsu VI Input VM VM th VI Data Input VM VM 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VI VM Input VM 0V tPLH tPHL VOH VM Output VM VOL tPHL Output Waveform 1 S1 at VLOAD (see Note B) tPLH VM VM VM 0V tPZL tPLZ VLOAD/2 VM tPZH VOH Output VI Output Control VM VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Output Waveform 2 S1 at GND (see Note B) VOL + V VOL tPHZ VM VOH ­ V VOH 0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 . D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms 6 POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 MECHANICAL DATA MPDS006C MPDS006C ­ FEBRUARY 1996 ­ REVISED AUGUST 2000 DGV (R-PDSO-G*) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,40 0,23 0,13 24 13 0,07 M 0,16 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 0°­8° 1 0,75 0,50 12 A Seating Plane 0,15 0,05 1,20 MAX PINS * 0,08 14 16 20 24 38 48 56 A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 DIM 4073251/E 4073251/E 08/00 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side. Falls within JEDEC: 24/48 Pins ­ MO-153 MO-153 14/16/20/56 Pins ­ MO-194 MO-194 POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 1 MECHANICAL DATA MSOI003E MSOI003E ­ JANUARY 1995 ­ REVISED SEPTEMBER 2001 DW (R-PDSO-G*) PLASTIC SMALL-OUTLINE PACKAGE 16 PINS SHOWN 0.020 (0,51) 0.014 (0,35) 9 0.050 (1,27) 16 0.010 (0,25) 0.419 (10,65) 0.400 (10,15) 0.010 (0,25) NOM 0.299 (7,59) 0.291 (7,39) Gage Plane 0.010 (0,25) 1 8 0°­ 8° 0.050 (1,27) 0.016 (0,40) A Seating Plane 0.104 (2,65) MAX 0.012 (0,30) 0.004 (0,10) PINS * 0.004 (0,10) 16 18 20 24 28 A MAX 0.410 (10,41) 0.462 (11,73) 0.510 (12,95) 0.610 (15,49) 0.710 (18,03) A MIN 0.400 (10,16) 0.453 (11,51) 0.500 (12,70) 0.600 (15,24) 0.700 (17,78) DIM 4040000/E 4040000/E 08/01 NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). Falls within JEDEC MS-013 MS-013 POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 1 MECHANICAL DATA MSSO002E MSSO002E ­ JANUARY 1995 ­ REVISED DECEMBER 2001 DB (R-PDSO-G*) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°­8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS * 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-150 MO-150 POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 1 MECHANICAL DATA MTSS001C MTSS001C ­ JANUARY 1995 ­ REVISED FEBRUARY 1999 PW (R-PDSO-G*) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°­ 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS * 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153 MO-153 POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 1 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. 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