SN54LV594A SN74LV594A SCLS413B LV594A A114-A A115-A SCBA004 MIL-PRF-38535 - Datasheet Archive

 

8-BIT SHIFT REGISTERS WITH OUTPUT REGISTERS SCLS413B ­ APRIL 1998 ­ REVISED SEPTEMBER 1999 D D D D 14 4 13 5 12 6 11 7 10

 

SN54LV594A SN54LV594A, SN74LV594A SN74LV594A 8-BIT SHIFT REGISTERS WITH OUTPUT REGISTERS SCLS413B SCLS413B ­ APRIL 1998 ­ REVISED SEPTEMBER 1999 D D D D 14 4 13 5 12 6 11 7 10 8 9 SN54LV594A SN54LV594A . . . FK PACKAGE (TOP VIEW) QD QE NC QF QG description The 'LV594A LV594A devices are 8-bit shift registers designed for 2-V to 5.5-V VCC operation. 15 3 VCC QA SER RCLR RCLK SRCLK SRCLR QH 16 2 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 SER RCLR NC RCLK SRCLK SRCLR D 1 NC VCC QA D QB QC QD QE QF QG QH GND QC QB D SN54LV594A SN54LV594A . . . J OR W PACKAGE SN74LV594A SN74LV594A . . . D, DB, NS, OR PW PACKAGE (TOP VIEW) GND NC Q H D EPIC TM (Enhanced-Performance Implanted CMOS) Process Typical VOLP (Output Ground Bounce) 2 V at VCC = 3.3 V, TA = 25°C 8-Bit Serial-In, Parallel-Out Shift Registers With Storage Independent Direct Overriding Clears on Shift and Storage Registers Independent Clocks for Shift and Storage Registers Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 ­ 2000-V Human-Body Model (A114-A A114-A) ­ 200-V Machine Model (A115-A A115-A) ­ 1000-V Charged-Device Model (C101) Package Options Include Plastic Small-Outline (D, NS), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW) Packages, Ceramic Flat (W) Packages, Chip Carriers (FK), and DIPs (J) QH D NC ­ No internal connection These devices contain an 8-bit serial-in, parallelout shift register that feeds an 8-bit D-type storage register. Separate clocks (RCLK, SRCLK) and direct overriding clear (RCLR, SRCLR) inputs are provided on the shift and storage registers. A serial output (QH) is provided for cascading purposes. The shift-register (SRCLK) and storage-register (RCLK) clocks are positive-edge triggered. If the clocks are tied together, the shift register always is one clock pulse ahead of the storage register. The SN54LV594A SN54LV594A is characterized for operation over the full military temperature range of ­55°C to 125°C. The SN74LV594A SN74LV594A is characterized for operation from ­40°C to 85°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC is a trademark of Texas Instruments Incorporated. Copyright © 1999, Texas Instruments Incorporated UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 1 SN54LV594A SN54LV594A, SN74LV594A SN74LV594A 8-BIT SHIFT REGISTERS WITH OUTPUT REGISTERS SCLS413B SCLS413B ­ APRIL 1998 ­ REVISED SEPTEMBER 1999 FUNCTION TABLE INPUTS FUNCTION SER SRCLK SRCLR RCLK RCLR X X L X X Shift register is cleared. L H X X First stage of shift register goes low. Other stages store the data of previous stage, respectively. H H X X First stage of shift register goes high. Other stages store the data of previous stage, respectively. L # H X X Shift register state is not changed. X X X X L Storage register is cleared. X X X H Shift register data is stored in the storage register. X X X # H Storage register state is not changed. logic symbol RCLR RCLK SRCLR SRCLK SER 13 12 10 11 R3 C2 SRG8 R C1/ 14 1D 2D 3 15 1 2 3 QA QB QC QD 4 5 6 2D 3 7 9 QE QF QG QH QH This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, DB, J, NS, PW, and W packages. 2 POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 SN54LV594A SN54LV594A, SN74LV594A SN74LV594A 8-BIT SHIFT REGISTERS WITH OUTPUT REGISTERS SCLS413B SCLS413B ­ APRIL 1998 ­ REVISED SEPTEMBER 1999 logic diagram (positive logic) RCLR RCLK SRCLR SRCLK SER 13 12 10 11 14 R 3D Q C3 2D Q C2 R 1 R 3D Q C3 2D Q C2 R 15 R 3D Q C3 1D Q C1 R 2 R 3D Q C3 2D Q C2 R R 3D Q C3 2D Q C2 R 3 4 R 3D Q C3 2D Q C2 R 6 R 3D Q C3 2D Q C2 R 5 R 3D Q C3 2D Q C2 R 7 9 Pin numbers shown are for the D, DB, J, NS, PW, and W packages. POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 QA QB QC QD QE QF QG QH QH 3 SN54LV594A SN54LV594A, SN74LV594A SN74LV594A 8-BIT SHIFT REGISTERS WITH OUTPUT REGISTERS SCLS413B SCLS413B ­ APRIL 1998 ­ REVISED SEPTEMBER 1999 timing diagram SRCLK SER RCLK SRCLR RCLR ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ QA QB QC QD QE QF QG QH QH' 4 POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 SN54LV594A SN54LV594A, SN74LV594A SN74LV594A 8-BIT SHIFT REGISTERS WITH OUTPUT REGISTERS SCLS413B SCLS413B ­ APRIL 1998 ­ REVISED SEPTEMBER 1999 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ­0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ­0.5 V to 7 V Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ­0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ­20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±35 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±70 mA Package thermal impedance, JA (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ­65°C to 150°C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. This value is limited to 7 V maximum. 3. The package thermal impedance is calculated in accordance with JESD 51. recommended operating conditions (see Note 4) SN54LV594A SN54LV594A SN74LV594A SN74LV594A MIN VCC VIH VIL VI VO IOH IOL High level input voltage High-level Low-level Low level input voltage VCC = 2 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V MIN MAX 2 Supply voltage MAX 5.5 2 5.5 1.5 VCC × 0.7 VCC × 0.7 VCC × 0.7 VCC = 2 V VCC = 2.3 V to 2.7 V 0.5 VCC × 0.3 VCC × 0.3 VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V 0 Output voltage 0 Low-level Low level output current V VCC × 0.7 0.5 Input voltage High-level High level output current VCC = 2 V VCC = 2.3 V to 2.7 V VCC × 0.3 VCC × 0.3 VCC × 0.3 5.5 VCC × 0.3 5.5 VCC ­50 0 0 ­2 VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V VCC ­50 Input transition rise or fall rate V V V µA ­2 ­6 ­6 ­12 VCC = 2 V VCC = 2.3 V to 2.7 V 50 50 2 2 VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V 6 6 mA ­12 12 µA mA 12 VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V 0 200 0 200 0 100 0 100 VCC = 4.5 V to 5.5 V t/v V 1.5 VCC × 0.7 VCC × 0.7 UNIT 0 20 0 20 ns/V TA Operating free-air temperature ­55 125 ­40 85 °C NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004 SCBA004. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 5 SN54LV594A SN54LV594A, SN74LV594A SN74LV594A 8-BIT SHIFT REGISTERS WITH OUTPUT REGISTERS SCLS413B SCLS413B ­ APRIL 1998 ­ REVISED SEPTEMBER 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VOH VOL SN54LV594A SN54LV594A TEST CONDITIONS IOH = ­50 µA IOH = ­2 mA VCC 2 V to 5.5 V MIN TYP SN74LV594A SN74LV594A MAX MIN TYP VCC­0.1 2 VCC­0.1 2 3V 2.48 2.48 4.5 V 3.8 2.3 V IOH = ­6 mA IOH = ­12 mA IOL = 50 µA IOL = 2 mA MAX UNIT V 3.8 2 V to 5.5 V 0.1 0.1 2.3 V 0.4 0.4 3V 0.44 0.44 4.5 V 0.55 0.55 5.5 V ±1 ±1 µA 5.5 V 20 20 µA 0V 5 5 µA IOL = 6 mA IOL = 12 mA II ICC VI = VCC or GND VI = VCC or GND, Ioff VI or VO = 0 to 5.5 V Ci VI = VCC or GND IO = 0 3.3 V 3.5 3.5 5V 2 2 V pF timing requirements over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1) TA = 25°C MIN MAX SN54LV594A SN54LV594A MIN MAX SN74LV594A SN74LV594A MIN Pulse duration RCLK or SRCLK high or low 7 7.5 7.5 RCLR or SRCLR low 6 6.5 6.5 SER before SRCLK tw 2.5 3 Setup time UNIT 3 SRCLK before RCLK tsu MAX 8 SRCLR high (inactive) before SRCLK RCLR high (inactive) before RCLK 9 9 8.5 SRCLR low before RCLK 9.5 9.5 6 6.8 6.8 6.7 7.6 ns 7.6 ns th Hold time SER after SRCLK 1.5 1.5 1.5 ns This setup time ensures the output register sees stable data from the shift-register outputs. The clocks can be tied together, in which case the shift register is one clock pulse ahead of the storage register. timing requirements over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) TA = 25°C MIN MAX MIN MAX SN74LV594A SN74LV594A MIN Pulse duration 5.5 5.5 5.5 RCLR or SRCLR low 5 5 5 SER before SRCLK tw RCLK or SRCLK high or low SN54LV594A SN54LV594A 8 8.5 8 9 9 4.2 4.8 4.8 4.6 5.3 ns 8.5 SRCLR low before RCLK UNIT 3.5 RCLR high (inactive) before RCLK Setup time 3.5 SRCLR high (inactive) before SRCLK tsu 3.5 SRCLK before RCLK MAX 5.3 ns th Hold time SER after SRCLK 1.5 1.5 1.5 ns This setup time ensures the output register sees stable data from the shift-register outputs. The clocks can be tied together, in which case the shift register is one clock pulse ahead of the storage register. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 6 POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 SN54LV594A SN54LV594A, SN74LV594A SN74LV594A 8-BIT SHIFT REGISTERS WITH OUTPUT REGISTERS SCLS413B SCLS413B ­ APRIL 1998 ­ REVISED SEPTEMBER 1999 timing requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) TA = 25°C MIN MAX MIN MAX SN74LV594A SN74LV594A MIN 5 3 3 5 5 5 5 5 2.9 3.3 3.3 RCLR high (inactive) before RCLK 3.2 3.7 UNIT 3 5 MAX 5.2 SRCLR low before RCLK Setup time 5 5.2 SRCLR high (inactive) before SRCLK tsu 5 5.2 SRCLK before RCLK Pulse duration RCLR or SRCLR low SER before SRCLK tw RCLK or SRCLK high or low SN54LV594A SN54LV594A 3.7 ns ns th Hold time SER after SRCLK 2 2 2 ns This setup time ensures the output register sees stable data from the shift-register outputs. The clocks can be tied together, in which case the shift register is one clock pulse ahead of the storage register. switching characteristics over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) MIN TA = 25°C TYP MAX SN54LV594A SN54LV594A MIN MAX SN74LV594A SN74LV594A MIN CL = 15 pF* 65 80 45 60 70 40 40 6.4 1 6.3 QA­QH Q 10.6 10.4 7.4 RCLK MAX 45 CL = 50 pF fmax tPLH* tPHL* LOAD CAPACITANCE 12.1 7.2 UNIT MHz 11.1 1 11.1 1 11.1 1 11.1 1 12.8 1 12.8 11.6 1 12.8 1 12.8 12.7 1 13.6 1 13.6 tPLH* tPHL* SRCLK QH tPHL* RCLR QA­QH 7.9 tPHL* tPLH SRCLR QH 7.4 11.9 1 13.1 1 13.1 9.5 14.1 1 14.6 1 14.6 10.8 15.5 1 17.2 1 17.2 10.6 15.7 1 16.5 1 16.5 11.3 16.1 1 18.6 1 18.6 12.1 RCLR QA­QH tPHL 11.6 SRCLR QH * On products compliant to MIL-PRF-38535 MIL-PRF-38535, this parameter is not production tested. 17.4 1 19 1 19 16.5 1 18.6 1 18.6 tPHL tPLH tPHL tPHL RCLK QA­QH Q SRCLK QH CL = 15 pF CL = 50 pF ns ns PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 7 SN54LV594A SN54LV594A, SN74LV594A SN74LV594A 8-BIT SHIFT REGISTERS WITH OUTPUT REGISTERS SCLS413B SCLS413B ­ APRIL 1998 ­ REVISED SEPTEMBER 1999 switching characteristics over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) MIN TA = 25°C TYP MAX SN54LV594A SN54LV594A MIN MAX SN74LV594A SN74LV594A MIN CL = 15 pF* 80 120 70 55 105 50 MAX 70 CL = 50 pF fmax tPLH* tPHL* LOAD CAPACITANCE 50 MHz 4.6 tPLH* tPHL* SRCLK QH tPHL* RCLR QA­QH 8.5 1 8.5 8.2 1 8.8 1 8.8 9.1 1 9.7 1 9.7 5.5 CL = 15 pF 1 4.9 QA­QH Q 8 5.4 RCLK UNIT 9.2 1 9.9 1 9.9 6 9.8 1 10.6 1 10.6 5.6 9.2 1 10 1 10 6.9 10.5 1 11.1 1 11.1 8.1 11.9 1 13.1 1 13.1 7.7 11.7 1 12.4 1 12.4 8.4 12.5 1 13.9 1 13.9 9.1 13.1 1 14.4 1 14.4 tPHL 8.5 SRCLR QH * On products compliant to MIL-PRF-38535 MIL-PRF-38535, this parameter is not production tested. 12.4 1 14 1 ns 14 tPHL* tPLH tPHL tPLH tPHL tPHL SRCLR QH RCLK QA­QH Q SRCLK QH RCLR QA­QH CL = 50 pF ns switching characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) TA = 25°C MIN TYP MAX SN54LV594A SN54LV594A MIN MAX SN74LV594A SN74LV594A MIN CL = 15 pF* 135 170 115 120 140 95 MAX 115 CL = 50 pF fmax tPLH* tPHL* LOAD CAPACITANCE 95 MHz 3.3 QA­QH Q 6.2 1 6.5 1 6.5 3.7 6.5 1 6.9 1 6.9 3.7 RCLK UNIT 6.8 1 7.2 1 7.2 4.1 7.2 1 7.6 1 7.6 tPLH* tPHL* SRCLK QH tPHL* RCLR QA­QH 4.5 7.6 1 8.2 1 8.2 tPHL* tPLH SRCLR QH 4.1 7.1 1 7.6 1 7.6 4.9 7.8 1 8.3 1 8.3 5.8 8.9 1 9.7 1 9.7 5.5 8.6 1 9.1 1 9.1 6 9.2 1 10.1 1 10.1 6.6 RCLR QA­QH tPHL 6 SRCLR QH * On products compliant to MIL-PRF-38535 MIL-PRF-38535, this parameter is not production tested. 10 1 10.7 1 10.7 9.2 1 10.1 1 10.1 tPHL tPLH tPHL RCLK SRCLK CL = 15 pF QA­QH Q QH CL = 50 pF tPHL PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 8 POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 ns ns SN54LV594A SN54LV594A, SN74LV594A SN74LV594A 8-BIT SHIFT REGISTERS WITH OUTPUT REGISTERS SCLS413B SCLS413B ­ APRIL 1998 ­ REVISED SEPTEMBER 1999 noise characteristics, VCC = 3.3 V, CL = 50 pF, TA = 25°C (see Note 5) SN74LV594A SN74LV594A PARAMETER MIN TYP MAX UNIT VOL(P) VOL(V) Quiet output, maximum dynamic VOL 0.5 0.8 V Quiet output, minimum dynamic VOL ­0.1 ­0.8 V VOH(V) VIH(D) Quiet output, minimum dynamic VOH 2.8 High-level dynamic input voltage V 2.31 V VIL(D) Low-level dynamic input voltage NOTE 5: Characteristics are for surface-mount packages only. 0.99 V VCC 3.3 V TYP UNIT 5V 112 operating characteristics, TA = 25°C PARAMETER Cpd TEST CONDITIONS Power dissi ation ca acitance dissipation capacitance f = 10 MHz POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 93 pF F 9 SN54LV594A SN54LV594A, SN74LV594A SN74LV594A 8-BIT SHIFT REGISTERS WITH OUTPUT REGISTERS SCLS413B SCLS413B ­ APRIL 1998 ­ REVISED SEPTEMBER 1999 PARAMETER MEASUREMENT INFORMATION RL = 1 k From Output Under Test Test Point From Output Under Test VCC Open S1 TEST GND CL (see Note A) CL (see Note A) S1 Open VCC GND VCC tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS VCC 50% VCC Timing Input 0V tw tsu VCC 50% VCC 50% VCC Input th VCC 50% VCC Data Input 50% VCC 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC 50% VCC Input 50% VCC 0V tPLH In-Phase Output tPHL Out-of-Phase Output VOH 50% VCC VOL VOH 50% VCC VOL 50% VCC 0V tPLZ VCC Output Waveform 1 S1 at VCC (see Note B) 50% VCC tPZH tPLH 50% VCC 50% VCC tPZL tPHL 50% VCC VCC Output Control Output Waveform 2 S1 at GND (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS VOL + 0.3 V VOL tPHZ 50% VCC VOH ­ 0.3 V VOH 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO = 50 , tr 3 ns, tf 3 ns. D. The outputs are measured one at a time with one input transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPHL and tPLH are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms 10 POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. 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