SN74LV125AT SCES629A A114-A A115-A SN74LV125ATDR SN74LV125ATNS SN74LV125ATNSR - Datasheet Archive

 

QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS www.ti.com SCES629A ­ MAY 2005 ­ REVISED AUGUST 2005 FEATURES ·

 

SN74LV125AT SN74LV125AT QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS www.ti.com SCES629A SCES629A ­ MAY 2005 ­ REVISED AUGUST 2005 FEATURES · · · · · · Inputs Are TTL-Voltage Compatible 4.5-V to 5.5-V VCC Operation Typical tpd of 3.8 ns at 5 V Typical VOLP (Output Ground Bounce) 2.3 V at VCC = 5 V, TA = 25°C Support Mixed-Mode Voltage Operation on All Ports · · · Ioff Supports Partial-Power-Down Mode Operation Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds JESD 22 ­ 2000-V Human-Body Model (A114-A A114-A) ­ 200-V Machine Model (A115-A A115-A) ­ 1000-V Charged-Device Model (C101) XXXX XXXX 13 3 12 4 11 5 10 6 9 7 8 1 VCC 4OE 4A 4Y 3OE 3A 3Y 1A 1Y 2OE 2A 2Y 14 2 13 4OE 3 12 4A 4 11 4Y 5 6 10 3OE 9 3A 7 8 3Y 14 2 1OE 1 GND 1OE 1A 1Y 2OE 2A 2Y GND VCC RGY PACKAGE (TOP VIEW) D, DB, NS, OR PW PACKAGE (TOP VIEW) DESCRIPTION/ORDERING INFORMATION The SN74LV125AT SN74LV125AT is a quadruple bus buffer gate. This device features independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is high. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. ORDERING INFORMATION PACKAGE (1) TA QFN ­ RGY ORDERABLE PART NUMBER ­40°C to 85°C SSOP ­ DB TSSOP ­ PW (1) Tube of 50 Reel of 2500 SN74LV125ATDR SN74LV125ATDR Tube of 50 SN74LV125ATNS SN74LV125ATNS Reel of 2000 SN74LV125ATNSR SN74LV125ATNSR Tube of 80 SN74LV125ATDB SN74LV125ATDB Reel of 2000 SN74LV125ATDBR SN74LV125ATDBR SN74LV125ATPW SN74LV125ATPW Reel of 2000 TOP-SIDE MARKING SN74LV125ATD SN74LV125ATD SN74LV125ATPWR SN74LV125ATPWR Reel of 250 SOP ­ NS SN74LV125ATRGYR SN74LV125ATRGYR Tube of 90 SOIC ­ D Reel of 1000 VV125 VV125 SN74LV125ATPWT SN74LV125ATPWT LV125AT LV125AT Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2005, Texas Instruments Incorporated SN74LV125AT SN74LV125AT QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS www.ti.com SCES629A SCES629A ­ MAY 2005 ­ REVISED AUGUST 2005 FUNCTION TABLE (EACH BUFFER) INPUTS OE A OUTPUT Y L H H L L L H X Z LOGIC DIAGRAM (POSITIVE LOGIC) 1OE 1A 1 2 3OE 3 1Y 3A 8 9 3Y 13 4 4OE 2OE 2A 10 5 6 2Y 4A 11 12 4Y Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VCC Supply voltage range ­0.5 7 V VI Input voltage range (2) ­0.5 7 V VO Voltage range applied to any output in the high-impedance or power-off state (2) ­0.5 7 V VO Output voltage range (2) (3) ­0.5 VCC + 0.5 V IIK Input clamp current VI < 0 ­20 mA IOK Output clamp current VO < 0 or VO > VCC ±50 mA IO Continuous output current VO = 0 to VCC ±35 mA ±70 mA Continuous current through VCC or GND D package (4) DB package (4) JA 86 96 76 PW package (4) Package thermal impedance package (4) RGY package (5) Tstg (1) (2) (3) (4) (5) 2 Storage temperature range °C/W 113 NS 47 ­65 150 °C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. This value is limited to 5.5 V maximum. The package thermal impedance is calculated in accordance with JESD 51-7. The package thermal impedance is calculated in accordance with JESD 51-5. SN74LV125AT SN74LV125AT QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS www.ti.com SCES629A SCES629A ­ MAY 2005 ­ REVISED AUGUST 2005 Recommended Operating Conditions (1) MIN 4.5 VCC High-level input voltage VCC = 4.5 V to 5.5 V VIL Low-level input voltage VCC = 4.5 V to 5.5 V VI 5.5 Supply voltage VIH MAX Input voltage UNIT V 2 V 0.8 V V 0 5.5 High or low state 0 VCC 3-state 0 5.5 VO Output voltage IOH High-level output current VCC = 4.5 V to 5.5 V ­16 IOL Low-level output current VCC = 4.5 V to 5.5 V 16 mA t/v Input transition rise or fall rate VCC = 4.5 V to 5.5 V 20 ns/V TA Operating free-air temperature 125 °C (1) ­40 V mA All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004 SCBA004. Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN VOH VOL TA = ­40°C to 85°C TA = 25°C TYP 4.5 IOH = ­50 µA 4.5 V 4.4 IOH = ­16 mA 4.5 V 4.5 V IOL = 16 mA 4.5 V MIN 3.8 IOL = 50 µA MAX TA = ­40°C to 125°C MAX MIN 4.4 0 4.4 3.8 UNIT MAX 3.8 V 0.1 0.1 0.1 0.55 0.55 0.55 V II VI = 5.5 V or GND 0 to 5.5 V ±0.1 ±1 ±1 µA IOZ VO = VCC or GND 5.5 V ±0.25 ±2.5 ±2.5 µA ICC VI = VCC or GND, IO = 0 5.5 V 2 20 20 µA One input at 3.4 V, Other inputs at VCC or GND 5.5 V 1.35 1.5 1.5 mA 0 0.5 5 5 µA ICC (1) Ioff Ci (1) VI or VO = 0 to 5.5 V VI = VCC or GND 2 pF This is the increase in supply current for each input at one of the specified TTL voltage levels, rather than 0 V or VCC. Switching Characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE tpd A Y ten OE Y tdis OE tpd ten tdis OE PARAMETER tsk(o) TA = ­40°C to 85°C TA = 25°C TA = ­40°C to 125°C UNIT MIN TYP MAX MIN MAX MIN MAX CL = 15 pF 1.9 3.8 5.5 1 6.5 1 8.5 ns CL = 15 pF 2 3.6 5.1 1 6 1 7.5 ns Y CL = 15 pF 1.5 3.2 6.8 1 8 1 10 ns A Y CL = 50 pF 2.9 5.3 7.5 1 8.5 1 10.5 ns OE Y CL = 50 pF 2.8 5.1 7.1 1 8 1 9.5 ns Y CL = 50 pF 2.8 6.1 8.8 1 10 1 10 ns 1 ns CL = 50 pF 1 1 3 SN74LV125AT SN74LV125AT QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS www.ti.com SCES629A SCES629A ­ MAY 2005 ­ REVISED AUGUST 2005 Noise Characteristics (1) VCC = 5 V, CL = 50 pF, TA = 25°C TYP MAX VOL(P) Quiet output, maximum dynamic VOL MIN 1.1 1.5 V VOL(V) Quiet output, minimum dynamic VOL ­0.3 ­0.8 V VOH(V) Quiet output, minimum dynamic VOH VIH(D) High-level dynamic input voltage VIL(D) Low-level dynamic input voltage (1) 3 UNIT V 2 V 0.8 V Characteristics are for surface-mount packages only. Operating Characteristics VCC = 5 V, TA - 25°C PARAMETER Cpd 4 Power dissipation capacitance TEST CONDITIONS Outputs enabled CL = 50 pF, f = 10 MHz TYP 16 UNIT pF SN74LV125AT SN74LV125AT QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS www.ti.com SCES629A SCES629A ­ MAY 2005 ­ REVISED AUGUST 2005 PARAMETER MEASUREMENT INFORMATION VCC From Output Under Test Test Point RL = 1 k From Output Under Test CL (see Note A) S1 Open TEST GND CL (see Note A) LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain Open VCC GND VCC LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS 3V 1.5 V Timing Input 0V tw 3V 1.5 V Input 1.5 V th tsu 3V 1.5 V Data Input 1.5 V 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 3V 1.5 V Input 1.5 V 0V tPLH tPHL VOH In-Phase Output 50% VCC tPHL Out-of-Phase Output 50% VCC VOL Output Waveform 1 S1 at VCC (see Note B) VOH 50% VCC VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 1.5 V 1.5 V 0V tPZL tPLZ VCC 50% VCC tPZH tPLH 50% VCC 3V Output Control Output Waveform 2 S1 at GND (see Note B) VOL + 0.3 V VOL tPHZ 50% VCC VOH - 0.3 V VOH 0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO = 50 , tr 3 ns, tf 3 ns. D. The outputs are measured one at a time, with one input transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPHL and tPLH are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuits and Voltage Waveforms 5 PACKAGE OPTION ADDENDUM www.ti.com 8-Dec-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SN74LV125ATD SN74LV125ATD ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV125ATDB SN74LV125ATDB ACTIVE SSOP DB 14 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV125ATDBE4 SN74LV125ATDBE4 ACTIVE SSOP DB 14 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV125ATDBG4 SN74LV125ATDBG4 ACTIVE SSOP DB 14 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV125ATDBR SN74LV125ATDBR ACTIVE SSOP DB 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV125ATDBRE4 SN74LV125ATDBRE4 ACTIVE SSOP DB 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV125ATDBRG4 SN74LV125ATDBRG4 ACTIVE SSOP DB 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV125ATDE4 SN74LV125ATDE4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV125ATDG4 SN74LV125ATDG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV125ATDR SN74LV125ATDR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV125ATDRE4 SN74LV125ATDRE4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV125ATDRG4 SN74LV125ATDRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV125ATNS SN74LV125ATNS ACTIVE SO NS 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV125ATNSE4 SN74LV125ATNSE4 ACTIVE SO NS 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV125ATNSG4 SN74LV125ATNSG4 ACTIVE SO NS 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV125ATNSR SN74LV125ATNSR ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV125ATNSRE4 SN74LV125ATNSRE4 ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV125ATNSRG4 SN74LV125ATNSRG4 ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV125ATPW SN74LV125ATPW ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV125ATPWE4 SN74LV125ATPWE4 ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV125ATPWG4 SN74LV125ATPWG4 ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV125ATPWR SN74LV125ATPWR ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV125ATPWRE4 SN74LV125ATPWRE4 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV125ATPWRG4 SN74LV125ATPWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV125ATPWT SN74LV125ATPWT ACTIVE TSSOP PW 14 250 CU NIPDAU Level-1-260C-UNLIM Addendum-Page 1 Green (RoHS & no Sb/Br) Lead/Ball Finish MSL Peak Temp (3) PACKAGE OPTION ADDENDUM www.ti.com 8-Dec-2009 Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SN74LV125ATPWTE4 SN74LV125ATPWTE4 ACTIVE TSSOP PW 14 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV125ATPWTG4 SN74LV125ATPWTG4 ACTIVE TSSOP PW 14 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV125ATRGYR SN74LV125ATRGYR ACTIVE VQFN RGY 14 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR SN74LV125ATRGYRG4 SN74LV125ATRGYRG4 ACTIVE VQFN RGY 14 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 8-Dec-2009 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SN74LV125ATDBR SN74LV125ATDBR SSOP SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) DB 14 2000 330.0 16.4 8.2 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 6.6 2.5 12.0 16.0 Q1 SN74LV125ATDR SN74LV125ATDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 SN74LV125ATNSR SN74LV125ATNSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 SN74LV125ATPWR SN74LV125ATPWR TSSOP PW 14 2000 330.0 12.4 7.0 5.6 1.6 8.0 12.0 Q1 SN74LV125ATRGYR SN74LV125ATRGYR VQFN RGY 14 3000 180.0 12.4 3.75 3.75 1.15 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 8-Dec-2009 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74LV125ATDBR SN74LV125ATDBR SSOP DB 14 2000 346.0 346.0 33.0 SN74LV125ATDR SN74LV125ATDR SOIC D 14 2500 346.0 346.0 33.0 SN74LV125ATNSR SN74LV125ATNSR SO NS 14 2000 346.0 346.0 33.0 SN74LV125ATPWR SN74LV125ATPWR TSSOP PW 14 2000 346.0 346.0 29.0 SN74LV125ATRGYR SN74LV125ATRGYR VQFN RGY 14 3000 190.5 212.7 31.8 Pack Materials-Page 2 MECHANICAL DATA MSSO002E MSSO002E ­ JANUARY 1995 ­ REVISED DECEMBER 2001 DB (R-PDSO-G*) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°­8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS * 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-150 MO-150 POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 MECHANICAL DATA MTSS001C MTSS001C ­ JANUARY 1995 ­ REVISED FEBRUARY 1999 PW (R-PDSO-G*) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°­ 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS * 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. 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