SN54HCT240 SN74HCT240 SCLS174D HCT240 SN74HCT240N SN74HCT240DW SN74HCT240DWR - Datasheet Archive

 

OCTAL BUFFERS AND LINE DRIVERS WITH 3STATE OUTPUTS SCLS174D ­ MARCH 1984 ­ REVISED DECEMBER 2002 D Operating Voltage

 

SN54HCT240 SN54HCT240, SN74HCT240 SN74HCT240 OCTAL BUFFERS AND LINE DRIVERS WITH 3STATE OUTPUTS SCLS174D SCLS174D ­ MARCH 1984 ­ REVISED DECEMBER 2002 D Operating Voltage Range of 4.5 V to 5.5 V D High-Current Outputs Drive Up To 15 LSTTL Loads Low Power Consumption, 80-µA Max ICC Typical tpd = 12 ns ±6-mA Output Drive at 5 V Low Input Current of 1 µA Max Inputs Are TTL-Voltage Compatible 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers 1OE 1A1 2Y4 1A2 2Y3 1A3 2Y2 1A4 2Y1 GND description/ordering information These octal buffers and line drivers are designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The 'HCT240 HCT240 devices are organized as two 4-bit buffers/drivers with separate output-enable (OE) inputs. When OE is low, the device passes inverted data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-impedance state. 1 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 VCC 2OE 1Y1 2A4 1Y2 2A3 1Y3 2A2 1Y4 2A1 20 11 2Y4 1A1 1OE VCC SN54HCT240 SN54HCT240 . . . FK PACKAGE (TOP VIEW) 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 1Y1 2A4 1Y2 2A3 1Y3 2Y1 GND 2A1 1Y4 2A2 1A2 2Y3 1A3 2Y2 1A4 2OE D D D D D D SN54HCT240 SN54HCT240 . . . J OR W PACKAGE SN74HCT240 SN74HCT240 . . . DW, N, NS, OR PW PACKAGE (TOP VIEW) ORDERING INFORMATION ORDERABLE PART NUMBER PACKAGE TA PDIP ­ N TOP-SIDE MARKING Tube SN74HCT240N SN74HCT240N Tube SN74HCT240DW SN74HCT240DW Tape and reel SN74HCT240DWR SN74HCT240DWR Tape and reel SN74HCT240NSR SN74HCT240NSR Tube SN74HCT240PW SN74HCT240PW Tape and reel SN74HCT240PWR SN74HCT240PWR CDIP ­ J Tube SNJ54HCT240J SNJ54HCT240J SNJ54HCT240J SNJ54HCT240J CFP ­ W Tube SNJ54HCT240W SNJ54HCT240W SNJ54HCT240W SNJ54HCT240W SOIC ­ DW ­40°C to 85°C 40°C SOP ­ NS TSSOP ­ PW ­55°C to 125 C 55 C 125°C SN74HCT240N SN74HCT240N HCT240 HCT240 HCT240 HCT240 HT240 HT240 LCCC ­ FK Tube SNJ54HCT240FK SNJ54HCT240FK SNJ54HCT240FK SNJ54HCT240FK Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2002, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. On products compliant to MILPRF38535 MILPRF38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 1 SN54HCT240 SN54HCT240, SN74HCT240 SN74HCT240 OCTAL BUFFERS AND LINE DRIVERS WITH 3STATE OUTPUTS SCLS174D SCLS174D ­ MARCH 1984 ­ REVISED DECEMBER 2002 FUNCTION TABLE (each buffer/driver) INPUTS OE A OUTPUT Y L H L L L H H X Z logic diagram (positive logic) 1OE 1A1 1A2 1A3 1A4 1 2OE 2 4 18 16 6 14 8 12 1Y1 2A1 1Y2 2A2 1Y3 2A3 1Y4 2A4 19 11 9 13 7 15 5 17 3 2Y1 2Y2 2Y3 2Y4 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ­0.5 V to 7 V Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±35 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±70 mA Package thermal impedance, JA (see Note 2): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ­65°C to 150°C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. 2 POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 SN54HCT240 SN54HCT240, SN74HCT240 SN74HCT240 OCTAL BUFFERS AND LINE DRIVERS WITH 3STATE OUTPUTS SCLS174D SCLS174D ­ MARCH 1984 ­ REVISED DECEMBER 2002 recommended operating conditions (see Note 3) SN54HCT240 SN54HCT240 SN74HCT240 SN74HCT240 MIN NOM MAX MIN NOM MAX 4.5 5 5.5 4.5 5 5.5 VCC VIH Supply voltage VIL VI Low-level input voltage Input voltage 0 VO t/v Output voltage 0 High-level input voltage VCC = 4.5 V to 5.5 V VCC = 4.5 V to 5.5 V 2 2 Input transition rise/fall time V V 0.8 VCC VCC UNIT 0.8 500 V 500 0 V VCC VCC 0 ns V TA Operating free-air temperature ­55 125 ­40 85 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004 SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC VOH VI = VIH or VIL IOH = ­20 µA IOH = ­6 mA 4.5 45V VOL VI = VIH or VIL IOL = 20 µA IOL = 6 mA 45V 4.5 II IOZ VI = VCC or 0 VO = VCC or 0, MIN ICC ICC TA = 25°C TYP MAX SN54HCT240 SN54HCT240 MIN MAX SN74HCT240 SN74HCT240 MIN 4.4 4.499 4.4 4.3 3.7 3.84 UNIT 4.4 3.98 MAX V 0.1 0.1 0.1 0.17 0.26 0.4 0.33 5.5 V VI = VIH or VIL VI = VCC or 0, IO = 0 One input at 0.5 V or 2.4 V, Other inputs at 0 or VCC 0.001 ±0.1 ±100 ±1000 ±1000 nA 5.5 V ±0.01 ±0.5 ±10 ±5 µA 8 160 80 µA 1.4 2.4 3 2.9 mA 3 10 10 10 pF 5.5 V 5.5 V 4.5 V to 5.5 V Ci V This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than 0 V or VCC. switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) tpd A Y ten OE Y tdis OE Y VCC MIN TA = 25°C TYP MAX SN54HCT240 SN54HCT240 MIN MAX SN74HCT240 SN74HCT240 MIN MAX 4.5 V 37 32 5.5 V 12 23 33 29 21 35 53 44 5.5 V 19 32 48 40 4.5 V Y 25 4.5 V tt 13 19 35 53 44 5.5 V 18 32 48 40 4.5 V 8 12 18 15 5.5 V 7 11 16 14 UNIT POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 ns ns ns ns 3 SN54HCT240 SN54HCT240, SN74HCT240 SN74HCT240 OCTAL BUFFERS AND LINE DRIVERS WITH 3STATE OUTPUTS SCLS174D SCLS174D ­ MARCH 1984 ­ REVISED DECEMBER 2002 switching characteristics over recommended operating free-air temperature range, CL = 150 pF (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) tpd A Y ten OE Y VCC MIN TA = 25°C TYP MAX SN54HCT240 SN54HCT240 MIN MAX SN74HCT240 SN74HCT240 MIN MAX 4.5 V Y 42 63 53 19 38 56 48 4.5 V tt 20 5.5 V 25 52 79 65 5.5 V 22 47 71 59 4.5 V 17 42 63 53 5.5 V 14 38 57 48 UNIT ns ns ns operating characteristics, TA = 25°C PARAMETER Cpd 4 TEST CONDITIONS Power dissipation capacitance No load POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 TYP 40 UNIT pF SN54HCT240 SN54HCT240, SN74HCT240 SN74HCT240 OCTAL BUFFERS AND LINE DRIVERS WITH 3STATE OUTPUTS SCLS174D SCLS174D ­ MARCH 1984 ­ REVISED DECEMBER 2002 PARAMETER MEASUREMENT INFORMATION VCC From Output Under Test CL (see Note A) S1 Test Point RL S2 1 k tPZL tPHZ tdis 50 pF or 150 pF Open Closed Closed Open Open Closed Open Open Open 50 pF tPLZ ­­ LOAD CIRCUIT 2.7 V S2 1 k tpd or tt Input 1.3 V 0.3 V S1 RL tPZH ten CL Closed PARAMETER 2.7 V 50 pF or 150 pF 3V 1.3 V 0.3 V 0 V tr tf VOLTAGE WAVEFORM INPUT RISE AND FALL TIMES 3V Input 1.3 V 1.3 V 0V tPLH In-Phase Output 1.3 V 10% tPHL 90% 90% tr tPHL Out-ofPhase Output 90% VOH 1.3 V 10% V OL tf tPLH 1.3 V 10% 1.3 V 10% tf Output Control (Low-Level Enabling) 3V 1.3 V 1.3 V 0V tPZL Output Waveform 1 (See Note B) tPLZ VCC 1.3 V 10% tPZH 90% VOH VOL tr VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT RISE AND FALL TIMES Output Waveform 2 (See Note B) VOL tPHZ 1.3 V 90% VOH 0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS NOTES: A. CL includes probe and test-fixture capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO = 50 , tr = 6 ns, tf = 6 ns. D. The outputs are measured one at a time with one input transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 5 MECHANICAL DATA MLCC006B MLCC006B ­ OCTOBER 1996 FK (S-CQCC-N*) LEADLESS CERAMIC CHIP CARRIER 28 TERMINAL SHOWN 18 17 16 15 14 13 NO. OF TERMINALS * 12 A B 11 20 MAX MIN MAX 20 0.342 (8,69) 0.358 (9,09) 0.307 (7,80) 0.358 (9,09) 28 19 MIN 0.442 (11,23) 0.458 (11,63) 0.406 (10,31) 0.458 (11,63) 10 21 9 22 8 44 0.640 (16,26) 0.660 (16,76) 0.495 (12,58) 0.560 (14,22) 23 7 52 0.739 (18,78) 0.761 (19,32) 0.495 (12,58) 0.560 (14,22) 24 6 68 0.938 (23,83) 0.962 (24,43) 0.850 (21,6) 0.858 (21,8) 84 1.141 (28,99) 1.165 (29,59) 1.047 (26,6) 1.063 (27,0) B SQ A SQ 25 5 26 27 28 1 2 3 4 0.080 (2,03) 0.064 (1,63) 0.020 (0,51) 0.010 (0,25) 0.020 (0,51) 0.010 (0,25) 0.055 (1,40) 0.045 (1,14) 0.045 (1,14) 0.035 (0,89) 0.045 (1,14) 0.035 (0,89) 0.028 (0,71) 0.022 (0,54) 0.050 (1,27) 4040140 / D 10/96 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a metal lid. The terminals are gold plated. Falls within JEDEC MS-004 MS-004 POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 1 MECHANICAL MPDI002C MPDI002C ­ JANUARY 1995 ­ REVISED DECEMBER 20002 N (R-PDIP-T*) PLASTIC DUAL-IN-LINE PACKAGE 16 PINS SHOWN PINS * 14 16 18 20 A MAX 0.775 (19,69) 0.775 (19,69) 0.920 (23,37) 1.060 (26,92) A MIN 0.745 (18,92) 0.745 (18,92) 0.850 (21,59) 0.940 (23,88) MS-100 MS-100 VARIATION AA BB AC DIM A 16 9 0.260 (6,60) 0.240 (6,10) 1 C AD 8 0.070 (1,78) 0.045 (1,14) 0.045 (1,14) 0.030 (0,76) D D 0.325 (8,26) 0.300 (7,62) 0.020 (0,51) MIN 0.015 (0,38) Gauge Plane 0.200 (5,08) MAX Seating Plane 0.010 (0,25) NOM 0.125 (3,18) MIN 0.100 (2,54) 0.430 (10,92) MAX 0.021 (0,53) 0.015 (0,38) 0.010 (0,25) M 14/18 PIN ONLY 20 pin vendor option D 4040049/E 4040049/E 12/2002 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-001 MS-001, except 18 and 20 pin minimum body lrngth (Dim A). D. The 20 pin end lead shoulder width is a vendor option, either half or full width. POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 1 MECHANICAL DATA MSOI003E MSOI003E ­ JANUARY 1995 ­ REVISED SEPTEMBER 2001 DW (R-PDSO-G*) PLASTIC SMALL-OUTLINE PACKAGE 16 PINS SHOWN 0.020 (0,51) 0.014 (0,35) 9 0.050 (1,27) 16 0.010 (0,25) 0.419 (10,65) 0.400 (10,15) 0.010 (0,25) NOM 0.299 (7,59) 0.291 (7,39) Gage Plane 0.010 (0,25) 1 8 0°­ 8° 0.050 (1,27) 0.016 (0,40) A Seating Plane 0.104 (2,65) MAX 0.012 (0,30) 0.004 (0,10) PINS * 0.004 (0,10) 16 18 20 24 28 A MAX 0.410 (10,41) 0.462 (11,73) 0.510 (12,95) 0.610 (15,49) 0.710 (18,03) A MIN 0.400 (10,16) 0.453 (11,51) 0.500 (12,70) 0.600 (15,24) 0.700 (17,78) DIM 4040000/E 4040000/E 08/01 NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). Falls within JEDEC MS-013 MS-013 POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 1 MECHANICAL DATA MTSS001C MTSS001C ­ JANUARY 1995 ­ REVISED FEBRUARY 1999 PW (R-PDSO-G*) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°­ 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS * 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. 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