SN54HCT00 SN74HCT00 SCLS062D SN74HCT00N SN74HCT00D SN74HCT00DR SN74HCT00DT - Datasheet Archive

 

QUADRUPLE 2-INPUT POSITIVE-NAND GATES SCLS062D ­ NOVEMBER 1988 ­ REVISED AUGUST 2003 D D D Operating Voltage Range of 4.5

 

SN54HCT00 SN54HCT00, SN74HCT00 SN74HCT00 QUADRUPLE 2-INPUT POSITIVE-NAND GATES SCLS062D SCLS062D ­ NOVEMBER 1988 ­ REVISED AUGUST 2003 D D D Operating Voltage Range of 4.5 V to 5.5 V Outputs Can Drive Up To 10 LSTTL Loads Low Power Consumption, 20-µA Max ICC D D D D Typical tpd = 10 ns ±4-mA Output Drive at 5 V Low Input Current of 1 µA Max Inputs Are TTL-Voltage Compatible SN54HCT00 SN54HCT00 . . . J OR W PACKAGE SN74HCT00 SN74HCT00 . . . D, DB, N, NS, OR PW PACKAGE (TOP VIEW) 1 14 2 13 3 12 4 11 5 10 6 9 7 8 1B 1A NC VCC 4B VCC 4B 4A 4Y 3B 3A 3Y 1Y NC 2A NC 2B 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 4A NC 4Y NC 3B 2Y GND NC 3Y 3A 1A 1B 1Y 2A 2B 2Y GND SN54HCT00 SN54HCT00 . . . FK PACKAGE (TOP VIEW) NC ­ No internal connection description/ordering information These devices contain four independent 2-input NAND gates. They perform the Boolean function Y = A · B or Y = A + B in positive logic. ORDERING INFORMATION PACKAGE TA PDIP ­ N ORDERABLE PART NUMBER TOP-SIDE MARKING Tube of 25 SN74HCT00N SN74HCT00N Tube of 50 SN74HCT00D SN74HCT00D Reel of 2500 SN74HCT00DR SN74HCT00DR Reel of 250 SN74HCT00DT SN74HCT00DT SOP ­ NS Reel of 2000 SN74HCT00NSR SN74HCT00NSR HCT00 HCT00 SSOP ­ DB Reel of 2000 SN74HCT00DBR SN74HCT00DBR HT00 Tube of 90 SN74HCT00PW SN74HCT00PW Reel of 2000 SN74HCT00PWR SN74HCT00PWR Reel of 250 SN74HCT00PWT SN74HCT00PWT CDIP ­ J Tube of 25 SNJ54HCT00J SNJ54HCT00J SNJ54HCT00J SNJ54HCT00J CFP ­ W Tube of 150 SNJ54HCT00W SNJ54HCT00W SNJ54HCT00W SNJ54HCT00W LCCC ­ FK Tube of 55 SNJ54HCT00FK SNJ54HCT00FK SOIC ­ D ­40°C 85°C ­40 C to 85 C TSSOP ­ PW ­55°C 125°C ­55 C to 125 C SN74HCT00N SN74HCT00N HCT00 HCT00 HT00 SNJ54HCT00FK SNJ54HCT00FK Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2003, Texas Instruments Incorporated UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 1 SN54HCT00 SN54HCT00, SN74HCT00 SN74HCT00 QUADRUPLE 2-INPUT POSITIVE-NAND GATES SCLS062D SCLS062D ­ NOVEMBER 1988 ­ REVISED AUGUST 2003 FUNCTION TABLE (each gate) INPUTS OUTPUT Y A B H H L L X H X L H logic diagram (positive logic) A Y B absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ­0.5 V to 7 V Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Package thermal impedance, JA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ­65°C to 150°C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 3) SN54HCT00 SN54HCT00 SN74HCT00 SN74HCT00 MIN NOM MAX MIN NOM MAX 4.5 5 5.5 4.5 5 5.5 VCC VIH Supply voltage VIL VI Low-level input voltage Input voltage 0 VO t/v Output voltage 0 High-level input voltage VCC = 4.5 V to 5.5 V VCC = 4.5 V to 5.5 V 2 2 0.8 Input transition rise/fall time VCC VCC 500 UNIT V V 0.8 0 0 V VCC VCC V 500 ns V TA Operating free-air temperature ­55 125 ­40 85 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004 SCBA004. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 2 POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 SN54HCT00 SN54HCT00, SN74HCT00 SN74HCT00 QUADRUPLE 2-INPUT POSITIVE-NAND GATES SCLS062D SCLS062D ­ NOVEMBER 1988 ­ REVISED AUGUST 2003 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC VOH VI = VIH or VIL IOH = ­20 µA IOH = ­4 mA 4.5 V VOL VI = VIH or VIL IOL = 20 µA IOL = 4 mA 4.5 V II ICC VI = VCC or 0 VI = VCC or 0, MIN ICC MIN MAX SN74HCT00 SN74HCT00 MIN 4.4 4.499 4.4 3.7 MAX 4.4 4.3 3.84 UNIT V 0.001 0.1 0.1 0.1 0.17 0.26 0.4 0.33 ±0.1 ±100 ±1000 ±1000 nA 2 40 20 µA 1.4 2.4 3 2.9 mA 3 10 10 10 pF 5.5 V 5.5 V 4.5 V to 5.5 V Ci SN54HCT00 SN54HCT00 3.98 5.5 V IO = 0 One input at 0.5 V or 2.4 V, Other inputs at 0 or VCC TA = 25°C TYP MAX V This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than 0 V or VCC. switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) tpd A or B Y tt Y VCC MIN TA = 25°C TYP MAX SN54HCT00 SN54HCT00 MIN MAX SN74HCT00 SN74HCT00 MIN MAX 4.5 V 11 20 30 25 5.5 V 10 18 27 22 4.5 V 9 15 22 19 5.5 V 8 14 20 17 UNIT ns ns operating characteristics, TA = 25°C PARAMETER Cpd TEST CONDITIONS Power dissipation capacitance per gate No load TYP 20 UNIT pF PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 3 SN54HCT00 SN54HCT00, SN74HCT00 SN74HCT00 QUADRUPLE 2-INPUT POSITIVE-NAND GATES SCLS062D SCLS062D ­ NOVEMBER 1988 ­ REVISED AUGUST 2003 PARAMETER MEASUREMENT INFORMATION From Output Under Test 3V Test Point Input 1.3 V 1.3 V 0V CL = 50 pF (see Note A) tPLH In-Phase Output LOAD CIRCUIT 1.3 V 10% tPHL 90% 90% tr Input 1.3 V 0.3 V 2.7 V tPHL 3V 2.7 V 1.3 V 0.3 V 0 V tr Out-of-Phase Output 90% tf VOLTAGE WAVEFORM INPUT RISE AND FALL TIMES VOH 1.3 V 10% V OL tf tPLH 1.3 V 10% tf 1.3 V 10% 90% VOH VOL tr VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT RISE AND FALL TIMES NOTES: A. CL includes probe and test-fixture capacitance. B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO = 50 , tr = 6 ns, tf = 6 ns. C. The outputs are measured one at a time with one input transition per measurement. D. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms 4 POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 MECHANICAL DATA MTSS001C MTSS001C ­ JANUARY 1995 ­ REVISED FEBRUARY 1999 PW (R-PDSO-G*) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°­ 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS * 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. 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