SN74HC86Q1 SCLS587B AEC-Q100 SN74HC86IDRQ1 HC86I SN74HC86IPWRQ1 SN74HC86QDRQ1

QUADRUPLE 2INPUT EXCLUSIVEOR GATE SCLS587B - JUNE 2004 - SEPTEMBER 2004 D Qualification in Accordance With D D D D D D D D D OR

SN74HC86Q1 SN74HC86Q1 QUADRUPLE 2INPUT EXCLUSIVEOR GATE SCLS587B SCLS587B - JUNE 2004 - SEPTEMBER 2004 D Qualification in Accordance With D D D D D D D D D OR PW PACKAGE (TOP VIEW) AEC-Q100 AEC-Q100 Qualified for Automotive Applications Customer-Specific Configuration Control Can Be Supported Along With Major-Change Approval Wide Operating Voltage Range of 2 V to 6 V Outputs Can Drive Up To 10 LSTTL Loads Low Power Consumption, 20-µA Max ICC ±4-mA Output Drive at 5 V Low Input Current of 1 µA Max True Logic 1A 1B 1Y 2A 2B 2Y GND 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4B 4A 4Y 3B 3A 3Y Contact factory for details. Q100 qualification data available on request. description/ordering information This device contains four independent 2-input exclusive-OR gates. They perform the Boolean function Y = A B or Y = AB + AB in positive logic. A common application is as a true/ complement element. If one of the inputs is low, the other input is reproduced in true form at the output. If one of the inputs is high, the signal on the other input is reproduced inverted at the output. ORDERING INFORMATION -40°C to 85°C -40°C to 125°C ORDERABLE PART NUMBER PACKAGE TA TOP-SIDE MARKING SOIC - D Reel of 2500 SN74HC86IDRQ1 SN74HC86IDRQ1 HC86I HC86I TSSOP - PW Reel of 2000 SN74HC86IPWRQ1 SN74HC86IPWRQ1 HC86I HC86I SOIC - D Reel of 2500 SN74HC86QDRQ1 SN74HC86QDRQ1 HC86Q HC86Q TSSOP - PW Reel of 2000 SN74HC86QPWRQ1 SN74HC86QPWRQ1 HC86Q HC86Q Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE (each gate) INPUTS A B OUTPUT Y L L L L H H H L H H H L Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2004, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 1 SN74HC86Q1 SN74HC86Q1 QUADRUPLE 2INPUT EXCLUSIVEOR GATE SCLS587B SCLS587B - JUNE 2004 - SEPTEMBER 2004 exclusive-OR logic An exclusive-OR gate has many applications, some of which can be represented better by alternative logic symbols. Exclusive OR =1 These are five equivalent exclusive-OR symbols valid for an 'HC86 gate in positive logic; negation may be shown at any two ports. Logic Identity Element Even-Parity Element = 2k The output is active (low) if all inputs stand at the same logic level (i.e., A = B). The output is active (low) if an even number of inputs (i.e., 0 or 2) are active. Odd-Parity Element 2k + 1 The output is active (high) if an odd number of inputs (i.e., only 1 of the 2) are active. absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Package thermal impedance, JA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to 150°C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. 2 POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 SN74HC86Q1 SN74HC86Q1 QUADRUPLE 2INPUT EXCLUSIVEOR GATE SCLS587B SCLS587B - JUNE 2004 - SEPTEMBER 2004 recommended operating conditions (see Note 3) MIN VCC VIH 2 VCC = 2 V VCC = 4.5 V 5 6 3.15 V 0.5 1.35 0 Output voltage VCC VCC 0 VCC = 2 V VCC = 4.5 V Input transition rise/fall time V 1.8 Input voltage t/v V 4.2 VCC = 4.5 V VCC = 6 V Low-level input voltage UNIT 1.5 VCC = 6 V VCC = 2 V VI VO MAX Supply voltage High-level input voltage VIL NOM V V 1000 500 ns VCC = 6 V 400 TA Operating free-air temperature -40 125 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004 SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) TEST CONDITIONS VCC TA = -405C -405C TO 1255C 1255C TA = -405C -405C TO 855C MIN PARAMETER MIN MAX 2V VI = VIH or VIL IOH = -4 mA IOH = -5.2 mA 1.9 4.5 V 4.4 4.4 6V IOH = -20 µA VOH 1.9 5.9 5.9 4.5 V 3.7 3.84 6V 5.2 UNIT MAX V 5.34 2V 4.5 V 0.1 0.1 6V 0.1 0.1 IOL = 4 mA IOL = 5.2 mA II ICC 0.1 IOL = 20 µA VOL 0.1 4.5 V 0.4 0.33 6V 0.4 0.33 6V ±1000 ±1000 nA 6V 40 20 µA 2 V to 6 V 10 10 pF VI = VIH or VIL VI = VCC or 0 VI = VCC or 0, IO = 0 Ci POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 V 3 SN74HC86Q1 SN74HC86Q1 QUADRUPLE 2INPUT EXCLUSIVEOR GATE SCLS587B SCLS587B - JUNE 2004 - SEPTEMBER 2004 switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) FROM (INPUT) PARAMETER VCC TA = -405C -405C TO 1255C 1255C TA = -405C -405C TO 855C MIN TO (OUTPUT) MIN MAX UNIT MAX 2V 4.5 V Y 21 110 95 22 19 6V tt 25 25 4.5 V Y 30 2V A or B 125 6V tpd 150 19 16 ns ns operating characteristics, TA = 25°C PARAMETER Cpd TEST CONDITIONS Power dissipation capacitance per gate No load TYP UNIT 35 pF PARAMETER MEASUREMENT INFORMATION From Output Under Test Test Point Input VCC 50% 50% 0V CL = 50 pF (see Note A) tPLH In-Phase Output LOAD CIRCUIT 50% 10% tPHL 90% 90% tr Input 50% 10% 90% 90% tr tPHL VCC 50% 10% 0 V Out-of-Phase Output 90% tf VOH 50% 10% VOL tf tPLH 50% 10% tf 50% 10% 90% VOH VOL tr VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES VOLTAGE WAVEFORM INPUT RISE AND FALL TIMES NOTES: A. CL includes probe and test-fixture capacitance. B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO = 50 , tr = 6 ns, tf = 6 ns. C. The outputs are measured one at a time, with one input transition per measurement. D. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms 4 POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 MECHANICAL DATA MTSS001C MTSS001C JANUARY 1995 REVISED FEBRUARY 1999 PW (R-PDSO-G*) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0° 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS * 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. 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