SN54HC595 SN74HC595 SCLS041G HC595 SN74HC595N SN74HC595D SN74HC595DR - Datasheet Archive

 

8BIT SHIFT REGISTERS WITH 3STATE OUTPUT REGISTERS SCLS041G - DECEMBER 1982 - REVISED FEBRUARY 2004 D 8-Bit Serial-In,

 

SN54HC595 SN54HC595, SN74HC595 SN74HC595 8BIT SHIFT REGISTERS WITH 3STATE OUTPUT REGISTERS SCLS041G SCLS041G - DECEMBER 1982 - REVISED FEBRUARY 2004 D 8-Bit Serial-In, Parallel-Out Shift D Wide Operating Voltage Range of 2 V to 6 V D High-Current 3-State Outputs Can Drive Up D D D D D SN54HC595 SN54HC595 . . . J OR W PACKAGE SN74HC595 SN74HC595 . . . D, DB, DW, N, OR NS PACKAGE (TOP VIEW) QB QC QD QE QF QG QH GND To 15 LSTTL Loads Low Power Consumption, 80-µA Max ICC Typical tpd = 13 ns ±6-mA Output Drive at 5 V Low Input Current of 1 µA Max Shift Register Has Direct Clear 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC QA SER OE RCLK SRCLK SRCLR QH description/ordering information The 'HC595 HC595 devices contain an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. The storage register has parallel 3-state outputs. Separate clocks are provided for both the shift and storage register. The shift register has a direct overriding clear (SRCLR) input, serial (SER) input, and serial outputs for cascading. When the output-enable (OE) input is high, the outputs are in the high-impedance state. QC QB NC VCC QA SN54HC595 SN54HC595 . . . FK PACKAGE (TOP VIEW) 5 17 6 16 7 15 8 14 9 10 11 12 13 SER OE NC RCLK SRCLK SRCLR 3 2 1 20 19 18 QH Both the shift register clock (SRCLK) and storage register clock (RCLK) are positive-edge triggered. If both clocks are connected together, the shift register always is one clock pulse ahead of the storage register. 4 GND NC Q H QD QE NC QF QG NC - No internal connection ORDERING INFORMATION ORDERABLE PART NUMBER PACKAGE TA PDIP - N TOP-SIDE MARKING Tube of 25 SN74HC595N SN74HC595N Tube of 40 SN74HC595D SN74HC595D Reel of 2500 SN74HC595DR SN74HC595DR Reel of 250 SN74HC595DT SN74HC595DT Tube of 40 SN74HC595DW SN74HC595DW Reel of 2000 SN74HC595DWR SN74HC595DWR SOP - NS Reel of 2000 SN74HC595NSR SN74HC595NSR HC595 HC595 SSOP - DB Reel of 2000 SN74HC595DBR SN74HC595DBR HC595 HC595 CDIP - J Tube of 25 SNJ54HC595J SNJ54HC595J SNJ54HC595J SNJ54HC595J CFP - W Tube of 150 SNJ54HC595W SNJ54HC595W SNJ54HC595W SNJ54HC595W LCCC - FK Tube of 55 SNJ54HC595FK SNJ54HC595FK SOIC - D -40°C to 85°C SOIC - DW -55 C 125°C -55°C to 125 C SN74HC595N SN74HC595N HC595 HC595 HC595 HC595 SNJ54HC595FK SNJ54HC595FK Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2004, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. On products compliant to MILPRF38535 MILPRF38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 1 SN54HC595 SN54HC595, SN74HC595 SN74HC595 8BIT SHIFT REGISTERS WITH 3STATE OUTPUT REGISTERS SCLS041G SCLS041G - DECEMBER 1982 - REVISED FEBRUARY 2004 FUNCTION TABLE INPUTS SER X X X X X X L SRCLR FUNCTION RCLK OE X X H X X L Outputs QA-QH are disabled. Outputs QA-QH are enabled. L X X Shift register is cleared. H X X First stage of the shift register goes low. Other stages store the data of previous stage, respectively. H H X X First stage of the shift register goes high. Other stages store the data of previous stage, respectively. X 2 SRCLK X X X Shift-register data is stored in the storage register. POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 SN54HC595 SN54HC595, SN74HC595 SN74HC595 8BIT SHIFT REGISTERS WITH 3STATE OUTPUT REGISTERS SCLS041G SCLS041G - DECEMBER 1982 - REVISED FEBRUARY 2004 logic diagram (positive logic) OE RCLK SRCLR SRCLK SER 13 12 10 11 14 1D C1 R 3R C3 3S 15 2S 2R C2 R 3R C3 3S 1 2S 2R C2 R 3R C3 3S 2 2S 2R C2 R 3R C3 3S 3 2S 2R C2 R 3R C3 3S 4 2S 2R C2 R 3R C3 3S 5 2S 2R C2 R 3R C3 3S 6 2S 2R C2 R 3R C3 3S 7 9 QA QB QC QD QE QF QG QH QH Pin numbers shown are for the D, DB, DW, J, N, NS, and W packages. POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 3 SN54HC595 SN54HC595, SN74HC595 SN74HC595 8BIT SHIFT REGISTERS WITH 3STATE OUTPUT REGISTERS SCLS041G SCLS041G - DECEMBER 1982 - REVISED FEBRUARY 2004 timing diagram SRCLK SER RCLK SRCLR OE ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ QA QB QC QD QE QF QG QH QH' 4 ÎÎÎÎ ÎÎÎÎ NOTE: implies that the output is in 3-State mode. POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 SN54HC595 SN54HC595, SN74HC595 SN74HC595 8BIT SHIFT REGISTERS WITH 3STATE OUTPUT REGISTERS SCLS041G SCLS041G - DECEMBER 1982 - REVISED FEBRUARY 2004 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±35 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±70 mA Package thermal impedance, JA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82°C/W DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to 150°C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 3) SN54HC595 SN54HC595 SN74HC595 SN74HC595 MIN VCC VIH High-level input voltage VCC = 2 V VCC = 4.5 V VCC = 6 V VCC = 2 V VIL VI VO t/v Low-level input voltage 5 6 NOM MAX 2 5 6 3.15 3.15 4.2 UNIT V 1.5 4.2 V 0.5 0 VCC = 6 V 1.35 1.8 VCC = 2 V VCC = 4.5 V 0.5 1.35 0 Output voltage MIN 1.5 VCC = 4.5 V VCC = 6 V Input voltage Input transition rise/fall time MAX 2 Supply voltage NOM 1.8 VCC VCC 0 0 VCC VCC 1000 500 400 V V 1000 500 V 400 ns TA Operating free-air temperature -55 125 -40 85 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004 SCBA004. If this device is used in the threshold region (from VILmax = 0.5 V to VIHmin = 1.5 V), there is a potential to go into the wrong state from induced grounding, causing double clocking. Operating with the inputs at tt = 1000 ns and VCC = 2 V does not damage the device; however, functionally, the CLK inputs are not ensured while in the shift, count, or toggle operating modes. POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 5 SN54HC595 SN54HC595, SN74HC595 SN74HC595 8BIT SHIFT REGISTERS WITH 3STATE OUTPUT REGISTERS SCLS041G SCLS041G - DECEMBER 1982 - REVISED FEBRUARY 2004 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TA = 25°C TYP MAX SN54HC595 SN54HC595 SN74HC595 SN74HC595 VCC MIN 2V 1.9 1.998 1.9 1.9 IOH = -20 µA 4.5 V 4.4 4.499 4.4 4.4 6V VOH TEST CONDITIONS 5.9 5.999 5.9 5.9 3.98 4.3 3.7 3.84 3.98 4.3 3.7 3.84 5.48 5.8 5.2 5.34 VI = VIH or VIL QH, IOH = -4 mA QA-QH, IOH = -6 mA QH, IOH = -5.2 mA QA-QH, IOH = -7.8 mA 4.5 V 6V 5.48 5.8 MIN MAX 5.2 MIN MAX V 5.34 2V VOL VI = VIH or VIL QH, IOL = 4 mA QA-QH, IOL = 6 mA QH, IOL = 5.2 mA QA-QH, IOL = 7.8 mA 0.002 0.1 0.1 0.1 4.5 V 0.001 0.1 0.1 0.1 6V IOL = 20 µA UNIT 0.001 0.1 0.1 0.1 0.17 0.26 0.4 0.33 0.17 0.26 0.4 0.33 0.15 0.26 0.4 0.33 0.15 0.26 0.4 0.33 4.5 V 6V V II IOZ VI = VCC or 0 VO = VCC or 0, 6V ±0.1 ±100 ±1000 ±1000 nA QA-QH 6V ±0.01 ±0.5 ±10 ±5 µA ICC VI = VCC or 0, IO = 0 6V 8 160 80 µA 10 10 10 pF Ci 6 2V to 6 V POST OFFICE BOX 655303 3 · DALLAS, TEXAS 75265 SN54HC595 SN54HC595, SN74HC595 SN74HC595 8BIT SHIFT REGISTERS WITH 3STATE OUTPUT REGISTERS SCLS041G SCLS041G - DECEMBER 1982 - REVISED FEBRUARY 2004 timing requirements over recommended operating free-air temperature range (unless otherwise noted) VCC TA = 25°C MIN MAX SN54HC595 SN54HC595 MIN MAX SN74HC595 SN74HC595 MIN MAX 2V Clock frequency 6 4.2 5 4.5 V 31 21 25 6V fclock 36 25 29 2V tw 20 14 20 17 80 120 100 16 24 20 6V 25 21 75 113 94 4.5 V 15 23 19 13 19 16 50 75 65 4.5 V 10 15 13 9 13 11 50 75 60 4.5 V 10 15 12 6V 9 13 11 2V 0 0 0 4.5 V 0 0 0 6V Hold time, SER after SRCLK SRCLK 17 2V th 25 6V SRCLR high (inactive) before SRCLK 30 2V SRCLR low before RCLK 20 6V Setup time 125 4.5 V 0 0 ns 17 150 2V tsu 20 100 6V SRCLK before RCLK 14 2V SER before SRCLK MHz 100 24 4.5 V SRCLR low 120 16 2V Pulse duration 80 4.5 V 6V SRCLK or RCLK high or low UNIT 0 ns ns This setup time allows the storage register to receive stable data from the shift register. The clocks can be tied together, in which case the shift register is one clock pulse ahead of the storage register. POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 7 SN54HC595 SN54HC595, SN74HC595 SN74HC595 8BIT SHIFT REGISTERS WITH 3STATE OUTPUT REGISTERS SCLS041G SCLS041G - DECEMBER 1982 - REVISED FEBRUARY 2004 switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) VCC MIN TA = 25°C TYP MAX SN54HC595 SN54HC595 MIN MAX SN74HC595 SN74HC595 MIN 2V 6 26 4.2 31 38 21 25 6V 36 42 25 29 MHz 2V OE QA-QH 27 41 34 50 150 225 187 4.5 V 17 30 45 37 14 26 38 32 51 175 261 219 4.5 V 18 35 52 44 15 30 44 37 40 150 225 187 4.5 V 15 30 45 37 6V ten QH H 40 14 2V SRCLR 200 48 6V tPHL QA-QH 240 32 2V RCLK 160 17 6V tpd 50 2V QH H 4.5 V 6V SRCLK 13 26 38 32 2V QH H 20 34 51 28 60 90 8 12 18 15 6 10 15 13 28 75 110 95 4.5 V 8 15 22 19 6 13 19 ns 75 4.5 V ns 43 6V tt 50 ns 250 60 2V QA-QH 300 40 6V QA-QH 200 23 2V OE 42 4.5 V 6V tdis UNIT 5 4.5 V fmax MAX 16 ns ns switching characteristics over recommended operating free-air temperature range, CL = 150 pF (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) VCC MIN TA = 25°C TYP MAX SN54HC595 SN54HC595 MIN MAX SN74HC595 SN74HC595 MIN MAX 2V RCLK QA-QH 200 300 250 4.5 V 22 40 60 50 6V tpd 60 19 34 51 43 2V OE QA-QH 70 200 298 23 40 60 50 19 34 51 43 2V QA-QH 45 210 315 17 42 63 53 13 36 53 ns 265 4.5 V 6V tt ns 250 4.5 V 6V ten UNIT 45 ns operating characteristics, TA = 25°C PARAMETER Cpd 8 TEST CONDITIONS POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 UNIT No load Power dissipation capacitance TYP 400 pF SN54HC595 SN54HC595, SN74HC595 SN74HC595 8BIT SHIFT REGISTERS WITH 3STATE OUTPUT REGISTERS SCLS041G SCLS041G - DECEMBER 1982 - REVISED FEBRUARY 2004 PARAMETER MEASUREMENT INFORMATION VCC S1 Test Point From Output Under Test PARAMETER RL CL (see Note A) tPZH ten tPHZ tPLZ tpd or tt Data Input VCC 50% 10% 50% VCC 0V In-Phase Output 50% 10% tPHL 90% 90% tr tPHL Out-ofPhase Output 90% tf Open Open VCC th 90% 90% VCC 50% 10% 0 V tf 50% 10% Output Control (Low-Level Enabling) VCC 50% 50% 0V tPZL VOH 50% 10% V OL tf Output Waveform 1 (See Note B) tPLZ 90% VOH VOL Output Waveform 2 (See Note B) VCC VCC 50% 10% tPZH tPLH 50% 10% Open VOLTAGE WAVEFORMS SETUP AND HOLD AND INPUT RISE AND FALL TIMES 50% tPLH Closed tr VOLTAGE WAVEFORMS PULSE DURATIONS 50% Open 0V 0V Input Open tsu 0V 50% Closed 50% 50% tw Low-Level Pulse Closed 50 pF or 150 pF - Reference Input VCC 50% Open 50 pF LOAD CIRCUIT High-Level Pulse S2 Closed 1 k S1 50 pF or 150 pF 1 k tPZL tdis S2 CL RL VOL tPHZ 50% 90% VOH 0 V tr VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS NOTES: A. CL includes probe and test-fixture capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO = 50 , tr = 6 ns, tf = 6 ns. D. For clock inputs, fmax is measured when the input duty cycle is 50%. E. The outputs are measured one at a time, with one input transition per measurement. F. tPLZ and tPHZ are the same as tdis. G. tPZL and tPZH are the same as ten. H. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 9 PACKAGE OPTION ADDENDUM www.ti.com 12-Jan-2006 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty Lead/Ball Finish MSL Peak Temp (3) 5962-86816012A ACTIVE LCCC FK 20 1 TBD Call TI N / A for Pkg Type 5962-8681601EA 5962-8681601EA ACTIVE CDIP J 16 1 TBD Call TI N / A for Pkg Type 5962-8681601VEA 5962-8681601VEA ACTIVE CDIP J 16 1 TBD Call TI N / A for Pkg Type 5962-8681601VFA 5962-8681601VFA ACTIVE CFP W 16 1 TBD Call TI N / A for Pkg Type SN54HC595J SN54HC595J ACTIVE CDIP J 16 1 TBD Call TI N / A for Pkg Type SN74HC595D SN74HC595D ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC595DBR SN74HC595DBR ACTIVE SSOP DB 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC595DBRE4 SN74HC595DBRE4 ACTIVE SSOP DB 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC595DE4 SN74HC595DE4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC595DG4 SN74HC595DG4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1YEAR SN74HC595DR SN74HC595DR ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC595DRE4 SN74HC595DRE4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC595DRG4 SN74HC595DRG4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1YEAR SN74HC595DT SN74HC595DT ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC595DTE4 SN74HC595DTE4 ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC595DW SN74HC595DW ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC595DWE4 SN74HC595DWE4 ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC595DWR SN74HC595DWR ACTIVE SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC595DWRE4 SN74HC595DWRE4 ACTIVE SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC595N SN74HC595N ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type SN74HC595NE4 SN74HC595NE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type SN74HC595NSR SN74HC595NSR ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC595NSRE4 SN74HC595NSRE4 ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC595PW SN74HC595PW ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC595PWE4 SN74HC595PWE4 ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC595PWR SN74HC595PWR ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC595PWRE4 SN74HC595PWRE4 ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 12-Jan-2006 Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SNJ54HC595FK SNJ54HC595FK ACTIVE LCCC FK 20 1 TBD Call TI N / A for Pkg Type SNJ54HC595J SNJ54HC595J ACTIVE CDIP J 16 1 TBD Call TI N / A for Pkg Type SNJ54HC595W SNJ54HC595W OBSOLETE TBD Call TI Call TI 16 Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 MECHANICAL DATA MLCC006B MLCC006B ­ OCTOBER 1996 FK (S-CQCC-N*) LEADLESS CERAMIC CHIP CARRIER 28 TERMINAL SHOWN 18 17 16 15 14 13 NO. OF TERMINALS * 12 A B 11 20 MAX MIN MAX 20 0.342 (8,69) 0.358 (9,09) 0.307 (7,80) 0.358 (9,09) 28 19 MIN 0.442 (11,23) 0.458 (11,63) 0.406 (10,31) 0.458 (11,63) 10 21 9 22 8 44 0.640 (16,26) 0.660 (16,76) 0.495 (12,58) 0.560 (14,22) 23 7 52 0.739 (18,78) 0.761 (19,32) 0.495 (12,58) 0.560 (14,22) 24 6 68 0.938 (23,83) 0.962 (24,43) 0.850 (21,6) 0.858 (21,8) 84 1.141 (28,99) 1.165 (29,59) 1.047 (26,6) 1.063 (27,0) B SQ A SQ 25 5 26 27 28 1 2 3 4 0.080 (2,03) 0.064 (1,63) 0.020 (0,51) 0.010 (0,25) 0.020 (0,51) 0.010 (0,25) 0.055 (1,40) 0.045 (1,14) 0.045 (1,14) 0.035 (0,89) 0.045 (1,14) 0.035 (0,89) 0.028 (0,71) 0.022 (0,54) 0.050 (1,27) 4040140 / D 10/96 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a metal lid. The terminals are gold plated. Falls within JEDEC MS-004 MS-004 POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 MECHANICAL DATA MSSO002E MSSO002E ­ JANUARY 1995 ­ REVISED DECEMBER 2001 DB (R-PDSO-G*) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°­8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS * 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-150 MO-150 POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 MECHANICAL DATA MTSS001C MTSS001C ­ JANUARY 1995 ­ REVISED FEBRUARY 1999 PW (R-PDSO-G*) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°­ 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS * 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. 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