SN74HC4066 SCLS325F SN74HC4066N SN74HC4066D SN74HC4066DR SN74HC4066NSR HC4066 - Datasheet Archive

 

QUADRUPLE BILATERAL ANALOG SWITCH SCLS325F ­ MARCH 1996 ­ REVISED DECEMBER 2002 D D D D D D D D D D, DB, N, NS, OR PW

 

SN74HC4066 SN74HC4066 QUADRUPLE BILATERAL ANALOG SWITCH SCLS325F SCLS325F ­ MARCH 1996 ­ REVISED DECEMBER 2002 D D D D D D D D D D, DB, N, NS, OR PW PACKAGE (TOP VIEW) Wide Operating Voltage Range of 2 V to 6 V Typical Switch Enable Time of 18 ns Low Power Consumption, 20-µA Max ICC Low Input Current of 1 µA Max High Degree of Linearity High On-Off Output-Voltage Ratio Low Crosstalk Between Switches Low On-State Impedance . . . 50- TYP at VCC = 6 V Individual Switch Controls 1A 1B 2B 2A 2C 3C GND 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 1C 4C 4A 4B 3B 3A description/ordering information The SN74HC4066 SN74HC4066 is a silicon-gate CMOS quadruple analog switch designed to handle both analog and digital signals. Each switch permits signals with amplitudes of up to 6 V (peak) to be transmitted in either direction. Each switch section has its own enable input control (C). A high-level voltage applied to C turns on the associated switch section. Applications include signal gating, chopping, modulation or demodulation (modem), and signal multiplexing for analog-to-digital and digital-to-analog conversion systems. ORDERING INFORMATION ORDERABLE PART NUMBER PACKAGE TA PDIP ­ N TOP-SIDE MARKING Tube SN74HC4066N SN74HC4066N Tube SN74HC4066D SN74HC4066D Tape and reel SN74HC4066DR SN74HC4066DR SOP ­ NS Tape and reel SN74HC4066NSR SN74HC4066NSR HC4066 HC4066 SSOP ­ DB Tape and reel SN74HC4066DBR SN74HC4066DBR HC4066 HC4066 Tube SN74HC4066PW SN74HC4066PW Tape and reel SN74HC4066PWR SN74HC4066PWR SOIC ­ D ­40°C to 85°C 40 C 85 C TSSOP ­ PW SN74HC4066N SN74HC4066N HC4066 HC4066 HC4066 HC4066 Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE (each switch) INPUT CONTROL (C) SWITCH L OFF H ON Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2002, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 1 SN74HC4066 SN74HC4066 QUADRUPLE BILATERAL ANALOG SWITCH SCLS325F SCLS325F ­ MARCH 1996 ­ REVISED DECEMBER 2002 logic diagram, each switch (positive logic) A VCC VCC B C One of Four Switches absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ­0.5 V to 7 V Control-input diode current, II (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA I/O port diode current, II (VI < 0 or VI/O > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA On-state switch current (VI/O = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Package thermal impedance, JA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ­65°C to 150°C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltages are with respect to ground unless otherwise specified. 2. The package thermal impedance is calculated in accordance with JESD 51-7. 2 POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 SN74HC4066 SN74HC4066 QUADRUPLE BILATERAL ANALOG SWITCH SCLS325F SCLS325F ­ MARCH 1996 ­ REVISED DECEMBER 2002 recommended operating conditions (see Note 3) VCC VI/O VIH Supply voltage MIN 2 I/O port voltage 0 t/v 6 V V VCC VCC V 0 0.3 0 0.9 0 1.2 3.15 VCC = 4.5 V VCC = 6 V VCC = 2 V Low-level input voltage, control inputs Low level in ut in uts V 1000 VCC = 4.5 V VCC = 6 V In ut Input transition rise/fall time UNIT VCC VCC 1.5 VCC = 6 V VCC = 2 V VIL 5 MAX 4.2 VCC = 2 V VCC = 4.5 V High level input High-level in ut voltage, control in uts inputs NOM 500 ns 400 TA Operating free-air temperature ­40 85 °C With supply voltages at or near 2 V, the analog switch on-state resistance becomes very nonlinear. It is recommended that only digital signals be transmitted at these low supply voltages. NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004 SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) ron(p) on( ) On state On-state switch resistance Peak on-state resistance on state 1 A IT = ­1 mA, VI = 0 t VCC, to VC = VIH (see Figure 1) VI = VCC or GND VC = VIH, GND, IT = ­1 mA VC = 0 or VCC VI = VCC or 0, VO = VCC or 0, VC = VIL (see Figure 2) TA = 25_C MIN TYP MAX 150 4.5 V 50 6V 30 2V ron TEST CONDITIONS VCC 2V PARAMETER 320 4.5 V 70 6V 50 6V ±0.1 MAX UNIT 85 106 170 215 ±100 ±1000 nA 6V ±0.1 ±5 µA ±0.1 ±5 µA 2 20 µA 10 10 II Control input current Isoff Off-state switch leakage current Ison On-state switch leakage current VI = VCC or 0, VC = VIH (see Figure 3) 6V ICC Supply current VI = 0 or VCC, 6V IO = 0 A or B Ci Input Inp t capacitance Cf Feed-through capacitance A to B Co Output capacitance MIN 9 5V A or B C VI = 0 pF 0.5 5V POST OFFICE BOX 655303 3 · DALLAS, TEXAS 75265 pF 9 pF 3 SN74HC4066 SN74HC4066 QUADRUPLE BILATERAL ANALOG SWITCH SCLS325F SCLS325F ­ MARCH 1996 ­ REVISED DECEMBER 2002 switching characteristics over recommended operating free-air temperature range PARAMETER FROM (INPUT) TO (OUTPUT) A or B B or A TEST CONDITIONS VCC TA = 25_C MIN TYP MAX MIN MAX 2V tPLH, tPHL Propagation P ti delay time tPZH, tPZL Switch S it h turn-on time tPLZ, tPHZ Switch S it h turn-off time fI Control input frequency f Control feed-through feed through noise C C C C A or B A or B A or B A or B CL = 50 pF (see Figure 4) 10 60 75 4.5 V 4 12 15 UNIT 6V 3 10 13 RL = 1 k k, CL = 50 pF F (see Figure 5) 2V 70 180 225 4.5 V 21 36 45 6V 18 31 38 RL = 1 k k, CL = 50 pF F (see Figure 5) 2V 50 200 250 4.5 V 25 40 50 6V 22 34 43 2V 15 4.5 V 30 6V 30 4.5 V ns 15 CL = 15 pF, RL = 1 k, k VC = VCC or GND, VO = VCC/2 (see Figure 6) CL = 50 pF, Rin = RL = 600 , VC = VCC or GND, GND fin = 1 MHz (see Figure 7) ns ns MHz mV (rms) 6V 20 operating characteristics, VCC = 4.5 V, TA = 25°C PARAMETER Cpd TEST CONDITIONS TYP UNIT Power dissipation capacitance per gate CL = 50 pF, f = 1 MHz 45 pF Minimum through bandwidth, A to B or B to A [20 log (VO/VI)] = ­3 dB CL = 50 pF, VC = VCC RL = 600 , (see Figure 8) 30 MHz Crosstalk between any switches CL = 10 pF, fin = 1 MHz RL = 50 , (see Figure 9) 45 dB Feed through, switch off, A to B or B to A CL = 50 pF, fin = 1 MHz RL = 600 , (see Figure 10) 42 dB Amplitude distortion rate, A to B or B to A CL = 50 pF, fin = 1 kHz RL = 10 k, (see Figure 11) 0.05% Adjust the input amplitude for output = 0 dBm at f = 1 MHz. Input signal must be a sine wave. Adjust the input amplitude for input = 0 dBm at f = 1 MHz. Input signal must be a sine wave. 4 POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 SN74HC4066 SN74HC4066 QUADRUPLE BILATERAL ANALOG SWITCH SCLS325F SCLS325F ­ MARCH 1996 ­ REVISED DECEMBER 2002 PARAMETER MEASUREMENT INFORMATION VCC VC = VIH VCC VI = VCC VO (ON) GND + r on + 1.0 mA V I­O 10 ­3 W ­ V VI­O Figure 1. On-State Resistance Test Circuit VCC VC = VIL VCC A A (OFF) B GND VS = VA ­ VB CONDITION 1: VA = 0, VB = VCC CONDITION 2: VA = VCC, VB = 0 Figure 2. Off-State Switch Leakage-Current Test Circuit POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 5 SN74HC4066 SN74HC4066 QUADRUPLE BILATERAL ANALOG SWITCH SCLS325F SCLS325F ­ MARCH 1996 ­ REVISED DECEMBER 2002 PARAMETER MEASUREMENT INFORMATION VCC VC = VIH VCC A A B (ON) VCC Open GND VA = VCC TO GND Figure 3. On-State Leakage-Current Test Circuit VCC VC = VIH VCC VI VO (ON) 50 50 pF GND TEST CIRCUIT tr tf VI A or B 90% 50% 10% VCC 90% 50% 10% 0V tPLH VO B or A tPHL VOH 50% 50% VOL VOLTAGE WAVEFORMS Figure 4. Propagation Delay Time, Signal Input to Signal Output 6 POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 SN74HC4066 SN74HC4066 QUADRUPLE BILATERAL ANALOG SWITCH SCLS325F SCLS325F ­ MARCH 1996 ­ REVISED DECEMBER 2002 PARAMETER MEASUREMENT INFORMATION VCC 50 TEST VC RL VO 1 k VCC VI S2 S1 S1 S2 tPZL tPZH tPLZ tPHZ GND VCC GND VCC VCC GND VCC GND CL 50 pF GND TEST CIRCUIT VCC VCC VC 50% 50% 0V 0V tPZH tPZL VOH VOH VO 50% 50% VOL VOL (tPZL, tPZH) VCC VCC VC 50% 50% 0V 0V tPHZ tPLZ VOH VOH VO VOL 10% 90% VOL (tPLZ, tPHZ) VOLTAGE WAVEFORMS Figure 5. Switching Time (tPZL, tPLZ, tPZH, tPHZ), Control to Signal Output POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 7 SN74HC4066 SN74HC4066 QUADRUPLE BILATERAL ANALOG SWITCH SCLS325F SCLS325F ­ MARCH 1996 ­ REVISED DECEMBER 2002 PARAMETER MEASUREMENT INFORMATION VCC VCC 50 VC VC 0V VCC VO VI = VCC GND CL 15 pF RL 1 k VCC/2 Figure 6. Control-Input Frequency VCC 50 tr VC VCC VCC VI GND Rin 600 RL 600 90% 90% VC VO 10% 0V CL 50 pF tf 10% (f = 1 MHz) tr = tf = 6 ns VCC/2 VCC/2 Figure 7. Control Feed-Through Noise VCC VC = VCC 0.1 µF fin 50 VI VCC (ON) GND VI VO RL 600 CL 50 pF VCC/2 Figure 8. Minimum Through Bandwidth 8 POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 (VI = 0 dBm at f = 1 MHz) SN74HC4066 SN74HC4066 QUADRUPLE BILATERAL ANALOG SWITCH SCLS325F SCLS325F ­ MARCH 1996 ­ REVISED DECEMBER 2002 PARAMETER MEASUREMENT INFORMATION VCC VC = VCC VCC (ON) VI fin 50 0.1 µF Rin 600 VO1 GND RL 600 CL 50 pF VCC/2 VI VCC VC = GND (VI = 0 dBm at f = 1 MHz) VCC (OFF) VO2 GND Rin 600 RL 600 CL 50 pF VCC/2 Figure 9. Crosstalk Between Any Two Switches VCC VC = GND 0.1 µF 50 VCC (OFF) VI fin Rin 600 VI VO RL 600 GND VCC/2 CL 50 pF (VI = 0 dBm at f = 1 MHz) VCC/2 Figure 10. Feed Through, Switch Off VCC VC = VCC fin VI 10 µF VCC (ON) GND VO RL 10 k VI CL 50 pF (VI = 0 dBm at f = 1 kHz) VCC/2 Figure 11. Amplitude-Distortion Rate POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 9 MECHANICAL MPDI002C MPDI002C ­ JANUARY 1995 ­ REVISED DECEMBER 20002 N (R-PDIP-T*) PLASTIC DUAL-IN-LINE PACKAGE 16 PINS SHOWN PINS * 14 16 18 20 A MAX 0.775 (19,69) 0.775 (19,69) 0.920 (23,37) 1.060 (26,92) A MIN 0.745 (18,92) 0.745 (18,92) 0.850 (21,59) 0.940 (23,88) MS-100 MS-100 VARIATION AA BB AC DIM A 16 9 0.260 (6,60) 0.240 (6,10) 1 C AD 8 0.070 (1,78) 0.045 (1,14) 0.045 (1,14) 0.030 (0,76) D D 0.325 (8,26) 0.300 (7,62) 0.020 (0,51) MIN 0.015 (0,38) Gauge Plane 0.200 (5,08) MAX Seating Plane 0.010 (0,25) NOM 0.125 (3,18) MIN 0.100 (2,54) 0.430 (10,92) MAX 0.021 (0,53) 0.015 (0,38) 0.010 (0,25) M 14/18 PIN ONLY 20 pin vendor option D 4040049/E 4040049/E 12/2002 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-001 MS-001, except 18 and 20 pin minimum body lrngth (Dim A). D. The 20 pin end lead shoulder width is a vendor option, either half or full width. POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 1 MECHANICAL DATA MSOI002B MSOI002B ­ JANUARY 1995 ­ REVISED SEPTEMBER 2001 D (R-PDSO-G*) PLASTIC SMALL-OUTLINE PACKAGE 8 PINS SHOWN 0.020 (0,51) 0.014 (0,35) 0.050 (1,27) 8 0.010 (0,25) 5 0.008 (0,20) NOM 0.244 (6,20) 0.228 (5,80) 0.157 (4,00) 0.150 (3,81) Gage Plane 1 4 0.010 (0,25) 0°­ 8° A 0.044 (1,12) 0.016 (0,40) Seating Plane 0.010 (0,25) 0.004 (0,10) 0.069 (1,75) MAX PINS * 0.004 (0,10) 8 14 16 A MAX 0.197 (5,00) 0.344 (8,75) 0.394 (10,00) A MIN 0.189 (4,80) 0.337 (8,55) 0.386 (9,80) DIM 4040047/E 4040047/E 09/01 NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15). Falls within JEDEC MS-012 MS-012 POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 1 MECHANICAL DATA MSSO002E MSSO002E ­ JANUARY 1995 ­ REVISED DECEMBER 2001 DB (R-PDSO-G*) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°­8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS * 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-150 MO-150 POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 1 MECHANICAL DATA MTSS001C MTSS001C ­ JANUARY 1995 ­ REVISED FEBRUARY 1999 PW (R-PDSO-G*) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°­ 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS * 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153 MO-153 POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 1 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. 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