SN74CBTD3306C SCDS128A A114-B SN74CBTD3306CDR SN74CBTD3306CD SN74CBTD3306CPW - Datasheet Archive

 

DUAL FET BUS SWITCH WITH LEVEL SHIFTING 5V BUS SWITCH WITH 2V UNDERSHOOT PROTECTION SCDS128A - SEPTEMBER 2003 - REVISED OCTOBER

 

SN74CBTD3306C SN74CBTD3306C DUAL FET BUS SWITCH WITH LEVEL SHIFTING 5V BUS SWITCH WITH 2V UNDERSHOOT PROTECTION SCDS128A SCDS128A - SEPTEMBER 2003 - REVISED OCTOBER 2003 D Undershoot Protection for Off-Isolation on D Data I/Os Support 0 to 5-V Signaling Levels A and B Ports Up To -2 V Integrated Diode to VCC Provides 5-V Input Down To 3.3-V Output Level Shift Bidirectional Data Flow, With Near-Zero Propagation Delay Low ON-State Resistance (ron) Characteristics (ron = 3 Typical) Low Input/Output Capacitance Minimizes Loading and Signal Distortion (Cio(OFF) = 5 pF Typical) Data and Control Inputs Provide Undershoot Clamp Diodes VCC Operating Range From 4.5 V to 5.5 V (0.8-V, 1.2-V, 1.5-V, 1.8-V, 2.5-V, 3.3-V, 5-V) Control Inputs Can be Driven by TTL or 5-V/3.3-V CMOS Outputs Ioff Supports Partial-Power-Down Mode Operation Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Performance Tested Per JESD 22 - 2000-V Human-Body Model (A114-B A114-B, Class II) - 1000-V Charged-Device Model (C101) Supports Both Digital and Analog Applications: USB Interface, Memory Interleaving, Bus Isolation, Low-Distortion Signal Gating D D D D D D D D D D D D OR PW PACKAGE (TOP VIEW) 1OE 1A 1B GND 1 7 3 6 4 VCC 2OE 2B 2A 8 2 5 description/ordering information The SN74CBTD3306C SN74CBTD3306C is a high-speed TTL-compatible FET bus switch with low ON-state resistance (ron), allowing for minimal propagation delay. This device features an integrated diode in series with VCC to provide level shifting for 5-V input down to 3.3-V output levels. Active Undershoot-Protection Circuitry on the A and B ports of the SN74CBTD3306C SN74CBTD3306C provides protection for undershoot up to -2 V by sensing an undershoot event and ensuring that the switch remains in the proper OFF state. The SN74CBTD3306C SN74CBTD3306C is organized as two 1-bit bus switches with separate output-enable (1OE, 2OE) inputs. It can be used as two 1-bit bus switches or as one 2-bit bus switch. When OE is low, the associated 1-bit bus switch is ON, and the A port is connected to the B port, allowing bidirectional data flow between ports. When OE is high, the associated 1-bit bus switch is OFF, and a high-impedance state exists between the A and B ports. ORDERING INFORMATION ORDERABLE PART NUMBER PACKAGE TA TOP-SIDE MARKING Tube TSSOP - PW SN74CBTD3306CDR SN74CBTD3306CDR Tube -40°C to 85°C SN74CBTD3306CD SN74CBTD3306CD Tape and reel SOIC - D SN74CBTD3306CPW SN74CBTD3306CPW Tape and reel SN74CBTD3306CPWR SN74CBTD3306CPWR CC306C CC306C CC306C CC306C Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2003, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 1 SN74CBTD3306C SN74CBTD3306C DUAL FET BUS SWITCH WITH LEVEL SHIFTING 5V BUS SWITCH WITH 2V UNDERSHOOT PROTECTION SCDS128A SCDS128A - SEPTEMBER 2003 - REVISED OCTOBER 2003 description/ordering information (continued) This device is fully specified for partial-power-down applications using Ioff. The Ioff feature ensures that damaging current will not backflow through the device when it is powered down. The device has isolation during power off. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. FUNCTION TABLE (each bus switch) INPUT OE INPUT/OUTPUT A FUNCTION L B A port = B port H Z Disconnect logic diagram (positive logic) 3 2 1A 1OE 1B SW 1 5 6 2A SW 2B 7 2OE simplified schematic, each FET switch (SW) A B Undershoot Protection Circuit EN EN is the internal enable signal applied to the switch. 2 POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 SN74CBTD3306C SN74CBTD3306C DUAL FET BUS SWITCH WITH LEVEL SHIFTING 5V BUS SWITCH WITH 2V UNDERSHOOT PROTECTION SCDS128A SCDS128A - SEPTEMBER 2003 - REVISED OCTOBER 2003 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Control input voltage range, VIN (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Switch I/O voltage range, VI/O (see Notes 1, 2, and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Control input clamp current, IIK (VIN < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA I/O port clamp current, II/OK (VI/O < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA ON-state switch current, II/O (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±128 mA Continuous current through VCC or GND terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA Package thermal impedance, JA (see Note 5): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to 150°C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltages are with respect to ground unless otherwise specified. 2. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 3. VI and VO are used to denote specific conditions for VI/O. 4. II and IO are used to denote specific conditions for II/O. 5. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Notes 6 and 7) MIN MAX 4.5 5.5 V High-level control input voltage 2 5.5 V Low-level control input voltage 0 0.8 V Data input/output voltage 0 5.5 V VCC VIH Supply voltage VIL VI/O UNIT TA Operating free-air temperature -40 85 °C NOTES: 6. All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004 SCBA004. 7. In applications with fast edge rates, multiple outputs switching, and operating at high frequencies, the output may have little or no level-shifting effect. POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 3 SN74CBTD3306C SN74CBTD3306C DUAL FET BUS SWITCH WITH LEVEL SHIFTING 5V BUS SWITCH WITH 2V UNDERSHOOT PROTECTION SCDS128A SCDS128A - SEPTEMBER 2003 - REVISED OCTOBER 2003 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VIK Control inputs VCC = 4.5 V, VIKU Data inputs VCC = 5 V, VOH IIN Control inputs IIN = -18 mA 0 mA > II -50 mA, VIN = VCC or GND, MIN TYP UNIT -1.8 V -2 V ±1 µA ±10 Switch OFF MAX µA See Figures 4 and 5 VCC = 5.5 V, IOZ VCC = 5.5 V, Ioff VCC = 0, ICC VCC = 5.5 V, VIN = VCC or GND VO = 0 to 5.5 V, VI = 0, Switch OFF, VIN = VCC or GND VO = 0 to 5.5 V, II/O = 0, VIN = VCC or GND, VI = 0 10 µA Switch ON or OFF 1.5 mA VCC = 5.5 V, VIN = 3 V or 0 One input at 3.4 V, Other inputs at VCC or GND 2.5 mA Cio(OFF) VI/O = 3 V or 0, Switch OFF, Cio(ON) VI/O = 3 V or 0, Switch ON, ron¶ VCC = 4.5 V VI = 0 IO = 64 mA IO = 30 mA ICC§ Cin Control inputs Control inputs 3.5 pF VIN = VCC or GND 5 pF VIN = VCC or GND 12.5 pF 3 6 3 6 VI = 2.4 V, IO = -15 mA 9 20 VIN and IIN refer to control inputs. VI, VO, II, and IO refer to data pins. All typical values are at VCC = 5 V (unless otherwise noted), TA = 25°C. For I/O ports, the parameter IOZ includes the input leakage current. § This is the increase in supply current for each input that is at the specified voltage level, rather than VCC or GND. ¶ Measured by the voltage drop between the A and B terminals at the indicated current through the switch. ON-state resistance is determined by the lower of the voltages of the two (A or B) terminals. switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3) PARAMETER tpd# ten FROM (INPUT) TO (OUTPUT) A or B B or A OE A or B VCC = 5 V ± 0.5 V MIN UNIT MAX 0.15 1.5 ns 4.7 ns tdis A or B 1.5 4.7 ns OE # The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance). 4 POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 SN74CBTD3306C SN74CBTD3306C DUAL FET BUS SWITCH WITH LEVEL SHIFTING 5V BUS SWITCH WITH 2V UNDERSHOOT PROTECTION SCDS128A SCDS128A - SEPTEMBER 2003 - REVISED OCTOBER 2003 undershoot characteristics (see Figures 1 and 2) PARAMETER VOUTU VCC = 5.5 V, Switch OFF, All typical values are at VCC = 5 V (unless otherwise noted), TA = 25°C. VCC Input Generator 50 DUT TYP 2 VOH-0.3 VIN = VCC or GND MAX UNIT V 11 V Input (Open Socket) 100 k Ax VS MIN TEST CONDITIONS Bx 100 k 90 % 2 ns 10 % -2 V 20 ns Output (VOUTU) POST OFFICE BOX 655303 5.5 V 2 ns 10 % 10 pF Figure 1. Device Test Setup 90 % VOH VOH - 0.3 Figure 2. Transient Input Voltage (VI) and Output Voltage (VOUTU) Waveforms (Switch OFF) · DALLAS, TEXAS 75265 5 SN74CBTD3306C SN74CBTD3306C DUAL FET BUS SWITCH WITH LEVEL SHIFTING 5V BUS SWITCH WITH 2V UNDERSHOOT PROTECTION SCDS128A SCDS128A - SEPTEMBER 2003 - REVISED OCTOBER 2003 PARAMETER MEASUREMENT INFORMATION FOR LEVEL SHIFTER VCC Input Generator VIN 50 50 VG1 TEST CIRCUIT DUT 7V Input Generator S1 RL VO VI GND 50 50 VG2 CL (see Note A) RL VCC S1 RL VI CL tpd(s) 5 V ± 0.5 V Open 500 VCC or GND 50 pF tPLZ/tPZL 5 V ± 0.5 V 7V 500 GND 50 pF 0.3 V tPHZ/tPZH 5 V ± 0.5 V Open 500 VCC 50 pF 0.3 V TEST Output Control (VIN) V 3V 1.5 V 3V 1.5 V 1.5 V 0V tPLH VOH Output 1.5 V Output Waveform 1 S1 at 7 V (see Note B) tPLZ 3.5 V 1.5 V tPZH tPHL 1.5 V VOL Output Waveform 2 S1 at Open (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES (tpd(s) 1.5 V 0V tPZL Output Control (VIN) Open VOL + V VOL tPHZ 1.5 V VOH - V VOH 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2.5 ns, tf 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd(s). The tpd propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance). H. All parameters and waveforms are not applicable to all devices. Figure 3. Test Circuit and Voltage Waveforms 6 POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 SN74CBTD3306C SN74CBTD3306C DUAL FET BUS SWITCH WITH LEVEL SHIFTING 5V BUS SWITCH WITH 2V UNDERSHOOT PROTECTION SCDS128A SCDS128A - SEPTEMBER 2003 - REVISED OCTOBER 2003 TYPICAL CHARACTERISTICS OUTPUT VOLTAGE HIGH vs SUPPLY VOLTAGE OUTPUT VOLTAGE HIGH vs SUPPLY VOLTAGE 4 3.5 100 µA 3.25 6 mA 12 mA 3 24 mA VOH - Output Voltage High - V 3.75 6 mA 12 mA 3.25 24 mA 3 2.75 2.5 2.25 2 1.75 1.5 4.5 TA = 25°C VI = VCC 100 µA 3.5 2.75 2.5 2.25 2 1.75 4.75 5 5.25 5.5 1.5 4.5 5.75 4.75 VCC - Supply Voltage - V 5 5.25 5.5 5.75 VCC - Supply Voltage - V OUTPUT VOLTAGE HIGH vs SUPPLY VOLTAGE 4 TA = 0°C VI = VCC 3.75 VOH - Output Voltage High - V VOH - Output Voltage High - V 3.75 4 TA = 85°C VI = VCC 3.5 100 µA 3.25 6 mA 12 mA 3 24 mA 2.75 2.5 2.25 2 1.75 1.5 4.5 4.75 5 5.25 5.5 5.75 VCC - Supply Voltage - V Figure 4. VOH Values POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 7 SN74CBTD3306C SN74CBTD3306C DUAL FET BUS SWITCH WITH LEVEL SHIFTING 5V BUS SWITCH WITH 2V UNDERSHOOT PROTECTION SCDS128A SCDS128A - SEPTEMBER 2003 - REVISED OCTOBER 2003 TYPICAL CHARACTERISTICS (continued) OUTPUT VOLTAGE vs INPUT VOLTAGE 3.5 VCC = 5 V TA = 25°C VO - Output Voltage - V 3 100 µA 6 mA 12 mA 24 mA 2.5 2 1.5 1 5 0 0 1 2 3 4 5 VI - Input Voltage - V Figure 5. Data Output Voltage vs Data Input Voltage 8 POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 24-May-2007 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SN74CBTD3306CD SN74CBTD3306CD ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74CBTD3306CDE4 SN74CBTD3306CDE4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74CBTD3306CDG4 SN74CBTD3306CDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74CBTD3306CDR SN74CBTD3306CDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74CBTD3306CDRE4 SN74CBTD3306CDRE4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74CBTD3306CDRG4 SN74CBTD3306CDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74CBTD3306CPW SN74CBTD3306CPW ACTIVE TSSOP PW 8 150 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74CBTD3306CPWE4 SN74CBTD3306CPWE4 ACTIVE TSSOP PW 8 150 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74CBTD3306CPWG4 SN74CBTD3306CPWG4 ACTIVE TSSOP PW 8 150 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74CBTD3306CPWR SN74CBTD3306CPWR ACTIVE TSSOP PW 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74CBTD3306CPWRE4 SN74CBTD3306CPWRE4 ACTIVE TSSOP PW 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74CBTD3306CPWRG4 SN74CBTD3306CPWRG4 ACTIVE TSSOP PW 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 24-May-2007 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 19-Mar-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel Diameter Width (mm) W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN74CBTD3306CDR SN74CBTD3306CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 SN74CBTD3306CPWR SN74CBTD3306CPWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 19-Mar-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74CBTD3306CDR SN74CBTD3306CDR SOIC D 8 2500 340.5 338.1 20.6 SN74CBTD3306CPWR SN74CBTD3306CPWR TSSOP PW 8 2000 346.0 346.0 29.0 Pack Materials-Page 2 MECHANICAL DATA MTSS001C MTSS001C ­ JANUARY 1995 ­ REVISED FEBRUARY 1999 PW (R-PDSO-G*) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°­ 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS * 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153 MO-153 POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. 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