SN54CBT16209 SN74CBT16209A 18-BIT SCDS006M SN74CBT16209ADL SN74CBT616209ADLR - Datasheet Archive

 

18-BIT FET BUS-EXCHANGE SWITCHES SCDS006M ­ NOVEMBER 1992 ­ REVISED OCTOBER 2000 D D D Members of Texas Instruments'

 

SN54CBT16209 SN54CBT16209, SN74CBT16209A SN74CBT16209A 18-BIT 18-BIT FET BUS-EXCHANGE SWITCHES SCDS006M SCDS006M ­ NOVEMBER 1992 ­ REVISED OCTOBER 2000 D D D Members of Texas Instruments' Widebus TM Family 5- Switch Connection Between Two Ports TTL-Compatible Input Levels SN54CBT16209 SN54CBT16209 . . . WD PACKAGE SN74CBT16209A SN74CBT16209A . . . DGG, DGV, OR DL PACKAGE (TOP VIEW) S0 1A1 1A2 GND 2A1 2A2 VCC 3A1 3A2 GND 4A1 4A2 5A1 5A2 GND 6A1 6A2 7A1 7A2 GND 8A1 8A2 9A1 9A2 description The SN54CBT16209 SN54CBT16209 and SN74CBT16209A SN74CBT16209A devices provide 18 bits of high-speed TTL-compatible bus switching or exchanging. The low on-state resistance of the switches allows connections to be made with minimal propagation delay. The devices operate as an 18-bit bus switch or a 9-bit bus exchanger, which provides data exchanging between the four signal ports via the data-select (S0, S1, S2) terminals. 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 32 18 31 19 30 20 29 21 28 22 27 23 26 24 25 S1 S2 1B1 1B2 2B1 2B2 GND 3B1 3B2 GND 4B1 4B2 5B1 5B2 GND 6B1 6B2 7B1 7B2 GND 8B1 8B2 9B1 9B2 ORDERING INFORMATION ORDERABLE PART NUMBER PACKAGE TA TOP-SIDE MARKING Tube SN74CBT16209ADL SN74CBT16209ADL Tape and reel SN74CBT616209ADLR SN74CBT616209ADLR TSSOP ­ DGG Tape and reel SN74CBT16209ADGGR SN74CBT16209ADGGR CBT16209A CBT16209A TVSOP ­ DGV Tape and reel SN74CBT16209ADGVR SN74CBT16209ADGVR CY209A CY209A SSOP ­ DL ­40°C to 85°C 40°C CBT16209A CBT16209A ­55°C to 125°C CFP ­ WD Tube SNJ54CBT16209WD SNJ54CBT16209WD SNJ54CBT16209WD SNJ54CBT16209WD Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus is a trademark of Texas Instruments. Copyright © 2000, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. On products compliant to MIL-PRF-38535 MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 1 SN54CBT16209 SN54CBT16209, SN74CBT16209A SN74CBT16209A 18-BIT 18-BIT FET BUS-EXCHANGE SWITCHES SCDS006M SCDS006M ­ NOVEMBER 1992 ­ REVISED OCTOBER 2000 FUNCTION TABLE INPUTS INPUTS/OUTPUTS S2 S1 S0 L L L L L H L FUNCTION A1 A2 L Z Z Disconnect H B1 Z A1 port = B1 port B2 Z A1 port = B2 port L H Z B1 A2 port = B1 port L L Z B2 A2 port = B2 port H L H Z Z Disconnect H H L B1 B2 A1 port = B1 port A2 port = B2 port H 2 H H H H B2 B1 A1 port = B2 port A2 port = B1 port POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 SN54CBT16209 SN54CBT16209, SN74CBT16209A SN74CBT16209A 18-BIT 18-BIT FET BUS-EXCHANGE SWITCHES SCDS006M SCDS006M ­ NOVEMBER 1992 ­ REVISED OCTOBER 2000 logic diagram (positive logic) 1A1 1A2 2 46 3 45 1B2 23 26 24 9A1 1B1 25 9B1 9B2 9A2 1 S0 S1 48 47 S2 POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 3 SN54CBT16209 SN54CBT16209, SN74CBT16209A SN74CBT16209A 18-BIT 18-BIT FET BUS-EXCHANGE SWITCHES SCDS006M SCDS006M ­ NOVEMBER 1992 ­ REVISED OCTOBER 2000 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ­0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ­0.5 V to 7 V Continuous channel current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ­50 mA Package thermal impedance, JA (see Note 2): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ­65°C to 150°C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 3) SN54CBT16209 SN54CBT16209 SN74CBT16209A SN74CBT16209A MIN MAX MIN MAX 5.5 4 5.5 VCC VIH Supply voltage 4 High-level control input voltage 2 VIL TA Low-level control input voltage 2 ­55 V V 0.8 Operating free-air temperature UNIT 0.8 125 V 85 ­40 °C NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004 SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK ICC ICC§ Control inputs Ci Control inputs ron¶ II = ­18 mA VI = 5.5 V VCC = 5.5 V, VCC = 5.5 V, VI = 5.5 V or GND IO = 0, VCC = 5.5 V, VI = 3 V or 0 One input at 3.4 V, VO = 3 V or 0, S0, S1, or S2 = VCC MIN TYP VCC = 4.5 V MAX UNIT ­1.2 VCC = 4.5 V, VCC = 0, II Cio(OFF) TEST CONDITIONS V 10 ±1 3 µA 2.5 VI = VCC or GND Other inputs at VCC or GND mA 4 VI = 0 pF 7.5 II = 64 mA II = 30 mA µA pF 4 8 4 8 VI = 2.4 V, II = 15 mA 6 15 All typical values are at VCC = 5 V (unless otherwise noted), TA = 25°C. § This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND. ¶ Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is determined by the lower of the voltages of the two (A or B) terminals. 4 POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 SN54CBT16209 SN54CBT16209, SN74CBT16209A SN74CBT16209A 18-BIT 18-BIT FET BUS-EXCHANGE SWITCHES SCDS006M SCDS006M ­ NOVEMBER 1992 ­ REVISED OCTOBER 2000 switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) SN54CBT16209 SN54CBT16209 FROM (INPUT) TO (OUTPUT) SN74CBT16209A SN74CBT16209A VCC = 4 V VCC = 4 V VCC = 5 V ± 0.5 V MIN PARAMETER VCC = 5 V ± 0.5 V MIN MIN MIN MAX MAX MAX tpd A or B B or A tpd S A or B 14 2 13.1 9.9 ten tdis S A or B 16 1.7 15.3 10.3 S A or B 14.5 1 13.2 9.3 0.8* UNIT MAX 0.35 0.25 ns 1.5 9 ns 1.5 9.8 ns 1.5 8.8 ns * On products compliant to MIL-PRF-38535 MIL-PRF-38535, this parameter is not production tested. The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance). PARAMETER MEASUREMENT INFORMATION 7V S1 500 From Output Under Test TEST GND CL = 50 pF (see Note A) S1 tpd tPLZ/tPZL tPHZ/tPZH Open Open 7V Open 500 3V Output Control LOAD CIRCUIT 1.5 V 0V tPLZ tPZL 3V Input 1.5 V 1.5 V 0V tPLH Output Waveform 1 S1 at 7 V (see Note B) 1.5 V 3.5 V 1.5 V 1.5 V VOL Output Waveform 2 S1 at Open (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VOL + 0.3 V VOL tPHZ tPZH tPHL VOH Output 1.5 V 1.5 V VOH VOH ­ 0.3 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2.5 ns, tf 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 5 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. 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