SN74ALS666 SN74ALS667 SDAS227A SN74ALS666DW SN74ALS666DWE4 SN74ALS666DWR - Datasheet Archive

 

8-BIT D-TYPE TRANSPARENT READ-BACK LATCHES WITH 3-STATE OUTPUTS SDAS227A ­ JUNE 1984 ­ REVISED JANUARY 1995 ·

 

SN74ALS666 SN74ALS666, SN74ALS667 SN74ALS667 8-BIT D-TYPE TRANSPARENT READ-BACK LATCHES WITH 3-STATE OUTPUTS SDAS227A SDAS227A ­ JUNE 1984 ­ REVISED JANUARY 1995 · · · · · 3-State I/O-Type Read-Back Inputs Bus-Structured Pinout Choice of True or Inverting Logic ­ SN74ALS666 SN74ALS666 . . . True Outputs ­ SN74ALS667 SN74ALS667 . . . Inverted Outputs Preset and Clear Inputs Package Options Include Plastic Small-Outline (DW) Packages and Standard Plastic (NT) 300-mil DIPs description These 8-bit D-type transparent latches are designed specifically for storing the contents of the input data bus, plus reading back the stored data onto the input data bus. In addition, they provide a 3-state buffer-type output and are easily utilized in bus-structured applications. While the latch enable (LE) is high, the Q outputs of the SN74ALS666 SN74ALS666 follow the data (D) inputs. The Q outputs of the SN74ALS667 SN74ALS667 provide the inverse of the data applied to its D inputs. The Q or Q output of both devices is in the high-impedance state if either output-enable (OE1 or OE2) input is at a high logic level. Read back is provided through the read-back control (OERB) input. When OERB is taken low, the data present at the output of the data latches passes back onto the input data bus. When OERB is taken high, the output of the data latches is isolated from the D inputs. OERB does not affect the internal operation of the latches; however, caution should be exercised to avoid a bus conflict. SN74ALS666 SN74ALS666 . . . DW OR NT PACKAGE (TOP VIEW) OERB OE1 1D 2D 3D 4D 5D 6D 7D 8D CLR GND 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 VCC OE2 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q PRE LE SN74ALS667 SN74ALS667 . . . DW OR NT PACKAGE (TOP VIEW) OERB OE1 1D 2D 3D 4D 5D 6D 7D 8D CLR GND 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 VCC OE2 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q PRE LE The SN74ALS666 SN74ALS666 and SN74ALS667 SN74ALS667 are characterized for operation from 0°C to 70°C. Copyright © 1995, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 1 SN74ALS666 SN74ALS666, SN74ALS667 SN74ALS667 8-BIT D-TYPE TRANSPARENT READ-BACK LATCHES WITH 3-STATE OUTPUTS SDAS227A SDAS227A ­ JUNE 1984 ­ REVISED JANUARY 1995 logic symbols SN74ALS666 SN74ALS666 & 2 OE1 OE2 OERB 14 PRE 11 CLR LE 1D 13 3 OE2 EN3 2D 3D 4D 5D 6D 7D 8D OERB S 1 14 11 CLR C1 LE 1D 22 2 4 21 5 20 6 19 7 18 8 17 9 16 10 15 1D 13 3 1Q 2Q 3Q 2D 3D 4D 5Q 5D 6Q 6D 7Q 7D POST OFFICE BOX 655303 S R C1 1D 8D 22 2 1Q 4 21 5 20 6 19 7 18 8 17 9 16 10 15 These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. 2 EN3 3 4Q 8Q EN2 23 PRE R 3 & 2 OE1 EN2 23 1 SN74ALS667 SN74ALS667 · DALLAS, TEXAS 75265 2Q 3Q 4Q 5Q 6Q 7Q 8Q SN74ALS666 SN74ALS666, SN74ALS667 SN74ALS667 8-BIT D-TYPE TRANSPARENT READ-BACK LATCHES WITH 3-STATE OUTPUTS SDAS227A SDAS227A ­ JUNE 1984 ­ REVISED JANUARY 1995 logic diagrams (positive logic) OE1 OE2 OERB PRE CLR LE 1D 2 SN74ALS666 SN74ALS666 23 1 14 11 13 S 3 1D 22 C1 1Q R To Seven Other Channels OE1 OE2 OERB PRE CLR LE 1D 2 SN74ALS667 SN74ALS667 23 1 14 11 13 S 3 1D C1 22 1Q R To Seven Other Channels POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 3 SN74ALS666 SN74ALS666, SN74ALS667 SN74ALS667 8-BIT D-TYPE TRANSPARENT READ-BACK LATCHES WITH 3-STATE OUTPUTS SDAS227A SDAS227A ­ JUNE 1984 ­ REVISED JANUARY 1995 timing diagram Data Bus Input Data tsu Input Data Read Back th LE tsu tdis OERB tpd tpd Q CLR = H, PRE = H, OE1 = L, OE2 = L. This setup time ensures the read-back circuit does not create a conflict on the input data bus. absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage, VI (all inputs except D inputs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Voltage applied to D inputs and to disabled 3-state outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Operating free-air temperature range, TA: SN74ALS666 SN74ALS666, SN74ALS667 SN74ALS667 . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ­ 65°C to 150°C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. recommended operating conditions SN74ALS666 SN74ALS666 SN74ALS667 SN74ALS667 UNIT MIN VCC VIH VIL MAX 4.5 Supply voltage NOM 5 5.5 Low-level input voltage High-level input voltage IOH tw 0.8 ­ 0.4 Q 24 D Pulse duration ­ 2.6 D Low-level Low level output current 8 LE high 10 PRE low 10 Data before OERB 10 tsu Setup time th TA Hold time, data after LE Operating free-air temperature 0 POST OFFICE BOX 655303 mA ns 5 4 mA 10 Data before LE V 10 CLR low V V Q High-level High level output current IOL 2 · DALLAS, TEXAS 75265 ns ns 70 °C SN74ALS666 SN74ALS666, SN74ALS667 SN74ALS667 8-BIT D-TYPE TRANSPARENT READ-BACK LATCHES WITH 3-STATE OUTPUTS SDAS227A SDAS227A ­ JUNE 1984 ­ REVISED JANUARY 1995 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS SN74ALS666 SN74ALS666 SN74ALS667 SN74ALS667 MIN VIK All outputs II = ­ 18 mA IOH = ­ 0.4 mA Q or Q VCC = 4.5 V, D inputs VOH VCC = 4.5 V, VCC = 4.5 V to 5.5 V, VCC = 4 5 V 4.5 IOH = ­ 2.6 mA IOL = 4 mA VOL Q or Q IOZH IOZL II IIH IIL VCC = 4 5 V 4.5 Q or Q VCC = 5.5 V, VCC = 5.5 V, Q or Q D inputs All others D inputs VCC = 5 5 V 5.5 All others IO§ UNIT MAX ­ 1.2 VCC ­ 2 2.4 0.4 IOL = 8 mA IOL = 12 mA 0.35 0.5 0.25 0.4 IOL = 24 mA VO = 2.7 V 0.35 0.5 20 20 VI = 0 4 V 0.4 VO = 2.25 V Q outputs high µA 0.1 VI = 2 7 V 2.7 VCC = 5 5 V 5.5 V, µA 0.1 VI = 7 V VCC = 5 5 V 5.5 V, 20 ­ 0.1 ­ 0.1 ­ 30 ­112 SN74ALS667 SN74ALS667 VCC = 5.5 V 5 5 V, OERB high 55 25 50 Q outputs low 45 µA mA mA 73 30 mA 50 40 79 Q outputs disabled ICC 25 Q outputs low Q outputs high VCC = 5.5 V, 55V OERB high V ­ 20 VO = 0.4 V VI = 5.5 V Q outputs disabled SN74ALS666 SN74ALS666 V V 3.2 0.25 VCC = 5.5 V, All others D inputs TYP 30 mA 60 All typical values are at VCC = 5 V, TA = 25°C. For I/O ports (QA through QH), the parameters IIH and IIL include the off-state output current. § The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS. POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 5 SN74ALS666 SN74ALS666, SN74ALS667 SN74ALS667 8-BIT D-TYPE TRANSPARENT READ-BACK LATCHES WITH 3-STATE OUTPUTS SDAS227A SDAS227A ­ JUNE 1984 ­ REVISED JANUARY 1995 switching characteristics (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 4.5 V to 5.5 V, CL = 50 pF, TA = MIN to MAX MIN MAX 3 14 4 18 6 21 8 27 Q 9 29 D 11 32 Q 7 22 D 9 28 OERB D 4 21 OE1, OE2 Q 4 21 OERB D 1 14 OE1, OE2 Q 1 14 tPLH tPHL D Q tPLH tPHL LE Q tPHL CLR tPLH tPHL ten tdi § dis UNIT SN74ALS666 SN74ALS666 PRE ns ns ns ns ns ns For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. ten = tPZH or tPZL § tdis = tPHZ or tPLZ switching characteristics (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 4.5 V to 5.5 V, CL = 50 pF, TA = MIN to MAX MIN MAX 6 20 4 15 9 28 7 22 Q 7 24 D 8 26 Q 8 25 D 9 28 tPLH tPHL D Q tPLH tPHL LE Q tPHL CLR tPLH tPHL ten tdi § dis PRE OERB D 4 21 OE1, OE2 Q 4 21 OERB D 1 14 Q 1 14 OE1, OE2 For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. ten = tPZH or tPZL § tdis = tPHZ or tPLZ 6 POST OFFICE BOX 655303 UNIT SN74ALS667 SN74ALS667 · DALLAS, TEXAS 75265 ns ns ns ns ns ns SN74ALS666 SN74ALS666, SN74ALS667 SN74ALS667 8-BIT D-TYPE TRANSPARENT READ-BACK LATCHES WITH 3-STATE OUTPUTS SDAS227A SDAS227A ­ JUNE 1984 ­ REVISED JANUARY 1995 PARAMETER MEASUREMENT INFORMATION 7V 7V S1 S1 500 1 k Test Point From Output Under Test CL (see Note A) CL (see Note A) 500 LOAD CIRCUIT FOR Q OR Q OUTPUTS 1 k LOAD CIRCUIT FOR D OUTPUTS 3.5 V Timing Input Test Point From Output Under Test 1.3 V 3.5 V High-Level Pulse 1.3 V 1.3 V 0.3 V 0.3 V tw th tsu 3.5 V Data Input 1.3 V 1.3 V 0.3 V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 1.3 V 0.3 V 3.5 V Output Control (low-level enabling) 1.3 V tPHL tPLH VOH 1.3 V 1.3 V tPHL Out-of-Phase Output (see Note D) Waveform 1 S1 Closed (see Note B) VOL tPLH VOH 1.3 V 1.3 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES 1.3 V 0.3 V tPZL 1.3 V tPLZ 0.3 V In-Phase Output 1.3 V VOLTAGE WAVEFORMS PULSE DURATIONS 3.5 V 1.3 V Input 3.5 V Low-Level Pulse [3.5 V 1.3 V tPHZ tPZH Waveform 2 S1 Open (see Note B) VOL 0.3 V VOH 1.3 V 0.3 V [0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses have the following characteristics: PRR 1 MHz, tr = tf = 2 ns, duty cycle = 50%. D. When measuring propagation delay times of 3-state outputs, switch S1 is open. Figure 1. Load Circuits and Voltage Waveforms POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 7 PACKAGE OPTION ADDENDUM www.ti.com 12-Jan-2006 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SN74ALS666DW SN74ALS666DW ACTIVE SOIC DW 24 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALS666DWE4 SN74ALS666DWE4 ACTIVE SOIC DW 24 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALS666DWR SN74ALS666DWR ACTIVE SOIC DW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALS666DWRE4 SN74ALS666DWRE4 ACTIVE SOIC DW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALS666NSR SN74ALS666NSR ACTIVE SO NS 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALS666NSRE4 SN74ALS666NSRE4 ACTIVE SO NS 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALS666NT SN74ALS666NT ACTIVE PDIP NT 24 15 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type SN74ALS666NTE4 SN74ALS666NTE4 ACTIVE PDIP NT 24 15 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type SN74ALS667DW SN74ALS667DW ACTIVE SOIC DW 24 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALS667DWE4 SN74ALS667DWE4 ACTIVE SOIC DW 24 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALS667DWR SN74ALS667DWR ACTIVE SOIC DW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALS667DWRE4 SN74ALS667DWRE4 ACTIVE SOIC DW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALS667NSR SN74ALS667NSR ACTIVE SO NS 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALS667NSRE4 SN74ALS667NSRE4 ACTIVE SO NS 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALS667NT SN74ALS667NT ACTIVE PDIP NT 24 CU NIPDAU N / A for Pkg Type SN74ALS667NT3 SN74ALS667NT3 OBSOLETE PDIP NT 24 SN74ALS667NTE4 SN74ALS667NTE4 ACTIVE PDIP NT 24 Lead/Ball Finish 15 Pb-Free (RoHS) TBD Call TI 15 Pb-Free (RoHS) CU NIPDAU MSL Peak Temp (3) Call TI N / A for Pkg Type (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 12-Jan-2006 (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 MECHANICAL DATA MPDI004 MPDI004 ­ OCTOBER 1994 NT (R-PDIP-T*) PLASTIC DUAL-IN-LINE PACKAGE 24 PINS SHOWN PINS * A 24 28 A MAX 1.260 (32,04) 1.425 (36,20) A MIN 1.230 (31,24) 1.385 (35,18) B MAX 0.310 (7,87) 0.315 (8,00) B MIN 0.290 (7,37) 0.295 (7,49) DIM 24 13 0.280 (7,11) 0.250 (6,35) 1 12 0.070 (1,78) MAX B 0.020 (0,51) MIN 0.200 (5,08) MAX Seating Plane 0.125 (3,18) MIN 0.100 (2,54) 0.021 (0,53) 0.015 (0,38) 0°­ 15° 0.010 (0,25) M 0.010 (0,25) NOM 4040050 / B 04/95 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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