SN54AHCT74 SN74AHCT74 SCLS263C AHCT74 JESD-17 MIL-STD-883 MIL-PRF-38535

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET SCLS263C DECEMBER 1995 REVISED NOVEMBER 1996 D D

SN54AHCT74 SN54AHCT74, SN74AHCT74 SN74AHCT74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET SCLS263C SCLS263C DECEMBER 1995 REVISED NOVEMBER 1996 D D 1CLR 1D 1CLK 1PRE 1Q 1Q GND 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 2CLR 2D 2CLK 2PRE 2Q 2Q SN54AHCT74 SN54AHCT74 . . . FK PACKAGE (TOP VIEW) description The 'AHCT74 AHCT74 are dual positive-edge-triggered D-type flip-flops. 1CLK NC 1PRE NC 1Q 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 2D NC 2CLK NC 2PRE 1Q GND NC 2Q 2Q A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. 4 NC No internal connection The SN54AHCT74 SN54AHCT74 is characterized for operation over the full military temperature range of 55°C to 125°C. The SN74AHCT74 SN74AHCT74 is characterized for operation from 40°C to 85°C. FUNCTION TABLE INPUTS OUTPUTS PRE CLR CLK D Q L H X X H Q L H L X X L H L L X X H H H H H H L H H L L H H H L X Q0 Q0 This configuration is nonstable; that is, it does not persist when PRE or CLR returns to its inactive (high) level. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC is a trademark of Texas Instruments Incorporated. Copyright © 1996, Texas Instruments Incorporated ADVANCE INFORMATION concerns new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice. POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 1 ADVANCE INFORMATION D SN54AHCT74 SN54AHCT74 . . . J OR W PACKAGE SN74AHCT74 SN74AHCT74 . . . D, DB, N, OR PW PACKAGE (TOP VIEW) Inputs Are TTL-Voltage Compatible EPIC TM (Enhanced-Performance Implanted CMOS) Process High Latch-Up Immunity Exceeds 250 mA Per JEDEC Standard JESD-17 JESD-17 ESD Protection Exceeds 2000 V Per MIL-STD-883 MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Package Options Include Plastic Small-Outline (D), Shrink Small-Outline (DB), Thin Shrink Small-Outline (PW), and Ceramic Flat (W) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs 1D 1CLR NC VCC 2CLR D D SN54AHCT74 SN54AHCT74, SN74AHCT74 SN74AHCT74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET SCLS263C SCLS263C DECEMBER 1995 REVISED NOVEMBER 1996 logic symbol 1PRE 4 1CLK 1CLR 2PRE 1D 1 6 1Q R 10 9 11 2CLK 1Q C1 2 1D 5 S 3 2Q 12 2D 8 2CLR 13 2Q This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, DB, J, N, PW, and W packages. ADVANCE INFORMATION logic diagram, each flip-flop (positive logic) PRE CLK C C C Q TG C C C C TG TG TG C D C C Q CLR 2 POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 SN54AHCT74 SN54AHCT74, SN74AHCT74 SN74AHCT74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET SCLS263C SCLS263C DECEMBER 1995 REVISED NOVEMBER 1996 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils, except for the N package, which has a trace length of zero. recommended operating conditions (see Note 3) SN54AHCT74 SN54AHCT74 SN74AHCT74 SN74AHCT74 MIN MAX MIN MAX 4.5 5.5 4.5 5.5 VCC VIH Supply voltage VIL VI Low-level input voltage Input voltage 0 5.5 VO IOH Output voltage 0 VCC 8 IOL Dt/Dv Low-level output current High-level input voltage 2 2 0.8 High-level output current UNIT V V 0.8 V 0 5.5 V 0 VCC 8 V mA 8 TA Operating free-air temperature NOTE 3: Unused inputs must be held high or low to prevent them from floating. 55 8 mA 20 Input transition rise or fall rate 20 ns/V 85 °C 125 40 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VOH TEST CONDITIONS IOH = 50 mA IOH = 8 mA VCC 4.5 45V VOL IOL = 50 mA IOL = 8 mA II ICC VI = VCC or GND VI = VCC or GND, DICC One input at 3.4 V, Other inputs at GND or VCC MIN 4.4 TA = 25°C TYP MAX 4.5 SN54AHCT74 SN54AHCT74 MIN MAX SN74AHCT74 SN74AHCT74 MIN 4.4 4.4 3.8 3.94 MAX 3.8 V 0.1 0.1 0.1 0.36 4.5 45V UNIT 0.5 0.44 V 5.5 V IO = 0 ±0.1 ±1 ±1 5.5 V 2 20 20 mA mA 5.5 V 1.35 1.5 1.5 mA 10 pF Ci VI = VCC or GND 5V 2 10 This is the increase in supply current for each input at one of the specified TTL voltage levels rather than 0 V or VCC. POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 3 ADVANCE INFORMATION Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Maximum power dissipation at TA = 55°C (in still air) (see Note 2): D package . . . . . . . . . . . . . . . . . . . 1.25 W DB or PW package . . . . . . . . . . . . . 0.5 W N package . . . . . . . . . . . . . . . . . . . . 1.1 W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C SN54AHCT74 SN54AHCT74, SN74AHCT74 SN74AHCT74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET SCLS263C SCLS263C DECEMBER 1995 REVISED NOVEMBER 1996 timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 1) TA = 25°C MIN MAX PARAMETER SN54AHCT74 SN54AHCT74 MIN SN74AHCT74 SN74AHCT74 MAX MIN PRE or CLR low tsu Setup time before CLK th 5 5 5 5 5 Data Pulse duration 5 CLK tw 5 5 5 3.5 3.5 3.5 0 0 MAX 0 Hold time, data after CLK PRE or CLR inactive UNIT ns ns ns switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 1) SN54AHCT74 SN54AHCT74 PARAMETER FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE TA = 25°C MIN TYP MAX MIN ADVANCE INFORMATION CL = 15 pF 100 160 80 CL = 50 pF fmax 80 140 MAX 65 tPLH* tPHL* PRE or CLR Q or Q CL = 15 pF tPLH* tPHL* CLK Q or Q CL = 15 pF tPLH tPHL PRE or CLR Q or Q CL = 50 pF tPLH tPHL CLK Q or Q CL = 50 pF UNIT MHz 7.6 10.4 1 12 7.6 10.4 1 12 5.8 7.8 1 9 5.8 7.8 1 9 8.1 11.4 1 13 8.1 11.4 1 13 6.3 8.8 1 10 6.3 8.8 1 10 ns ns ns ns * On products compliant to MIL-PRF-38535 MIL-PRF-38535, this parameter is ensured but not production tested. switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 1) SN74AHCT74 SN74AHCT74 PARAMETER FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE MIN MIN CL = 15 pF 100 160 80 140 65 tPLH tPHL PRE or CLR Q or Q CL = 15 pF tPLH tPHL CLK Q or Q CL = 15 pF tPLH tPHL PRE or CLR Q or Q CL = 50 pF tPLH tPHL CLK Q or Q CL = 50 pF POST OFFICE BOX 655303 MAX 80 CL = 50 pF fmax 4 TA = 25°C TYP MAX · DALLAS, TEXAS 75265 UNIT MHz 7.6 10.4 1 12 7.6 10.4 1 12 5.8 7.8 1 9 5.8 7.8 1 9 8.1 11.4 1 13 8.1 11.4 1 13 6.3 8.8 1 10 6.3 8.8 1 10 ns ns ns ns SN54AHCT74 SN54AHCT74, SN74AHCT74 SN74AHCT74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET SCLS263C SCLS263C DECEMBER 1995 REVISED NOVEMBER 1996 noise characteristics, VCC = 5 V, CL = 50 pF, TA = 25°C (see Note 4) SN74AHCT74 SN74AHCT74 PARAMETER MIN MAX UNIT VOL(P) VOL(V) Quiet output, maximum dynamic VOL 0.8 V Quiet output, minimum dynamic VOL 0.8 V VOH(V) VIH(D) Quiet output, minimum dynamic VOH 4 V High-level dynamic input voltage 2 V VIL(D) Low-level dynamic input voltage 0.8 NOTE 4: Characteristics are determined during product characterization and ensured by design for surface-mount packages only. V operating characteristics, VCC = 5 V, TA = 25°C TEST CONDITIONS Power dissipation capacitance No load, TYP f = 1 MHz 32 UNIT pF ADVANCE INFORMATION PARAMETER Cpd PARAMETER MEASUREMENT INFORMATION From Output Under Test Test Point CL (see Note A) tw 3V Input 1.5 V 0V VOLTAGE WAVEFORMS PULSE DURATION 3V Input (see Note B) 1.5 V 1.5 V 0V tPHL tPLH 3V Timing Input (see Note B) 1.5 V 0V 1.5 V 1.5 V VOL tPLH tPHL 3V 1.5 V VOH In-Phase Output th tsu Data Input LOAD CIRCUIT 1.5 V 1.5 V VOH Out-of-Phase Output 1.5 V 1.5 V VOL 0V VOLTAGE WAVEFORMS DELAY TIMES VOLTAGE WAVEFORMS SETUP AND HOLD TIMES NOTES: A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO = 50 , tr C. The outputs are measured one at a time with one input transition per measurement. + 3 ns, tf + 3 ns. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 5 IMPORTANT NOTICE Texas Instruments (TI) reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied on is current. TI warrants performance of its semiconductor products and related software to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or environmental damage ("Critical Applications"). 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Nor does TI warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. Copyright © 1996, Texas Instruments Incorporated