SN54LV573A SN74LV573A SCLS411D A114-A A115-A LV573A SN74LV573ADW SN74LV573ADWR - Datasheet Archive

 

OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCLS411D ­ APRIL 1998 ­ REVISED JANUARY 2001 D D D D 2-V to 5.5-V

 

SN54LV573A SN54LV573A, SN74LV573A SN74LV573A OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCLS411D SCLS411D ­ APRIL 1998 ­ REVISED JANUARY 2001 D D D D 2-V to 5.5-V VCC Operation Typical VOLP (Output Ground Bounce) 2.3 V at VCC = 3.3 V , TA = 25°C Support Mixed-Mode Voltage Operation on All Ports Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds JESD 22 ­ 2000-V Human-Body Model (A114-A A114-A) ­ 200-V Machine Model (A115-A A115-A) ­ 1000-V Charged-Device Model (C101) description SN54LV573A SN54LV573A . . . J OR W PACKAGE SN74LV573A SN74LV573A . . . DB, DGV, DW, NS, OR PW PACKAGE (TOP VIEW) OE 1D 2D 3D 4D 5D 6D 7D 8D GND 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 VCC 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q LE SN54LV573A SN54LV573A . . . FK PACKAGE (TOP VIEW) These devices feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. This device is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. 2D 1D OE VCC The 'LV573A LV573A devices are octal transparent D-type latches designed for 2-V to 5.5-V VCC operation. 3D 4D 5D 6D 7D 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 2Q 3Q 4Q 5Q 6Q 8D GND LE 8Q 7Q While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs. 1Q D D A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components. OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright © 2001, Texas Instruments Incorporated UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 1 SN54LV573A SN54LV573A, SN74LV573A SN74LV573A OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCLS411D SCLS411D ­ APRIL 1998 ­ REVISED JANUARY 2001 ORDERING INFORMATION ORDERABLE PART NUMBER PACKAGE TA TOP-SIDE MARKING Tube SN74LV573ADW SN74LV573ADW Tape and reel SN74LV573ADWR SN74LV573ADWR SOP ­ NS Tape and reel SN74LV573ANSR SN74LV573ANSR 74LV573A 74LV573A SSOP ­ DB Tape and reel SN74LV573ADBR SN74LV573ADBR LV573A LV573A TSSOP ­ PW Tape and reel SN74LV573APWR SN74LV573APWR LV573A LV573A TVSOP ­ DGV Tape and reel SN74LV573ADGVR SN74LV573ADGVR LV573A LV573A CDIP ­ J Tube SNJ54LV573AJ SNJ54LV573AJ SNJ54LV573AJ SNJ54LV573AJ CFP ­ W Tube SNJ54LV573AW SNJ54LV573AW SNJ54LV573AW SNJ54LV573AW SOIC ­ DW ­40°C to 85°C 40°C ­55°C to 125°C LV573A LV573A LCCC - FK Tube SNJ54LV573AFK SNJ54LV573AFK SNJ54LV573AFK SNJ54LV573AFK Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE (each latch) INPUTS OE LE D OUTPUT Q L H H H L H L L L L X Q0 H X X Z logic symbol OE LE 1D 2D 3D 4D 5D 6D 7D 8D 1 11 2 EN C1 19 1D 3 18 4 17 5 16 6 15 7 14 8 13 9 12 This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. 2 POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q SN54LV573A SN54LV573A, SN74LV573A SN74LV573A OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCLS411D SCLS411D ­ APRIL 1998 ­ REVISED JANUARY 2001 logic diagram (positive logic) OE LE 1 11 C1 1D 2 19 1D 1Q To Seven Other Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ­0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ­0.5 V to 7 V Voltage range applied to any output in the high-impedance or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ­0.5 V to 7 V Output voltage range applied in the high or low state, VO (see Notes 1 and 2) . . . . . . ­0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ­20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±35 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±70 mA Package thermal impedance, JA (see Note 3): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92°C/W DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ­65°C to 150°C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. This value is limited to 5.5 V maximum. 3. The package thermal impedance is calculated in accordance with JESD 51-7. POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 3 SN54LV573A SN54LV573A, SN74LV573A SN74LV573A OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCLS411D SCLS411D ­ APRIL 1998 ­ REVISED JANUARY 2001 recommended operating conditions (see Note 4) SN54LV573A SN54LV573A VCC VIH SN74LV573A SN74LV573A MIN MAX MIN MAX 2 5.5 2 5.5 Supply voltage VCC = 2 V VCC = 2.3 V to 2.7 V High-level High level input voltage VIL VCC × 0.7 VCC × 0.7 VCC × 0.7 VCC × 0.7 VCC × 0.7 VCC × 0.7 IOH IOL t/v VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V 0.5 High or low state 0 3-state VCC × 0.3 VCC × 0.3 VCC × 0.3 5.5 0 Output voltage V 0.5 VCC × 0.3 VCC × 0.3 Input voltage VO 0 0 VCC 5.5 VCC × 0.3 5.5 0 0 µA ­50 ­50 ­2 ­2 ­8 ­8 ­16 ­16 VCC = 2 V VCC = 2.3 V to 2.7 V 50 50 2 2 VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V 8 8 16 VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V Input transition rise or fall rate V V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V Low-level Low level output current V VCC 5.5 VCC = 2 V VCC = 2.3 V to 2.7 V High-level High level output current V 1.5 VCC = 2 V VCC = 2.3 V to 2.7 V Low-level Low level input voltage VI VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V 1.5 UNIT mA µA mA 16 0 200 0 200 0 100 0 100 ns/V VCC = 4.5 V to 5.5 V 0 20 0 20 TA Operating free-air temperature ­55 125 ­40 85 °C NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004 SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VOH VOL TEST CONDITIONS IOH = ­50 µA IOH = ­2 mA 2.3 V VI = VCC or GND 2.48 4.5 V TYP MAX 3.8 UNIT V 2.48 3.8 0.1 0.1 0.4 0.44 0.44 4.5 V 0.55 0.55 0 to 5.5 V ±1 ±1 µA 5.5 V IO = 0 0.4 3V ±5 ±5 µA 5.5 V 20 20 µA 5 µA 0 3.3 V 5 1.8 PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 4 MIN 2.3 V VI = 5.5 V or GND VO = VCC or GND Ci SN74LV573A SN74LV573A MAX VCC­0.1 2 2 V to 5.5 V IOL = 8 mA IOL = 16 mA VI = VCC or GND, VI or VO = 0 to 5.5 V TYP VCC­0.1 2 3V IOL = 50 µA IOL = 2 mA ICC Ioff MIN 2 V to 5.5 V IOH = ­8 mA IOH = ­16 mA II IOZ SN54LV573A SN54LV573A VCC POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 1.8 V pF SN54LV573A SN54LV573A, SN74LV573A SN74LV573A OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCLS411D SCLS411D ­ APRIL 1998 ­ REVISED JANUARY 2001 timing requirements over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1) TA = 25°C MIN MAX PARAMETER SN54LV573A SN54LV573A MIN MAX SN74LV573A SN74LV573A MIN MAX UNIT tw Pulse duration LE high 6.5 6.5 6.5 ns tsu Setup time Data before LE 5 5 5 ns th Hold time Data after LE 2 2 2 ns timing requirements over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) TA = 25°C MIN MAX PARAMETER tw Pulse duration LE high tsu Setup time th Hold time SN54LV573A SN54LV573A MIN MAX SN74LV573A SN74LV573A MIN MAX UNIT 5 5 5 ns Data before LE 3.5 3.5 3.5 ns Data after LE 1.5 1.5 1.5 ns timing requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) TA = 25°C MIN MAX PARAMETER tw Pulse duration LE high tsu Setup time Hold time th SN54LV573A SN54LV573A MIN MAX SN74LV573A SN74LV573A MIN MAX UNIT 5 5 5 ns Data before LE 3.5 3.5 3.5 ns Data after LE 1.5 1.5 1.5 ns switching characteristics over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1) FROM (INPUT) TO (OUTPUT) D LE Q ten OE Q tdis OE D LOAD CAPACITANCE TA = 25°C MIN TYP MAX Q PARAMETER SN54LV573A SN54LV573A SN74LV573A SN74LV573A MIN MAX MIN MAX 8.9* 15.8* 1* 18* 1 18 9.6* 16.2* 1* 19* 1 19 9.3* 16.2* 1* 19* 1 19 Q 6.7* 12.6* 1* 15* 1 15 Q 10.9 18.7 1 21 1 21 LE Q 11.6 19.1 1 23 1 23 ten OE Q 11.4 19 1 22 1 22 tdis OE Q 8.6 17.3 1 19 1 UNIT 19 tpd tpd CL = 15 pF F CL = 50 pF tsk(o) 2 ns ns 2 * On products compliant to MIL-PRF-38535 MIL-PRF-38535, this parameter is not production tested. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 5 SN54LV573A SN54LV573A, SN74LV573A SN74LV573A OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCLS411D SCLS411D ­ APRIL 1998 ­ REVISED JANUARY 2001 switching characteristics over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) FROM (INPUT) TO (OUTPUT) D PARAMETER LOAD CAPACITANCE MIN TA = 25°C TYP MAX SN54LV573A SN54LV573A SN74LV573A SN74LV573A MIN MAX MIN MAX Q 6.2* 11* 1* 13* 1 13 LE Q 6.8* 11.9* 1* 14* 1 14 ten OE Q 6.6* 11.5* 1* 13.5* 1 13.5 tdis OE Q 4.9* 11* 1* 13* 1 13 D Q 7.7 14.5 1 16.5 1 16.5 8.2 15.4 1 17.5 1 17.5 8 15 1 17 1 17 6.2 14.5 1 16.5 1 UNIT 16.5 tpd tpd LE Q ten OE Q tdis OE CL = 15 pF F Q CL = 50 pF tsk(o) 1.5 ns ns 1.5 * On products compliant to MIL-PRF-38535 MIL-PRF-38535, this parameter is not production tested. switching characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) FROM (INPUT) TO (OUTPUT) D LE Q ten OE Q tdis OE LOAD CAPACITANCE TA = 25°C MIN TYP MAX Q PARAMETER SN54LV573A SN54LV573A SN74LV573A SN74LV573A MIN MAX MIN MAX 4.3* 6.8* 1* 8* 1 8 4.7* 7.7* 1* 9* 1 9 4.7* 7.7* 1* 9* 1 9 Q 3.5* 7.7* 1* 9* 1 9 D Q 5.3 8.8 1 10 1 10 LE Q 5.7 9.7 1 11 1 11 ten OE Q 5.7 9.7 1 11 1 11 tdis OE Q 4.2 9.7 1 11 1 UNIT 11 tpd tpd CL = 15 pF F CL = 50 pF tsk(o) 1 ns ns 1 * On products compliant to MIL-PRF-38535 MIL-PRF-38535, this parameter is not production tested. noise characteristics, VCC = 3.3 V, CL = 50 pF, TA = 25°C (see Note 5) SN74LV573A SN74LV573A PARAMETER MIN TYP MAX UNIT VOL(P) VOL(V) Quiet output, maximum dynamic VOL 0.6 0.8 V Quiet output, minimum dynamic VOL ­0.5 ­0.8 V VOH(V) VIH(D) Quiet output, minimum dynamic VOH 2.9 High-level dynamic input voltage VIL(D) Low-level dynamic input voltage NOTE 5: Characteristics are for surface-mount packages only. POST OFFICE BOX 655303 V 0.99 PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 6 V 2.31 · DALLAS, TEXAS 75265 V SN54LV573A SN54LV573A, SN74LV573A SN74LV573A OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCLS411D SCLS411D ­ APRIL 1998 ­ REVISED JANUARY 2001 operating characteristics, TA = 25°C PARAMETER TEST CONDITIONS D to Q Cpd d Power dissipation capacitance CL = 50 pF pF, Outputs enabled LE to Q POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 f = 10 MHz VCC 3.3 V TYP UNIT 16 5V 18 3.3 V 18.2 5V 21.3 pF 7 SN54LV573A SN54LV573A, SN74LV573A SN74LV573A OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCLS411D SCLS411D ­ APRIL 1998 ­ REVISED JANUARY 2001 PARAMETER MEASUREMENT INFORMATION RL = 1 k From Output Under Test Test Point From Output Under Test VCC Open S1 TEST GND CL (see Note A) CL (see Note A) S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain Open VCC GND VCC LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS VCC 50% VCC Timing Input 0V tw tsu VCC 50% VCC 50% VCC Input th VCC 50% VCC Data Input 50% VCC 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC 50% VCC Input 50% VCC tPLH In-Phase Output 50% VCC VOH 50% VCC VOL VOH 50% VCC VOL 50% VCC 0V tPLZ VCC Output Waveform 1 S1 at VCC (see Note B) 50% VCC tPZH tPLH 50% VCC 50% VCC tPZL tPHL tPHL Out-of-Phase Output 0V VCC Output Control Output Waveform 2 S1 at GND (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS VOL + 0.3 V VOL tPHZ 50% VCC VOH ­ 0.3 V VOH 0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO = 50 , tr 3 ns, tf 3 ns. D. The outputs are measured one at a time with one input transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPHL and tPLH are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms 8 POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. 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