SN54LV165A SN74LV165A SCLS402B MIL-STD-883 LV165A SCBA004 MIL-PRF-38535 - Datasheet Archive

 

PARALLEL-LOAD 8-BIT SHIFT REGISTERS SCLS402B ­ APRIL 1998 ­ REVISED JULY 1998 D D D D D EPIC TM (Enhanced-Performance

 

SN54LV165A SN54LV165A, SN74LV165A SN74LV165A PARALLEL-LOAD 8-BIT SHIFT REGISTERS SCLS402B SCLS402B ­ APRIL 1998 ­ REVISED JULY 1998 D D D D D EPIC TM (Enhanced-Performance Implanted CMOS) Process Typical VOLP (Output Ground Bounce) < 0.8 V at VCC, TA = 25°C Typical VOHV (Output VOH Undershoot) < 2 V at VCC, TA = 25°C Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds 2000 V Per MIL-STD-883 MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Package Options Include Plastic Small-Outline (D, NS), Shrink Small-Outline (DB), Thin Very Small-Outline (DGV), and Thin Shrink Small-Outline (PW) Packages, Ceramic Flat (W) Packages, Chip Carriers (FK), and DIPs (J) SN54LV165A SN54LV165A . . . J OR W PACKAGE SN74LV165A SN74LV165A . . . D, DB, DGV, NS, OR PW PACKAGE (TOP VIEW) SH/LD CLK E F G H QH GND 1 15 3 14 4 13 5 VCC CLK INH D C B A SER QH 16 2 12 6 11 7 10 8 9 SN54LV165A SN54LV165A . . . FK PACKAGE (TOP VIEW) CLK SH/LD NC VCC CLK INH D description E F NC G H The 'LV165A LV165A devices are parallel-load, 8-bit shift registers designed for 2-V to 5.5-V VCC operation. 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 D C NC B A QH GND NC QH SER When the device is clocked, data is shifted toward the serial output QH. Parallel-in access to each stage is provided by eight individual direct data inputs that are enabled by a low level at the shift/load (SH/ LD) input. The 'LV165A LV165A devices feature a clock inhibit function and a complemented serial output QH. 4 NC ­ No internal connection Clocking is accomplished by a low-to-high transition of the clock (CLK) input while SH/ LD is held high and clock inhibit (CLK INH) is held low. The functions of the CLK and CLK INH inputs are interchangeable. Since a low CLK input and a low-to-high transition of CLK INH accomplishes clocking, CLK INH should be changed to the high level only while CLK is high. Parallel loading is inhibited when SH/ LD is held high. The parallel inputs to the register are enabled while SH/ LD is held low, independently of the levels of CLK, CLK INH, or SER. The SN54LV165A SN54LV165A is characterized for operation over the full military temperature range of ­55°C to 125°C. The SN74LV165A SN74LV165A is characterized for operation from ­40°C to 85°C. FUNCTION TABLE INPUTS SH/ LD CLK CLK INH OPERATION L X X Parallel load H H X Q0 H X H H L Q0 Shift H L Shift Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC is a trademark of Texas Instruments Incorporated. Copyright © 1998, Texas Instruments Incorporated UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 1 SN54LV165A SN54LV165A, SN74LV165A SN74LV165A PARALLEL-LOAD 8-BIT SHIFT REGISTERS SCLS402B SCLS402B ­ APRIL 1998 ­ REVISED JULY 1998 logic diagram (positive logic) A SH/LD CLK INH CLK SER B 11 1 C 12 D 13 E 14 F 3 G 4 H 5 6 15 2 S C1 1D R 10 S C1 1D R S C1 1D R S C1 1D R S C1 1D R S C1 1D R S C1 1D R Pin numbers shown are for the D, DB, DGV, J, NS, PW, and W packages. typical shift, load, and inhibit sequences CLK CLK INH SER L SH/LD A B L C H D L E H F L G H H Data Inputs H H QH H H L H L H L H QH L L H L H L H L Inhibit Serial Shift Load 2 POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 S C1 1D R 9 7 QH QH SN54LV165A SN54LV165A, SN74LV165A SN74LV165A PARALLEL-LOAD 8-BIT SHIFT REGISTERS SCLS402B SCLS402B ­ APRIL 1998 ­ REVISED JULY 1998 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ­0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ­0.5 V to 7 V Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ­0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ­20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Package thermal impedance, JA (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131°C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ­65°C to 150°C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. This value is limited to 7 V maximum. 3. The package thermal impedance is calculated in accordance with JESD 51. recommended operating conditions (see Note 4) SN54LV165A SN54LV165A SN74LV165A SN74LV165A MIN VCC VIH VIL VI VO IOH IOL MAX MIN MAX 2 5.5 2 5.5 Supply voltage High-level High level input voltage Low-level Low level input voltage VCC = 2 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V 1.5 VCC × 0.7 VCC × 0.7 VCC × 0.7 VCC = 2 V VCC = 2.3 V to 2.7 V 0.5 VCC × 0.3 VCC × 0.3 VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V 0 Output voltage 0 Low-level Low level output current V VCC × 0.7 0.5 Input voltage High-level High level output current VCC = 2 V VCC = 2.3 V to 2.7 V VCC × 0.3 VCC × 0.3 VCC × 0.3 5.5 VCC × 0.3 5.5 VCC ­50 0 0 ­2 VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V VCC ­50 Input transition rise or fall rate V V V µA ­2 ­6 ­6 ­12 VCC = 2 V VCC = 2.3 V to 2.7 V 50 50 2 2 VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V 6 6 mA ­12 12 µA mA 12 VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V 0 200 0 200 0 100 0 100 VCC = 4.5 V to 5.5 V t/v V 1.5 VCC × 0.7 VCC × 0.7 UNIT 0 20 0 20 ns/V TA Operating free-air temperature ­55 125 ­40 85 °C NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004 SCBA004. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 3 SN54LV165A SN54LV165A, SN74LV165A SN74LV165A PARALLEL-LOAD 8-BIT SHIFT REGISTERS SCLS402B SCLS402B ­ APRIL 1998 ­ REVISED JULY 1998 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VOH VOL SN54LV165A SN54LV165A TEST CONDITIONS IOH = ­50 µA IOH = ­2 mA VCC 2 V to 5.5 V MIN TYP VCC­0.1 2 2.48 2.48 4.5 V 3.8 MAX UNIT V 3.8 2 V to 5.5 V 0.1 0.1 2.3 V 0.4 0.4 3V 0.44 0.44 4.5 V 0.55 0.55 5.5 V ±1 ±1 µA 5.5 V 20 20 µA 0V 5 5 µA IOL = 6 mA IOL = 12 mA Ioff Ci SN74LV165A SN74LV165A MAX 3V IOL = 50 µA IOL = 2 mA VI = VCC or GND VI = VCC or GND, TYP VCC­0.1 2 2.3 V IOH = ­6 mA IOH = ­12 mA II ICC MIN VI or VO = 0 to 5.5 V VI = VCC or GND IO = 0 3.3 V 1.7 1.7 V pF timing requirements over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1) TA = 25°C MIN MAX tw Pulse duration CLK high or low SN54LV165A SN54LV165A MIN MAX SN74LV165A SN74LV165A MIN 8.5 SH/LD high before CLK 9 11 SH/LD low 9 13 13 7 8.5 9.5 7 7 7 11.5 12 12 ­1 0 0 Parallel data after SH/LD 0 0.5 0.5 0 0 0 CLK INH before CLK Data before SH/LD SER data after CLK th Hold time ns 9.5 SER before CLK Setup time UNIT 8.5 8.5 SH/LD high after CLK tsu MAX ns ns timing requirements over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) TA = 25°C MIN MAX MIN MAX SN74LV165A SN74LV165A MIN tsu Setup time 6 7 7 9 9 5 6 5 6 6 CLK INH before CLK 5 5 5 7.5 8.5 SER data after CLK Hold time Parallel data after SH/LD SH/LD high after CLK 0 0 0.5 0.5 0 0 0 POST OFFICE BOX 655303 ns ns 0 0.5 PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 4 UNIT 8.5 SH/LD low Data before SH/LD th MAX 6 SER before CLK Pulse duration 7.5 SH/LD high before CLK tw CLK high or low SN54LV165A SN54LV165A · DALLAS, TEXAS 75265 ns SN54LV165A SN54LV165A, SN74LV165A SN74LV165A PARALLEL-LOAD 8-BIT SHIFT REGISTERS SCLS402B SCLS402B ­ APRIL 1998 ­ REVISED JULY 1998 timing requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) TA = 25°C MIN MAX SN54LV165A SN54LV165A MIN MAX SN74LV165A SN74LV165A MIN tsu CLK high or low 4 4 SH/LD low Pulse duration 4 5 6 6 SH/LD high before CLK tw 4 4 4 0.5 0.5 1 1 1 0.5 SH/LD high after CLK 5 0.5 Parallel data after SH/LD 3.5 5 0.5 ns 4 3.5 5 SER data after CLK Hold time 4 3.5 CLK INH before CLK Data before SH/LD th UNIT 4 SER before CLK Setup time MAX 0.5 ns ns switching characteristics over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE TA = 25°C MIN TYP MAX MAX MIN 50 80 45 40 65 35 SH/LD 35 22 1 23.5 21.7 1 24 1 24 23.3 1 26 1 26 25.1 1 28 1 28 15.9 H 1 23.5 16.1 CL = 50 pF 22 1 15.3 QH or QH 1 21.5 12.9 CLK 19.8 13.1 CL = 15 pF UNIT MHz 12.2 QH or QH H SH/LD MAX 45 CL = 50 pF CLK tpd MIN SN74LV165A SN74LV165A CL = 15 pF* fmax tpd* SN54LV165A SN54LV165A 25.3 1 28 1 28 ns ns * On products compliant to MIL-PRF-38535 MIL-PRF-38535, this parameter is not production tested. switching characteristics over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE MIN TA = 25°C TYP MAX MIN MAX SN74LV165A SN74LV165A MIN CL = 15 pF* 65 115 55 60 90 50 50 CLK UNIT MHz 8.6 15.4 1 18 1 18 9.1 15.8 1 18.5 1 18.5 H 8.9 14.1 1 16.5 1 10.9 18.9 1 21.5 1 21.5 11.3 19.3 1 22 1 22 11.1 17.6 1 20 1 ns 16.5 CLK tpd SH/LD MAX 55 CL = 50 pF fmax tpd* SN54LV165A SN54LV165A 20 SH/LD QH or QH QH or QH CL = 15 pF CL = 50 pF H ns * On products compliant to MIL-PRF-38535 MIL-PRF-38535, this parameter is not production tested. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 5 SN54LV165A SN54LV165A, SN74LV165A SN74LV165A PARALLEL-LOAD 8-BIT SHIFT REGISTERS SCLS402B SCLS402B ­ APRIL 1998 ­ REVISED JULY 1998 switching characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) TA = 25°C TYP MAX 110 165 90 90 CL = 50 pF 95 125 85 85 CLK SH/LD MIN MAX UNIT MHz 11.5 1 1 11.5 1 11.5 1 10.5 1 10.5 11.9 1 13.5 1 13.5 7.7 CL = 50 pF 9 MAX 11.9 1 13.5 1 13.5 7.6 QH or QH 9.9 7.7 H 1 6 CL = 15 pF 9.9 6 QH or QH CLK SH/LD MIN 6 H tpd SN74LV165A SN74LV165A MIN CL = 15 pF* fmax tpd* SN54LV165A SN54LV165A LOAD CAPACITANCE 11.5 11 1 12.5 1 12.5 VCC 3.3 V TYP 5V 37.5 ns ns * On products compliant to MIL-PRF-38535 MIL-PRF-38535, this parameter is not production tested. operating characteristics, TA = 25°C PARAMETER Cpd Power dissipation ca acitance dissi ation capacitance TEST CONDITIONS CL = 50 pF F, PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 6 POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 f = 10 MHz 36.1 UNIT pF F SN54LV165A SN54LV165A, SN74LV165A SN74LV165A PARALLEL-LOAD 8-BIT SHIFT REGISTERS SCLS402B SCLS402B ­ APRIL 1998 ­ REVISED JULY 1998 PARAMETER MEASUREMENT INFORMATION RL = 1 k From Output Under Test Test Point From Output Under Test VCC Open S1 TEST GND CL (see Note A) CL (see Note A) S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain Open VCC GND VCC LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS VCC 50% VCC Timing Input 0V tw tsu VCC 50% VCC 50% VCC Input th VCC 50% VCC Data Input 50% VCC 0V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PULSE DURATION VCC 50% VCC Input 50% VCC tPLH In-Phase Output 50% VCC VOH 50% VCC VOL 50% VCC VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Output Waveform 2 S1 at GND (see Note B) 50% VCC 0V Output Waveform 1 S1 at VCC (see Note B) tPLH VOH 50% VCC VOL 50% VCC tPZL tPHL tPHL Out-of-Phase Output 0V VCC Output Control tPLZ 50% VCC tPZH VCC VOL + 0.3 V VOL tPHZ 50% VCC VOH ­ 0.3 V VOH 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO = 50 , tr 3 ns, tf 3 ns. D. The outputs are measured one at a time with one input transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPHL and tPLH are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 7 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. 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