SN54HC08 SN74HC08 SCLS081E SN74HC08N SN74HC08D SN74HC08DR SN74HC08DT - Datasheet Archive

 

QUADRUPLE 2INPUT POSITIVEAND GATES SCLS081E ­ DECEMBER 1982 ­ REVISED JULY 2003 D Wide Operating Voltage Range of 2 V to

 

SN54HC08 SN54HC08, SN74HC08 SN74HC08 QUADRUPLE 2INPUT POSITIVEAND GATES SCLS081E SCLS081E ­ DECEMBER 1982 ­ REVISED JULY 2003 D Wide Operating Voltage Range of 2 V to 6 V D Outputs Can Drive Up To 10 LSTTL Loads D Low Power Consumption, 20-µA Max ICC D Typical tpd = 8 ns D ±4-mA Output Drive at 5 V D Low Input Current of 1 µA Max SN54HC08 SN54HC08 . . . FK PACKAGE (TOP VIEW) 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4B 4A 4Y 3B 3A 3Y 1Y NC 2A NC 2B 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 4A NC 4Y NC 3B 2Y GND NC 3Y 3A 1A 1B 1Y 2A 2B 2Y GND 1B 1A NC VCC 4B SN54HC08 SN54HC08 . . . J OR W PACKAGE SN74HC08 SN74HC08 . . . D, N, NS, OR PW PACKAGE (TOP VIEW) NC ­ No internal connection description/ordering information The 'HC08 devices contain four independent 2-input AND gates. They perform the Boolean function Y + A · B or Y + A ) B in positive logic. ORDERING INFORMATION PACKAGE TA PDIP ­ N ORDERABLE PART NUMBER TOP-SIDE MARKING Tube of 25 SN74HC08N SN74HC08N Tube of 50 SN74HC08D SN74HC08D Reel of 2500 SN74HC08DR SN74HC08DR Reel of 250 SN74HC08DT SN74HC08DT Reel of 2000 SN74HC08NSR SN74HC08NSR Tube of 90 SN74HC08PW SN74HC08PW Reel of 2000 SN74HC08PWR SN74HC08PWR Reel of 250 SN74HC08PWT SN74HC08PWT CDIP ­ J Tube of 25 SNJ54HC08J SNJ54HC08J SNJ54HC08J SNJ54HC08J CFP ­ W Tube of 150 SNJ54HC08W SNJ54HC08W SNJ54HC08W SNJ54HC08W LCCC ­ FK Tube of 55 SNJ54HC08FK SNJ54HC08FK SOIC ­ D ­40°C to 85°C 40°C SOP ­ NS TSSOP ­ PW ­55°C to 125°C SN74HC08N SN74HC08N HC08 HC08 HC08 SNJ54HC08FK SNJ54HC08FK Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2003, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. On products compliant to MILPRF38535 MILPRF38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 1 SN54HC08 SN54HC08, SN74HC08 SN74HC08 QUADRUPLE 2INPUT POSITIVEAND GATES SCLS081E SCLS081E ­ DECEMBER 1982 ­ REVISED JULY 2003 FUNCTION TABLE (each gate) INPUTS A B OUTPUT Y H H H L X L X L L logic diagram (positive logic) A Y B absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ­0.5 V to 7 V Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Package thermal impedance, JA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ­65°C to 150°C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 3) SN54HC08 SN54HC08 SN74HC08 SN74HC08 MIN VCC VIH High level input High-level in ut voltage VCC = 2 V VCC = 4.5 V VI VO t/v Low level input Low-level in ut voltage 6 NOM MAX 2 5 6 1.5 3.15 3.15 V 4.2 V 0 VCC = 2 V VCC = 4.5 V 1.35 1.8 0 0.5 1.35 VCC = 4.5 V VCC = 6 V Output voltage UNIT 1.5 0.5 Input voltage Input transition rise/fall time In ut 5 MIN 4.2 VCC = 6 V VCC = 2 V VIL MAX 2 Supply voltage NOM 1.8 VCC VCC 0 0 VCC VCC 500 500 V V 1000 400 VCC = 6 V 1000 V 400 ns TA Operating free-air temperature ­55 125 ­40 85 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004 SCBA004. 2 POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 SN54HC08 SN54HC08, SN74HC08 SN74HC08 QUADRUPLE 2INPUT POSITIVEAND GATES SCLS081E SCLS081E ­ DECEMBER 1982 ­ REVISED JULY 2003 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TA = 25°C TYP MAX SN54HC08 SN54HC08 SN74HC08 SN74HC08 MIN MIN MAX 2V VOH VI = VIH or VIL IOH = ­4 mA IOH = ­5.2 mA 1.9 1.998 1.9 4.4 4.499 4.4 4.4 5.9 5.999 5.9 5.9 4.5 V 3.98 4.3 3.7 3.84 6V 5.48 UNIT 1.9 4.5 V 6V IOH = ­20 µA 20 MAX 5.8 5.2 V 5.34 2V IOL = 4 mA IOL = 5.2 mA II ICC VI = VCC or 0 VI = VCC or 0, IO = 0 0.1 0.1 4.5 V 0.001 0.1 0.1 0.1 0.001 0.1 0.1 0.1 4.5 V 0.17 0.26 0.4 0.33 6V 0.15 0.26 0.4 0.33 6V VI = VIH or VIL 0.1 6V IOL = 20 µA VOL 0.002 ±0.1 ±100 ±1000 ±1000 nA 2 40 20 µA 3 10 10 10 pF 6V Ci 2 V to 6 V V switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) TA = 25°C TYP MAX SN54HC08 SN54HC08 SN74HC08 SN74HC08 MIN MIN PARAMETER FROM (INPUT) TO (OUTPUT) VCC 2V 50 100 150 125 tpd d A or B Y 4.5 V 10 20 30 25 6V 8 17 25 21 MIN MAX MAX 2V Y 38 75 110 8 15 22 19 6 13 19 ns 95 4.5 V 6V tt UNIT 16 ns operating characteristics, TA = 25°C PARAMETER Cpd TEST CONDITIONS Power dissipation capacitance per gate POST OFFICE BOX 655303 No load · DALLAS, TEXAS 75265 TYP 20 UNIT pF 3 SN54HC08 SN54HC08, SN74HC08 SN74HC08 QUADRUPLE 2INPUT POSITIVEAND GATES SCLS081E SCLS081E ­ DECEMBER 1982 ­ REVISED JULY 2003 PARAMETER MEASUREMENT INFORMATION From Output Under Test Test Point Input VCC 50% 50% 0V CL = 50 pF (see Note A) tPLH In-Phase Output LOAD CIRCUIT 50% 10% tPHL 90% 90% tr Input 50% 10% 90% 90% tr VCC 50% 10% 0 V tPHL Out-of-Phase Output 90% tf VOH 50% 10% VOL tf tPLH 50% 10% tf 50% 10% 90% VOH VOL tr VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES VOLTAGE WAVEFORM INPUT RISE AND FALL TIMES NOTES: A. CL includes probe and test-fixture capacitance. B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO = 50 , tr = 6 ns, tf = 6 ns. C. The outputs are measured one at a time with one input transition per measurement. D. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms 4 POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 MECHANICAL DATA MCFP002A MCFP002A ­ JANUARY 1995 ­ REVISED FEBRUARY 2002 W (R-GDFP-F14 R-GDFP-F14) CERAMIC DUAL FLATPACK Base and Seating Plane 0.260 (6,60) 0.235 (5,97) 0.045 (1,14) 0.026 (0,66) 0.008 (0,20) 0.004 (0,10) 0.080 (2,03) 0.045 (1,14) 0.280 (7,11) MAX 1 0.019 (0,48) 0.015 (0,38) 14 0.050 (1,27) 0.390 (9,91) 0.335 (8,51) 0.005 (0,13) MIN 4 Places 7 8 0.360 (9,14) 0.250 (6,35) 0.360 (9,14) 0.250 (6,35) 4040180-2 / C 02/02 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a ceramic lid using glass frit. Index point is provided on cap for terminal identification only. Falls within MIL STD 1835 GDFP1-F14 GDFP1-F14 and JEDEC MO-092AB MO-092AB POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 1 MECHANICAL DATA MLCC006B MLCC006B ­ OCTOBER 1996 FK (S-CQCC-N*) LEADLESS CERAMIC CHIP CARRIER 28 TERMINAL SHOWN 18 17 16 15 14 13 NO. OF TERMINALS * 12 A B 11 20 MAX MIN MAX 20 0.342 (8,69) 0.358 (9,09) 0.307 (7,80) 0.358 (9,09) 28 19 MIN 0.442 (11,23) 0.458 (11,63) 0.406 (10,31) 0.458 (11,63) 10 21 9 22 8 44 0.640 (16,26) 0.660 (16,76) 0.495 (12,58) 0.560 (14,22) 23 7 52 0.739 (18,78) 0.761 (19,32) 0.495 (12,58) 0.560 (14,22) 24 6 68 0.938 (23,83) 0.962 (24,43) 0.850 (21,6) 0.858 (21,8) 84 1.141 (28,99) 1.165 (29,59) 1.047 (26,6) 1.063 (27,0) B SQ A SQ 25 5 26 27 28 1 2 3 4 0.080 (2,03) 0.064 (1,63) 0.020 (0,51) 0.010 (0,25) 0.020 (0,51) 0.010 (0,25) 0.055 (1,40) 0.045 (1,14) 0.045 (1,14) 0.035 (0,89) 0.045 (1,14) 0.035 (0,89) 0.028 (0,71) 0.022 (0,54) 0.050 (1,27) 4040140 / D 10/96 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a metal lid. The terminals are gold plated. Falls within JEDEC MS-004 MS-004 POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 1 MECHANICAL MPDI002C MPDI002C ­ JANUARY 1995 ­ REVISED DECEMBER 20002 N (R-PDIP-T*) PLASTIC DUAL-IN-LINE PACKAGE 16 PINS SHOWN PINS * 14 16 18 20 A MAX 0.775 (19,69) 0.775 (19,69) 0.920 (23,37) 1.060 (26,92) A MIN 0.745 (18,92) 0.745 (18,92) 0.850 (21,59) 0.940 (23,88) MS-100 MS-100 VARIATION AA BB AC DIM A 16 9 0.260 (6,60) 0.240 (6,10) 1 C AD 8 0.070 (1,78) 0.045 (1,14) 0.045 (1,14) 0.030 (0,76) D D 0.325 (8,26) 0.300 (7,62) 0.020 (0,51) MIN 0.015 (0,38) Gauge Plane 0.200 (5,08) MAX Seating Plane 0.010 (0,25) NOM 0.125 (3,18) MIN 0.100 (2,54) 0.430 (10,92) MAX 0.021 (0,53) 0.015 (0,38) 0.010 (0,25) M 14/18 PIN ONLY 20 pin vendor option D 4040049/E 4040049/E 12/2002 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-001 MS-001, except 18 and 20 pin minimum body lrngth (Dim A). D. The 20 pin end lead shoulder width is a vendor option, either half or full width. POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 1 MECHANICAL DATA MSOI002B MSOI002B ­ JANUARY 1995 ­ REVISED SEPTEMBER 2001 D (R-PDSO-G*) PLASTIC SMALL-OUTLINE PACKAGE 8 PINS SHOWN 0.020 (0,51) 0.014 (0,35) 0.050 (1,27) 8 0.010 (0,25) 5 0.008 (0,20) NOM 0.244 (6,20) 0.228 (5,80) 0.157 (4,00) 0.150 (3,81) Gage Plane 1 4 0.010 (0,25) 0°­ 8° A 0.044 (1,12) 0.016 (0,40) Seating Plane 0.010 (0,25) 0.004 (0,10) 0.069 (1,75) MAX PINS * 0.004 (0,10) 8 14 16 A MAX 0.197 (5,00) 0.344 (8,75) 0.394 (10,00) A MIN 0.189 (4,80) 0.337 (8,55) 0.386 (9,80) DIM 4040047/E 4040047/E 09/01 NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15). Falls within JEDEC MS-012 MS-012 POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 1 MECHANICAL DATA MTSS001C MTSS001C ­ JANUARY 1995 ­ REVISED FEBRUARY 1999 PW (R-PDSO-G*) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°­ 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS * 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. 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