SN54ABT821 SN74ABT821 10-BIT SCBS193A MIL-STD-883C JESD-17 SCBD002B MIL-STD-883 - Datasheet Archive

 

10-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS SCBS193A ­ FEBRUARY 1991 ­ REVISED JULY 1994 · ·

 

SN54ABT821 SN54ABT821, SN74ABT821 SN74ABT821 10-BIT 10-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS SCBS193A SCBS193A ­ FEBRUARY 1991 ­ REVISED JULY 1994 · · · · · · State-of-the-Art EPIC-B TM BiCMOS Design Significantly Reduces Power Dissipation ESD Protection Exceeds 2000 V Per MIL-STD-883C MIL-STD-883C, Method 3015 Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 JESD-17 Typical VOLP (Output Ground Bounce) < 1 V at VCC = 5 V, TA = 25°C High-Drive Outputs (­ 32-mA IOH, 64-mA IOL ) Package Options Include Plastic Small-Outline (DW) and Shrink Small-Outline (DB) Packages, Ceramic Chip Carriers (FK), and Plastic (NT) and Ceramic (JT) DIPs SN54ABT821 SN54ABT821 . . . JT PACKAGE SN74ABT821 SN74ABT821 . . . DB, DW, OR NT PACKAGE (TOP VIEW) OE 1D 2D 3D 4D 5D 6D 7D 8D 9D 10D GND description The ten flip-flops are edge-triggered D-type flip-flops. On the positive transition of the clock (CLK) input, the device provides true data at the Q outputs. A buffered output-enable (OE) input can be used to place the ten outputs in either a normal logic state (high or low level) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components. 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 VCC 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q 9Q 10Q CLK 2D 1D OE NC VCC 1Q 2Q SN54ABT821 SN54ABT821 . . . FK PACKAGE (TOP VIEW) 4 3D 4D 5D NC 6D 7D 8D 5 3 2 1 28 27 26 25 6 24 7 23 8 22 9 21 10 20 19 11 12 13 14 15 16 17 18 3Q 4Q 5Q NC 6Q 7Q 8Q 9D 10D GND NC CLK 10Q 9Q These 10-bit flip-flops feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing wider buffer registers, I/O ports, bidirectional bus drivers with parity, and working registers. 1 NC ­ No internal connection OE does not affect the internal operations of the latch. Previously stored data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN74ABT821 SN74ABT821 is available in TI's shrink small-outline package (DB), which provides the same I/O pin count and functionality of standard small-outline packages in less than half the printed-circuit-board area. The SN54ABT821 SN54ABT821 is characterized for operation over the full military temperature range of ­ 55°C to 125°C. The SN74ABT821 SN74ABT821 is characterized for operation from ­ 40°C to 85°C. EPIC-B is a trademark of Texas Instruments Incorporated. Copyright © 1994, Texas Instruments Incorporated UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 2­1 SN54ABT821 SN54ABT821, SN74ABT821 SN74ABT821 10-BIT 10-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS SCBS193A SCBS193A ­ FEBRUARY 1991 ­ REVISED JULY 1994 FUNCTION TABLE (each flip-flop) INPUTS OE CLK D OUTPUT Q L H H L L L L H or L X Q0 H X X Z logic symbol OE CLK 1D 2D 3D 4D 5D 6D 7D 8D 9D 10D 1 EN 13 2 C2 23 2D 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q 9Q 10Q This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. logic diagram (positive logic) OE CLK 1 13 C1 1D 2 1D To Nine Other Channels Pin numbers shown are for the DB, DW, JT, and NT packages. 2­2 POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 23 1Q SN54ABT821 SN54ABT821, SN74ABT821 SN74ABT821 10-BIT 10-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS SCBS193A SCBS193A ­ FEBRUARY 1991 ­ REVISED JULY 1994 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ­ 0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ­ 0.5 V to 7 V Voltage range applied to any output in the high state or power-off state, VO . . . . . . . . . . . . . ­ 0.5 V to 5.5 V Current into any output in the low state, IO: SN54ABT821 SN54ABT821 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA SN74ABT821 SN74ABT821 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ­18 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ­ 50 mA Maximum power dissipation at TA = 55°C (in still air) (see Note 2): DB package . . . . . . . . . . . . . . . . . . . 0.65 W DW package . . . . . . . . . . . . . . . . . . . 1.7 W NT package . . . . . . . . . . . . . . . . . . . . 1.3 W Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ­ 65°C to 150°C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions beyond those indicated in the "recommended operating conditions" section of this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils, except for the NT package, which has a trace length of zero. For more information, refer to the Package Thermal Considerations application note in the 1994 ABT Advanced BiCMOS Technology Data Book, literature number SCBD002B SCBD002B. recommended operating conditions (see Note 3) SN54ABT821 SN54ABT821 SN74ABT821 SN74ABT821 MIN MAX MIN MAX 4.5 5.5 4.5 5.5 UNIT VCC VIH Supply voltage VIL VI Low-level input voltage IOH IOL High-level output current VCC ­ 24 Low-level output current 48 64 mA t /v Input transition rise or fall rate 10 10 ns / V t /VCC Power-up ramp rate High-level input voltage 2 2 0.8 Input voltage 0 200 TA Operating free-air temperature NOTE 3: Unused or floating inputs must be held high or low. ­ 55 V 0.8 0 VCC ­ 32 ­ 40 V V mA µs / V 200 125 V 85 °C PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 2­3 SN54ABT821 SN54ABT821, SN74ABT821 SN74ABT821 10-BIT 10-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS SCBS193A SCBS193A ­ FEBRUARY 1991 ­ REVISED JULY 1994 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK TEST CONDITIONS VCC = 4.5 V, VCC = 4.5 V, II = ­18 mA IOH = ­ 3 mA VCC = 5 V, VOH MIN VCC = 4 5 V 4.5 VOL VCC = 4 5 V 4.5 II IOZPU VCC = 5.5 V, VCC = 0 to 2.1 V, IOZPD IOZH VCC = 2.1 V to 0, VCC = 2.1 V to 5.5 V, IOZL Ioff VCC = 2.1 V to 5.5 V, VCC = 0, ICEX IO VCC = 5.5 V, VCC = 5.5 V, ICC SN54ABT821 SN54ABT821 MIN ­1.2 SN74ABT821 SN74ABT821 MAX MIN ­1.2 MAX ­1.2 2.5 2.5 IOH = ­ 3 mA IOH = ­ 24 mA 3 3 3 2 2 IOH = ­ 32 mA IOL = 48 mA 2* UNIT V 2.5 V 2 0.55 IOL = 64 mA VI = VCC or GND 0.55 0.55* 0.55 V ±1 ±1 ±1 µA VO = 0.5 to 2.7 V, VO = 0.5 to 2.7 V, OE = X ± 50 ± 50 ± 50 µA OE = X ± 50 ± 50 ± 50 µA VO = 2.7 V, VO = 0.5 V, OE 2 V 10 10 10 µA ­ 10 ­ 10 OE 2 V VI or VO 4.5 V VO = 5.5 V Outputs high 50 VO = 2.5 V IO = 0, 0 ­ 10 ­ 50 ­140 ­180 1 250 ­ 50 ­ 50 250 µA ­180 mA 250 ­180 µA 50 50 µA ±100 ±100 Outputs high VCC = 5.5 V, 55V VI = VCC or GND TA = 25°C TYP MAX µA Outputs low 24 38 38 38 mA Outputs disabled 0.5 250 250 250 µA 1.5 1.5 1.5 mA ICC§ VCC = 5.5 V, One input at 3.4 V, Other inputs at VCC or GND Ci VI = 2.5 V or 0.5 V VO = 2.5 V or 0.5 V 4 pF Co 7 * On products compliant to MIL-STD-883 MIL-STD-883, Class B, this parameter does not apply. All typical values are at VCC = 5 V. Not more than one output should be tested at a time, and the duration of the test should not exceed one second. § This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND. pF timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 1) VCC = 5 V, TA = 25°C MIN fclock 0 Clock frequency MAX 125 SN54ABT821 SN54ABT821 MIN MAX 0 125 SN74ABT821 SN74ABT821 MIN 0 125 UNIT MAX High 2.9 2.9 2.9 Low 3.8 3.8 3.8 MHz tw Pulse duration CLK high or low duration, tsu th Setup time, data before CLK 2.1 2.1 2.1 ns Hold time, data after CLK 1.3 1.3 1.3 ns PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 2­4 POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 ns SN54ABT821 SN54ABT821, SN74ABT821 SN74ABT821 10-BIT 10-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS SCBS193A SCBS193A ­ FEBRUARY 1991 ­ REVISED JULY 1994 switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER fmax tPLH tPHL tPZH tPZL tPHZ FROM (INPUT) TO (OUTPUT) CLK Q OE Q OE tPLZ This data sheet limit may vary among suppliers. Q VCC = 5 V, TA = 25°C MIN TYP SN54ABT821 SN54ABT821 MAX MIN SN74ABT821 SN74ABT821 MAX MIN 6.2 125 1.6 4.1 5.6 125 1.6 6.9 125 1.6 2.1 4.6 6.2 2.1 6.9 2.1 6.7 1 3 4.5 1 6 1 5.3 2.2 4.1 5.6 2.2 6.5 2.2 6.3 2.7 1.7 4.7 6.2 2.7 1.7 6.7 6.1 2.7 1.7 7 4.6 7 UNIT MAX MHz 6.5 ns ns ns PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 2­5 SN54ABT821 SN54ABT821, SN74ABT821 SN74ABT821 10-BIT 10-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS SCBS193A SCBS193A ­ FEBRUARY 1991 ­ REVISED JULY 1994 PARAMETER MEASUREMENT INFORMATION 7V S1 500 From Output Under Test Open TEST CL = 50 pF (see Note A) 500 S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH GND Open 7V Open LOAD CIRCUIT FOR OUTPUTS 3V Timing Input 1.5 V 0V tw tsu 3V 1.5 V Input th 3V 1.5 V Data Input 1.5 V 1.5 V 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 3V Input (see Note B) 1.5 V 0V VOH 1.5 V Output 1.5 V VOL VOH Output 1.5 V 1.5 V VOL 1.5 V 0V tPLZ Output Waveform 1 S1 at 7 V (see Note C) tPLH tPHL 1.5 V tPZL tPHL tPLH 3V Output Control 1.5 V Output Waveform 2 S1 at Open (see Note C) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 1.5 V tPZH 3.5 V VOL + 0.3 V VOL tPHZ 1.5 V VOH ­ 0.3 V VOH [0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2.5 ns, tf 2.5 ns. C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. D. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuit and Voltage Waveforms 2­6 POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 15-Oct-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty 5962-9469101Q3A 5962-9469101Q3A ACTIVE LCCC FK 28 1 TBD 5962-9469101QKA 5962-9469101QKA ACTIVE CFP W 24 1 TBD 1 Lead/Ball Finish MSL Peak Temp (3) POST-PLATE N / A for Pkg Type A42 N / A for Pkg Type N / A for Pkg Type 5962-9469101QLA 5962-9469101QLA ACTIVE CDIP JT 24 TBD A42 SN74ABT821DBLE SN74ABT821DBLE OBSOLETE SSOP DB 24 TBD Call TI Call TI SN74ABT821DW SN74ABT821DW OBSOLETE SOIC DW 24 TBD Call TI Call TI SN74ABT821DWR SN74ABT821DWR OBSOLETE SOIC DW 24 TBD Call TI Call TI SN74ABT821NT SN74ABT821NT OBSOLETE PDIP NT 24 TBD Call TI Call TI SNJ54ABT821FK SNJ54ABT821FK ACTIVE LCCC FK 28 1 TBD SNJ54ABT821JT SNJ54ABT821JT ACTIVE CDIP JT 24 1 TBD A42 N / A for Pkg Type SNJ54ABT821W SNJ54ABT821W ACTIVE CFP W 24 1 TBD A42 N / A for Pkg Type POST-PLATE N / A for Pkg Type (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 MECHANICAL DATA MSSO002E MSSO002E ­ JANUARY 1995 ­ REVISED DECEMBER 2001 DB (R-PDSO-G*) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°­8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS * 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-150 MO-150 POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 MECHANICAL DATA MLCC006B MLCC006B ­ OCTOBER 1996 FK (S-CQCC-N*) LEADLESS CERAMIC CHIP CARRIER 28 TERMINAL SHOWN 18 17 16 15 14 13 NO. OF TERMINALS * 12 A B 11 20 MAX MIN MAX 20 0.342 (8,69) 0.358 (9,09) 0.307 (7,80) 0.358 (9,09) 28 19 MIN 0.442 (11,23) 0.458 (11,63) 0.406 (10,31) 0.458 (11,63) 10 21 9 22 8 44 0.640 (16,26) 0.660 (16,76) 0.495 (12,58) 0.560 (14,22) 23 7 52 0.739 (18,78) 0.761 (19,32) 0.495 (12,58) 0.560 (14,22) 24 6 68 0.938 (23,83) 0.962 (24,43) 0.850 (21,6) 0.858 (21,8) 84 1.141 (28,99) 1.165 (29,59) 1.047 (26,6) 1.063 (27,0) B SQ A SQ 25 5 26 27 28 1 2 3 4 0.080 (2,03) 0.064 (1,63) 0.020 (0,51) 0.010 (0,25) 0.020 (0,51) 0.010 (0,25) 0.055 (1,40) 0.045 (1,14) 0.045 (1,14) 0.035 (0,89) 0.045 (1,14) 0.035 (0,89) 0.028 (0,71) 0.022 (0,54) 0.050 (1,27) 4040140 / D 10/96 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a metal lid. The terminals are gold plated. Falls within JEDEC MS-004 MS-004 POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 MECHANICAL DATA MCFP007 MCFP007 ­ OCTOBER 1994 W (R-GDFP-F24 R-GDFP-F24) CERAMIC DUAL FLATPACK 0.375 (9,53) 0.340 (8,64) Base and Seating Plane 0.006 (0,15) 0.004 (0,10) 0.090 (2,29) 0.045 (1,14) 0.045 (1,14) 0.026 (0,66) 0.395 (10,03) 0.360 (9,14) 0.360 (9,14) 0.240 (6,10) 1 0.360 (9,14) 0.240 (6,10) 24 0.019 (0,48) 0.015 (0,38) 0.050 (1,27) 0.640 (16,26) 0.490 (12,45) 0.030 (0,76) 0.015 (0,38) 12 13 30° TYP 1.115 (28,32) 0.840 (21,34) 4040180-5 / B 03/95 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a ceramic lid using glass frit. Falls within MIL-STD-1835 MIL-STD-1835 GDFP2-F24 GDFP2-F24 and JEDEC MO-070AD MO-070AD Index point is provided on cap for terminal identification only. POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 MECHANICAL DATA MCER004A MCER004A ­ JANUARY 1995 ­ REVISED JANUARY 1997 JT (R-GDIP-T*) CERAMIC DUAL-IN-LINE 24 LEADS SHOWN PINS * A 1.280 (32,51) 1.460 (37,08) A MIN 1.240 (31,50) 1.440 (36,58) B MAX 0.300 (7,62) 0.291 (7,39) B MIN B 1 28 A MAX 13 24 24 0.245 (6,22) 0.285 (7,24) DIM 12 0.070 (1,78) 0.030 (0,76) 0.100 (2,54) MAX 0.320 (8,13) 0.290 (7,37) 0.015 (0,38) MIN 0.200 (5,08) MAX Seating Plane 0.130 (3,30) MIN 0.023 (0,58) 0.015 (0,38) 0°­15° 0.014 (0,36) 0.008 (0,20) 0.100 (2,54) 4040110/C 4040110/C 08/96 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a ceramic lid using glass frit. Index point is provided on cap for terminal identification. Falls within MIL STD 1835 GDIP3-T24 GDIP3-T24, GDIP4-T28 GDIP4-T28, and JEDEC MO-058 MO-058 AA, MO-058 MO-058 AB POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. 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