SN54ABT543A SN74ABT543A SCBS157F MIL-STD-883 ABT543A JESD51 MIL-PRF-38535 - Datasheet Archive

 

OCTAL REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS157F ­ JANUARY 1991 ­ REVISED MAY 1997 D D D D D State-of-the-Art

 

SN54ABT543A SN54ABT543A, SN74ABT543A SN74ABT543A OCTAL REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS157F SCBS157F ­ JANUARY 1991 ­ REVISED MAY 1997 D D D D D State-of-the-Art EPIC-B TM BiCMOS Design Significantly Reduces Power Dissipation ESD Protection Exceeds 2000 V Per MIL-STD-883 MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Typical VOLP (Output Ground Bounce) < 1 V at VCC = 5 V, TA = 25°C High-Drive Outputs (­32-mA IOH, 64-mA IOL) Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW) Packages, Ceramic Chip Carriers (FK), Ceramic Flat (W) Package, and Plastic (NT) and Ceramic (JT) DIPs SN54ABT543A SN54ABT543A . . . JT OR W PACKAGE SN74ABT543A SN74ABT543A . . . DB, DW, NT, OR PW PACKAGE (TOP VIEW) LEBA OEBA A1 A2 A3 A4 A5 A6 A7 A8 CEAB GND 1 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 VCC CEBA B1 B2 B3 B4 B5 B6 B7 B8 LEAB OEAB 24 2 13 description The A-to-B enable (CEAB) input must be low to enter data from A or to output data from B. If CEAB is low and LEAB is low, the A-to-B latches are transparent; a subsequent low-to-high transition of LEAB puts the A latches in the storage mode. With CEAB and OEAB both low, the 3-state B outputs are active and reflect the data present at the output of the A latches. Data flow from B to A is similar, but requires using the CEBA, LEBA, and OEBA inputs. 4 A2 A3 A4 NC A5 A6 A7 CEBA B1 A1 OEBA LEBA NC VCC SN54ABT543A SN54ABT543A . . . FK PACKAGE (TOP VIEW) 5 3 2 1 28 27 26 25 6 24 7 23 8 22 9 21 10 20 19 11 12 13 14 15 16 17 18 B2 B3 B4 NC B5 B6 B7 A8 CEAB GND NC OEAB LEAB B8 The 'ABT543A ABT543A octal transceivers contain two sets of D-type latches for temporary storage of data flowing in either direction. Separate latch-enable (LEAB or LEBA) and output-enable (OEAB or OEBA) inputs are provided for each register to permit independent control in either direction of data flow. NC ­ No internal connection To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN54ABT543A SN54ABT543A is characterized for operation over the full military temperature range of ­55°C to 125°C. The SN74ABT543A SN74ABT543A is characterized for operation from ­40°C to 85°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC-B is a trademark of Texas Instruments Incorporated. Copyright © 1997, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 1 SN54ABT543A SN54ABT543A, SN74ABT543A SN74ABT543A OCTAL REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS157F SCBS157F ­ JANUARY 1991 ­ REVISED MAY 1997 FUNCTION TABLE INPUTS OEAB A OUTPUT B CEAB LEAB H X X X Z X X H X Z L H L X L L L L B0 L L L L H H A-to-B data flow is shown; B-to-A flow control is the same except that it uses CEBA, LEBA, and OEBA. Output level before the indicated steady-state input conditions were established logic symbol§ OEBA CEBA LEBA 2 1EN3 23 1 1C5 13 OEAB 11 CEAB 14 LEAB A1 A2 A3 A4 A5 A6 A7 A8 G1 2EN4 G2 2C6 3 3 5D 6D 4 1 1 4 21 5 20 6 19 7 18 8 17 9 16 10 15 § This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the DB, DW, JT, NT, PW, and W packages. 2 22 POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 B1 B2 B3 B4 B5 B6 B7 B8 SN54ABT543A SN54ABT543A, SN74ABT543A SN74ABT543A OCTAL REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS157F SCBS157F ­ JANUARY 1991 ­ REVISED MAY 1997 logic diagram (positive logic) OEBA CEBA LEBA OEAB CEAB LEAB A1 2 23 1 13 11 14 C1 3 1D 22 B1 C1 1D To Seven Other Channels Pin numbers shown are for the DB, DW, JT, NT, PW, and W packages. absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ­0.5 V to 7 V Input voltage range, VI (except I/O ports) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ­0.5 V to 7 V Voltage range applied to any output in the high or power-off state, VO . . . . . . . . . . . . . . . . . . . ­0.5 V to 5.5 V Current into any output in the low state, IO: SN54ABT543A SN54ABT543A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA SN74ABT543A SN74ABT543A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ­18 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ­50 mA Package thermal impedance, JA (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104°C/W DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81°C/W NT package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ­65°C to 150°C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51 JESD51, except for through-hole packages, which use a trace length of zero. POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 3 SN54ABT543A SN54ABT543A, SN74ABT543A SN74ABT543A OCTAL REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS157F SCBS157F ­ JANUARY 1991 ­ REVISED MAY 1997 recommended operating conditions (see Note 3) SN54ABT543A SN54ABT543A SN74ABT543A SN74ABT543A MIN Supply voltage VIL VI Input transition rise or fall rate 5.5 4.5 5.5 High-level output current t/v MAX Low-level input voltage IOH IOL MIN 4.5 VCC VIH MAX High-level input voltage 2 2 0.8 Input voltage 0 Low-level output current 0 V V 0.8 VCC ­24 UNIT VCC ­32 V V mA 48 TA Operating free-air temperature NOTE 3: Unused pins (input or I/O) must be held high or low to prevent them from floating. ­55 64 mA 5 Outputs enabled 5 ns/V 85 °C 125 ­40 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK TEST CONDITIONS VCC = 4.5 V, VCC = 4.5 V, VCC = 5 V, VOH II = ­18 mA IOH = ­3 mA VCC = 4 5 V 4.5 VOL VCC = 4 5 V 4.5 MIN MIN ­1.2 MAX SN74ABT543A SN74ABT543A MIN ­1.2 IOH = ­3 mA IOH = ­24 mA 3 3 3 2 2 IOH = ­32 mA IOL = 48 mA 2* UNIT V 2.5 V 2 0.55 IOL = 64 mA 0.55 0.55* 0.55 100 V mV ±1 ±1 ±1 VO = 2.7 V VO = 0.5 V ±100 10§ ±100 10§ ±100 10§ ­10§ ­10§ ­10§ µA VCC = 0, VCC = 5.5 V, VO = 5.5 V VI or VO 4.5 V ±100 ±100 µA 50 µA VCC = 5.5 V, Control inputs VO = 2.5 V Outputs high ­180 mA VI = VCC or GND IOZH IOZL VCC = 5.5 V, VCC = 5.5 V, Ioff A or B ports ICEX IO¶ A or B ports p VCC = 5.5 V, IO = 0, VI = VCC or GND Outputs high 50 ­50* ­100 ­180* Ci Control inputs Cio A or B ports 50 ­50 ­200 ­50 µA µA 1 250* 350 250 µA Outputs low 24 30* 34 30 mA Outputs disabled 0.5 250* 350 250 µA 1.5 1.5 1.5 mA VCC = 5.5 V, One input at 3.4 V, Other inputs at VCC or GND ICC# VI = 2.5 V or 0.5 V VO = 2.5 V or 0.5 V 4 pF 7 pF * On products compliant to MIL-PRF-38535 MIL-PRF-38535, this parameter does not apply. All typical values are at VCC = 5 V. The parameters IOZH and IOZL include the input leakage current. § This data sheet limit may vary among suppliers. ¶ Not more than one output should be tested at a time, and the duration of the test should not exceed one second. # This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND. 4 MAX ­1.2 2.5 VCC = 5 5 V 5.5 V, ICC SN54ABT543A SN54ABT543A 2.5 Vhys II TA = 25°C TYP MAX POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 SN54ABT543A SN54ABT543A, SN74ABT543A SN74ABT543A OCTAL REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS157F SCBS157F ­ JANUARY 1991 ­ REVISED MAY 1997 timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 1) SN54ABT543A SN54ABT543A VCC = 5 V, TA = 25°C MIN tw Pulse duration, LEAB or LEBA low MIN 3.5 Data before CEAB or CEBA th Hold time 3.5 2.5 2.5 Low 3 3 High Data before LEAB or LEBA Setup time S i UNIT MAX High tsu MAX 2.5 2.5 Low 3 1 1 Data after CEAB or CEBA 1 ns 3 Data after LEAB or LEBA ns 1 ns timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 1) SN74ABT543A SN74ABT543A VCC = 5 V, TA = 25°C MIN tw Pulse duration, LEAB or LEBA low MIN Data before CEAB or CEBA th Hold time 3.5 3.5 Low 3 3 High S i Setup time 3.5 High tsu UNIT MAX 3.5 Data before LEAB or LEBA MAX 3.5 3.5 3 0.5 0.5 Data after CEAB or CEBA 0.5 0.5 POST OFFICE BOX 655303 Low ns 3 Data after LEAB or LEBA ns · DALLAS, TEXAS 75265 ns 5 SN54ABT543A SN54ABT543A, SN74ABT543A SN74ABT543A OCTAL REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS157F SCBS157F ­ JANUARY 1991 ­ REVISED MAY 1997 switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL = 50 pF (unless otherwise noted) (see Figure 1) SN54ABT543A SN54ABT543A PARAMETER FROM (INPUT) TO (OUTPUT) tPLH tPHL A or B B or A tPLH tPHL LEBA or LEAB A or B tPZH tPZL OEBA or OEAB A or B tPHZ tPLZ OEBA or OEAB A or B tPZH tPZL CEBA or CEAB A or B tPHZ tPLZ CEBA or CEAB A or B VCC = 5 V, TA = 25°C MIN MAX MIN 1.6 TYP MAX 4.4 4.4 1.6 5.5 1.6 1.6 4.4 5.1 6.2 4.1 5.1 1.6 1.6 1.6 4.6 5.4 1.6 6.4 1.4 3.9 4.1 1.4 5.1 2 2.5 5 4.9 5.8 5.9 5.8 2 2.5 2.5 5.5 6.1 2.5 7.6 1.4 3.9 4.7 1.4 5.6 2 3.2 5 5.7 6.2 5.9 6.5 2 3.2 2.5 5.5 6.7 2.5 7.8 UNIT 6.6 6.9 7.3 ns ns ns ns ns ns This data sheet limit may vary among suppliers. switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL = 50 pF (unless otherwise noted) (see Figure 1) SN74ABT543A SN74ABT543A PARAMETER FROM (INPUT) TO (OUTPUT) tPLH tPHL A or B B or A tPLH tPHL LEBA or LEAB A or B tPZH tPZL OEBA or OEAB A or B tPHZ tPLZ OEBA or OEAB A or B tPZH tPZL CEBA or CEAB A or B tPHZ tPLZ CEBA or CEAB A or B This data sheet limit may vary among suppliers. 6 POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 VCC = 5 V, TA = 25°C MIN MAX MIN 1.8 TYP MAX 4.4 5.9 1.8 6.9 1.9 1.5 4.4 5.9 6.9 4.1 5.6 1.9 1.5 2.1 4.6 6.1 2.1 7.1 1.4 3.9 5.4 1.4 6.4 2.5 2.5 5 6.5 7.5 5.9 7.4 2.5 2.5 2.5 5.5 7 2.5 8 1.4 3.9 5.4 1.4 6.4 2.5 2.9 5 6.5 7.5 5.9 7.4 2.5 2.9 2.4 5.5 7 2.4 8 UNIT 6.6 8.4 8.4 ns ns ns ns ns ns SN54ABT543A SN54ABT543A, SN74ABT543A SN74ABT543A OCTAL REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS157F SCBS157F ­ JANUARY 1991 ­ REVISED MAY 1997 PARAMETER MEASUREMENT INFORMATION 7V S1 500 From Output Under Test Open TEST CL = 50 pF (see Note A) 500 S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH GND Open 7V Open LOAD CIRCUIT 3V Timing Input 1.5 V 0V tw tsu 3V Input 1.5 V th 3V 1.5 V Data Input 1.5 V 1.5 V 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 3V 1.5 V Input 0V 1.5 V 1.5 V VOL tPLH tPHL VOH Output 1.5 V 1.5 V VOL 1.5 V 0V tPLZ Output Waveform 1 S1 at 7 V (see Note B) VOH Output 1.5 V tPZL tPHL tPLH 3V Output Control 1.5 V Output Waveform 2 S1 at Open (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 1.5 V tPZH 3.5 V VOL + 0.3 V VOL tPHZ 1.5 V VOH ­ 0.3 V VOH 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2.5 ns, tf 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 7 IMPORTANT NOTICE Texas Instruments (TI) reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied on is current. 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