SN54ABT16245 SN74ABT16245 16-BIT SCBS084B D3712 JESD-17 ABT16245 MIL-STD-883 - Datasheet Archive

 

16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS084B ­ D3712, JANUARY 1991 ­ REVISED DECEMBER 1992 · ·

 

SN54ABT16245 SN54ABT16245, SN74ABT16245 SN74ABT16245 16-BIT 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS084B SCBS084B ­ D3712 D3712, JANUARY 1991 ­ REVISED DECEMBER 1992 · · · · · · · · Members of the Texas Instruments Widebus TM Family State-of-the-Art EPIC-B TM BiCMOS Design Significantly Reduces Power Dissipation Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 JESD-17 Typical VOLP (Output Ground Bounce) < 1 V at VCC = 5 V, TA = 25°C Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise Flow-Through Architecture Optimizes PCB Layout High-Drive Outputs (­ 32-mA IOH, 64-mA IOL ) Packaged in Plastic 300-mil Shrink Small-Outline and Thin Shrink Small-Outline Packages and 380-mil Fine-Pitch Ceramic Flat Packages Using 25-mil Center-to-Center Spacings SN54ABT16245 SN54ABT16245 . . . WD PACKAGE SN74ABT16245 SN74ABT16245 . . . DGG OR DL PACKAGE (TOP VIEW) 1DIR 1B1 1B2 GND 1B3 1B4 VCC 1B5 1B6 GND 1B7 1B8 2B1 2B2 GND 2B3 2B4 VCC 2B5 2B6 GND 2B7 2B8 2DIR description The ABT16245 ABT16245 is a 16-bit (dual-octal) noninverting 3-state transceiver designed for synchronous two-way communication between data buses. The control function implementation minimizes external timing requirements. 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 32 18 31 19 30 20 29 21 28 22 27 23 26 24 25 1OE 1A1 1A2 GND 1A3 1A4 VCC 1A5 1A6 GND 1A7 1A8 2A1 2A2 GND 2A3 2A4 VCC 2A5 2A6 GND 2A7 2A8 2OE This device can be used as two 8-bit transceivers or one 16-bit transceiver. It allows data transmission from the A bus to the B bus or from the B bus to the A bus depending upon the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so that the buses are effectively isolated. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN74ABT16245 SN74ABT16245 is available in TI's shrink small-outline package (DL), which provides twice the I/O pin count and functionality of standard small-outline packages in the same printed-circuit-board area. The SN54ABT16245 SN54ABT16245 is characterized for operation over the full military temperature range of ­ 55°C to 125°C. The SN74ABT16245 SN74ABT16245 is characterized for operation from ­ 40°C to 85°C. FUNCTION TABLE (each 8-bit section) INPUTS OE DIR OPERATION L L B data to A bus L H A data to B bus H X Isolation Widebus and EPIC-B are trademarks of Texas Instruments Incorporated. Copyright © 1992, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 3­1 SN54ABT16245 SN54ABT16245, SN74ABT16245 SN74ABT16245 16-BIT 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS084B SCBS084B ­ D3712 D3712, JANUARY 1991 ­ REVISED DECEMBER 1992 logic symbol 48 1OE 1DIR 1 logic diagram (positive logic) G3 1DIR 1 3 EN1 [BA] 3 EN2 [AB] 25 2OE 2DIR 24 48 G6 6 EN4 [BA] 6 EN5 [AB] 1A1 1A2 1A3 1A4 1A5 1A6 1A7 1A8 2A1 47 1A1 2 1 2 46 3 44 5 43 6 41 8 40 9 38 11 37 12 36 13 4 47 1B1 2 1B3 1B4 1B5 To Seven Other Channels 1B6 1B7 1B8 2DIR 24 2B1 25 2A3 2A4 2A5 2A6 2A7 2A8 35 14 33 16 32 17 30 19 29 20 27 22 26 23 1B1 1B2 5 2A2 1OE 2OE 2B2 2B3 2B4 2A1 36 2B5 13 2B6 2B1 2B7 2B8 This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. To Seven Other Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ­ 0.5 V to 7 V Input voltage range, VI (except I/O ports) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ­ 0.5 V to 7 V Voltage range applied to any output in the high state or power-off state, VO . . . . . . . . . . . . . ­ 0.5 V to 5.5 V Current into any output in the low state, IO: SN54ABT16245 SN54ABT16245 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA SN74ABT16245 SN74ABT16245 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ­18 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ­ 50 mA Maximum power dissipation at TA = 55°C (in still air): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.8 W DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.85 W Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ­ 65°C to 150°C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 3­2 POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 SN54ABT16245 SN54ABT16245, SN74ABT16245 SN74ABT16245 16-BIT 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS084B SCBS084B ­ D3712 D3712, JANUARY 1991 ­ REVISED DECEMBER 1992 recommended operating conditions (see Note 2) SN54ABT16245 SN54ABT16245 SN74ABT16245 SN74ABT16245 MIN Supply voltage VIL VI Input transition rise or fall rate 5.5 4.5 5.5 High-level output current t /v MAX Low-level input voltage IOH IOL MIN 4.5 VCC VIH MAX High-level input voltage 2 2 0.8 Input voltage 0 Low-level output current 0 V V 0.8 VCC ­ 24 UNIT VCC ­ 32 V V mA 48 TA Operating free-air temperature NOTE 2: Unused or floating pins (input or I/O) must be held high or low. ­ 55 64 mA 10 Outputs enabled 10 ns/ V 85 °C 125 ­ 40 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOH VOL TEST CONDITIONS MIN VCC = 4.5 V, VCC = 4.5 V, II = ­18 mA IOH = ­ 3 mA VCC = 5 V, VCC = 4.5 V, IOH = ­ 3 mA IOH = ­ 24 mA VCC = 4.5 V, VCC = 4.5 V, IOH = ­ 32 mA IOL = 48 mA VCC = 4.5 V, TA = 25°C TYP MAX IOL = 64 mA SN54ABT16245 SN54ABT16245 MIN ­1.2 MAX SN74ABT16245 SN74ABT16245 MIN ­1.2 MAX ­1.2 2.5 2.5 3 3 2 2 2 V 2 0.55 0.55 IOZH§ IOZL§ VCC = 5.5 V, VCC = 5.5 V, VO = 2.7 V VO = 0.5 V Ioff ICEX IO# VCC = 0, VCC = 5.5 V, VI or VO 4.5 V VO = 5.5 V Outputs high VCC = 5.5 V, VO = 2.5 V ±1 ±100 10¶ A or B ports ±1 ±100 10 ±100 10¶ ­ 10¶ VCC = 5.5 V, VI = VCC or GND 0.55 ±1 Control inputs II ­ 10 ­ 10¶ µA ±100 µA 0.55 ±100 50 ­ 50 ­100 ­180 ­ 50 ­180 ICC ­ 50 ICC|| Ci Cio VCC = 5.5 V, One input at 3 4 V 3.4 V, Other inputs at VCC or GND VI = 2.5 V or 0.5 V VO = 2.5 V or 0.5 V µA µA mA 2 2 2 Outputs low 32 32 32 2 2 2 Outputs enabled 1 1.5 1 Outputs disabled Data inputs µA ­180 Outputs disabled A or B ports V 50 50 Outputs high VCC = 5.5 V, 55V IO = 0 0, VI = VCC or GND V 2.5 3 UNIT 0.05 1 0.05 1.5 1.5 1.5 Control inputs Control inputs A or B ports mA A mA A 3 pF 8.5 pF All typical values are at VCC = 5 V. On products compliant to MIL-STD-883 MIL-STD-883, Class B, this parameter does not apply. § The parameters IOZH and IOZL include the input leakage current. ¶ This data sheet limit may vary among suppliers. # Not more than one output should be tested at a time, and the duration of the test should not exceed one second. || This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND. POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 3­3 SN54ABT16245 SN54ABT16245, SN74ABT16245 SN74ABT16245 16-BIT 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS084B SCBS084B ­ D3712 D3712, JANUARY 1991 ­ REVISED DECEMBER 1992 switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) VCC = 5 V, TA = 25°C TO (OUTPUT) SN54ABT16245 SN54ABT16245 UNIT MIN tPLH tPHL OE OE B or A MAX MIN MAX MIN MAX 1 2.2 3.4 1 2.1 3.8 0.5 4 1 3.9 0.5 4.6 1 4.5 1 3.1 4.4 0.8 5.5 1 5.4 1 3 6.1 0.9 7.3 1 7.2 1.3 3.5 4.7 1.3 6.3 1.3 5.5 1.4 3.2 4.7 1.4 5.3 1.4 5.2 B or A tPHZ tPLZ TYP B or A tPZH tPZL 3­4 A or B SN74ABT16245 SN74ABT16245 POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 ns ns ns SN54ABT16245 SN54ABT16245, SN74ABT16245 SN74ABT16245 16-BIT 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS084B SCBS084B ­ D3712 D3712, JANUARY 1991 ­ REVISED DECEMBER 1992 PARAMETER MEASUREMENT INFORMATION 7V S1 500 From Output Under Test Open TEST CL = 50 pF (see Note A) 500 S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH GND Open 7V Open LOAD CIRCUIT FOR OUTPUTS 3V 1.5 V Timing Input 0V tw tsu 3V Input 1.5 V 3V 1.5 V Data Input 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 3V 1.5 V 0V tPHL 1.5 V 1.5 V VOL VOH Output 1.5 V 0V 1.5 V VOL tPLZ Output Waveform 1 S1 at 7 V (see Note C) tPLH tPHL 1.5 V 1.5 V tPZL VOH Output 3V Output Control 1.5 V tPLH 1.5 V 0V VOLTAGE WAVEFORMS PULSE DURATION Input (see Note B) th Output Waveform 2 S1 at Open (see Note C) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 1.5 V tPZH 3.5 V VOL + 0.3 V VOL tPHZ 1.5 V VOH ­ 0.3 V VOH [0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2.5 ns, tf 2.5 ns. C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. D. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 3­5 SN54ABT16245 SN54ABT16245, SN74ABT16245 SN74ABT16245 16-BIT 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS084B SCBS084B ­ D3712 D3712, JANUARY 1991 ­ REVISED DECEMBER 1992 3­6 POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments (TI) reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied on is current. TI warrants performance of its semiconductor products and related software to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. 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