SMJ320VC5416 SGUS035 MIL-PRF-38535 HPI8/16 HPI16 SMJ320VC5416HFG SPRU307 16HPI - Datasheet Archive

 

Digital Signal Processor Data Manual Literature Number: SGUS035 April 2003 PRODUCTION DATA information is current as of

 

SMJ320VC5416 SMJ320VC5416 Fixed-Point Digital Signal Processor Data Manual Literature Number: SGUS035 SGUS035 April 2003 PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. On products compliant to MIL-PRF-38535 MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters. Printed on Recycled Paper IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third­party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265 Copyright 2003, Texas Instruments Incorporated REVISION HISTORY REVISION DATE PRODUCT STATUS * March 2003 Production Data HIGHLIGHTS Original iii Contents Contents Section 1 2 3 Page SMJ320VC5416 SMJ320VC5416 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.2 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.2.1 Pin Assignments for the HFG Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.3 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.1 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.1.1 Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.1.2 Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.1.3 Extended Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.2 On-Chip ROM With Bootloader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.3 On-Chip RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.4 On-Chip Memory Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.5 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.5.1 Relocatable Interrupt Vector Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.6 On-Chip Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.6.1 Software-Programmable Wait-State Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.6.2 Programmable Bank-Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.6.3 Bus Holders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.7 Parallel I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.7.1 Enhanced 8-/16-Bit Host-Port Interface (HPI8/16 HPI8/16) . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.7.2 HPI Nonmultiplexed Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.8 Multichannel Buffered Serial Ports (McBSPs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.9 Hardware Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.10 Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.11 Enhanced External Parallel Interface (XIO2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.12 DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.12.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.12.2 DMA External Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.12.3 DMA Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.12.4 DMA Priority Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.12.5 DMA Source/Destination Address Modification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.12.6 DMA in Autoinitialization Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.12.7 DMA Transfer Counting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.12.8 DMA Transfer in Doubleword Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.12.9 DMA Channel Index Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.12.10 DMA Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.12.11 DMA Controller Synchronization Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.13 General-Purpose I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.13.1 McBSP Pins as General-Purpose I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.13.2 HPI Data Pins as General-Purpose I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.14 Device ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.15 Memory-Mapped Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.16 McBSP Control Registers and Subaddresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.17 DMA Subbank Addressed Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 April 2003 SGUS035 SGUS035 v Contents 4 5 6 vi 3.18 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Documentation Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3 Electrical Characteristics Over Recommended Operating Case Temperature Range (Unless Otherwise Noted) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4 Package Thermal Resistance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 Timing Parameter Symbology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.6 Internal Oscillator With External Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.7 Clock Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.7.1 Divide-By-Two and Divide-By-Four Clock Options . . . . . . . . . . . . . . . . . . . . . . . . . 5.7.2 Multiply-By-N Clock Option (PLL Enabled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.8 Memory and Parallel I/O Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.8.1 Memory Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.8.2 Memory Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.8.3 I/O Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.8.4 I/O Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.9 Ready Timing for Externally Generated Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.10 HOLD and HOLDA Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.11 Reset, BIO, Interrupt, and MP/MC Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.12 Instruction Acquisition (IAQ) and Interrupt Acknowledge (IACK) Timings . . . . . . . . . . . . . . . 5.13 External Flag (XF) and TOUT Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.14 Multichannel Buffered Serial Port (McBSP) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.14.1 McBSP Transmit and Receive Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.14.2 McBSP General-Purpose I/O Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.14.3 McBSP as SPI Master or Slave Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.15 Host-Port Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.15.1 HPI8 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.15.2 HPI16 HPI16 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1 Ceramic Quad Flatpack Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SGUS035 SGUS035 41 42 43 43 43 44 45 45 45 46 46 48 49 49 52 53 54 55 60 62 64 65 66 66 69 70 74 74 78 82 82 April 2003 Figures List of Figures Figure Page 2-1. 164-Pin HFG Ceramic Quad Flatpack (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3-1. SMJ320VC5416 SMJ320VC5416 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3-2. Program and Data Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3-3. Extended Program Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3-4. Processor Mode Status (PMST) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3-5. Software Wait-State Register (SWWSR) [Memory-Mapped Register (MMR) Address 0028h] . . . . . 16 3-6. Software Wait-State Control Register (SWCR) [MMR Address 002Bh] . . . . . . . . . . . . . . . . . . . . . . . . . 17 3-7. Bank-Switching Control Register (BSCR) [MMR Address 0029h] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3-8. Host-Port Interface - Nonmultiplexed Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3-9. HPI Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3-10. Multichannel Control Registers (MCR1 and MCR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3-11. Pin Control Register (PCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3-12. Nonconsecutive Memory Read and I/O Read Bus Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3-13. Consecutive Memory Read Bus Sequence (n = 3 reads) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3-14. Memory Write and I/O Write Bus Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3-15. DMA Transfer Mode Control Register (DMMCRn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3-16. On-Chip DMA Memory Map for Program Space (DLAXS = 0 and SLAXS = 0) . . . . . . . . . . . . . . . . . 30 3-17. On-Chip DMA Memory Map for Data and IO Space (DLAXS = 0 and SLAXS = 0) . . . . . . . . . . . . . . 31 3-18. DMPREC Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3-19. General-Purpose I/O Control Register (GPIOCR) [MMR Address 003Ch] . . . . . . . . . . . . . . . . . . . . . 34 3-20. General-Purpose I/O Status Register (GPIOSR) [MMR Address 003Dh] . . . . . . . . . . . . . . . . . . . . . . 34 3-21. Device ID Register (CSIDR) [MMR Address 003Eh] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3-22. IFR and IMR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 5-1. 3.3-V Test Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 5-2. Internal Divide-by-Two Clock Option With External Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 5-3. External Divide-by-Two Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 5-4. Multiply-by-One Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 5-5. Nonconsecutive Mode Memory Reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 5-6. Consecutive Mode Memory Reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 5-7. Memory Write (MSTRB = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 5-8. Parallel I/O Port Read (IOSTRB = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 5-9. Parallel I/O Port Write (IOSTRB = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 5-10. Memory Read With Externally Generated Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 5-11. Memory Write With Externally Generated Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 5-12. I/O Read With Externally Generated Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 5-13. I/O Write With Externally Generated Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 5-14. HOLD and HOLDA Timings (HM = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 5-15. Reset and BIO Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 5-16. Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 5-17. MP/MC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 April 2003 SGUS035 SGUS035 vii Figures 5-18. Instruction Acquisition (IAQ) and Interrupt Acknowledge (IACK) Timings . . . . . . . . . . . . . . . . . . . . . . 5-19. External Flag (XF) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-20. TOUT Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-21. McBSP Receive Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-22. McBSP Transmit Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-23. McBSP General-Purpose I/O Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-24. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 . . . . . . . . . . . . . . . . . . . . . . . . . 5-25. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 . . . . . . . . . . . . . . . . . . . . . . . . . 5-26. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 . . . . . . . . . . . . . . . . . . . . . . . . . 5-27. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 . . . . . . . . . . . . . . . . . . . . . . . . . 5-28. Using HDS to Control Accesses (HCS Always Low) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-29. Using HCS to Control Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-30. HINT Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-31. GPIOx Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-32. Nonmultiplexed Read Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-33. Nonmultiplexed Write Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-34. HRDY Relative to CLKOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1. SMJ320VC5416 SMJ320VC5416 164-Pin Ceramic Quad Flatpack (HFG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . viii SGUS035 SGUS035 64 65 65 67 68 69 70 71 72 73 76 77 77 77 80 81 81 82 April 2003 Tables List of Tables Table Page 2-1. Terminal Assignments for the SMJ320VC5416HFG SMJ320VC5416HFG (164-Pin CQFP Package) . . . . . . . . . . . . . . . . . . 3 2-2. Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3-1. Standard On-Chip ROM Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3-2. Processor Mode Status (PMST) Register Bit Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3-3. Software Wait-State Register (SWWSR) Bit Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3-4. Software Wait-State Control Register (SWCR) Bit Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3-5. Bank-Switching Control Register (BSCR) Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3-6. Bus Holder Control Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3-7. Sample Rate Input Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3-8. Clock Mode Settings at Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3-9. DMD Section of the DMMCRn Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3-10. DMA Reload Register Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3-11. DMA Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3-12. DMA Synchronization Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3-13. DMA Channel Interrupt Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3-14. CPU Memory-Mapped Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3-15. Peripheral Memory-Mapped Registers for Each DSP Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3-16. McBSP Control Registers and Subaddresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3-17. DMA Subbank Addressed Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3-18. Interrupt Locations and Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 5-1. Thermal Resistance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 5-2. Input Clock Frequency Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 5-3. Clock Mode Pin Settings for the Divide-By-2 and By Divide-by-4 Clock Options . . . . . . . . . . . . . . . . . 46 5-4. Divide-By-2 and Divide-by-4 Clock Options Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 5-5. Divide-By-2 and Divide-by-4 Clock Options Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 47 5-6. Multiply-By-N Clock Option Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 5-7. Multiply-By-N Clock Option Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 5-8. Memory Read Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 5-9. Memory Read Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 5-10. Memory Write Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 5-11. I/O Read Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 5-12. I/O Read Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 5-13. I/O Write Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 5-14. Ready Timing Requirements for Externally Generated Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . 55 5-15. Ready Switching Characteristics for Externally Generated Wait States . . . . . . . . . . . . . . . . . . . . . . . 55 5-16. HOLD and HOLDA Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 5-17. HOLD and HOLDA Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 5-18. Reset, BIO, Interrupt, and MP/MC Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 5-19. Instruction Acquisition (IAQ) and Interrupt Acknowledge (IACK) Switching Characteristics . . . . . . 64 5-20. External Flag (XF) and TOUT Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 5-21. McBSP Transmit and Receive Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 5-22. McBSP Transmit and Receive Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 5-23. McBSP General-Purpose I/O Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 5-24. McBSP General-Purpose I/O Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 5-25. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0) . . . . . . . . . . . 70 5-26. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0) . . . . . . . 70 April 2003 SGUS035 SGUS035 ix Tables 5-27. 5-28. 5-29. 5-30. 5-31. 5-32. 5-33. 5-34. 5-35. 5-36. x McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0) . . . . . . . . . . . McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0) . . . . . . . McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1) . . . . . . . . . . . McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1) . . . . . . . McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1) . . . . . . . . . . . McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1) . . . . . . . HPI8 Mode Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HPI8 Mode Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HPI16 HPI16 Mode Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HPI16 HPI16 Mode Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SGUS035 SGUS035 71 71 72 72 73 73 74 75 78 79 April 2003 Features 1 SMJ320VC5416 SMJ320VC5416 Features D Processed to MIL-PRF-38535 MIL-PRF-38535 (QML) D Advanced Multibus Architecture With Three D D D D D D D D D D D D Separate 16-Bit Data Memory Buses and One Program Memory Bus 40-Bit Arithmetic Logic Unit (ALU) Including a 40-Bit Barrel Shifter and Two Independent 40-Bit Accumulators 17 x 17-Bit Parallel Multiplier Coupled to a 40-Bit Dedicated Adder for Non-Pipelined Single-Cycle Multiply/Accumulate (MAC) Operation Compare, Select, and Store Unit (CSSU) for the Add/Compare Selection of the Viterbi Operator Exponent Encoder to Compute an Exponent Value of a 40-Bit Accumulator Value in a Single Cycle Two Address Generators With Eight Auxiliary Registers and Two Auxiliary Register Arithmetic Units (ARAUs) Data Bus With a Bus Holder Feature Extended Addressing Mode for 8M x 16-Bit Maximum Addressable External Program Space 128K x 16-Bit On-Chip RAM Composed of: ­ Eight Blocks of 8K x 16-Bit On-Chip Dual-Access Program/Data RAM ­ Eight Blocks of 8K x 16-Bit On-Chip Single-Access Program RAM 16K x 16-Bit On-Chip ROM Configured for Program Memory Enhanced External Parallel Interface (XIO2) Single-Instruction-Repeat and Block-Repeat Operations for Program Code Block-Memory-Move Instructions for Better Program and Data Management D Instructions With a 32-Bit Long Word Operand D Instructions With Two- or Three-Operand D D D D D D D D D D D D Reads Arithmetic Instructions With Parallel Store and Parallel Load Conditional Store Instructions Fast Return From Interrupt On-Chip Peripherals ­ Software-Programmable Wait-State Generator and Programmable Bank-Switching ­ On-Chip Programmable Phase-Locked Loop (PLL) Clock Generator With External Clock Source ­ One 16-Bit Timer ­ Six-Channel Direct Memory Access (DMA) Controller ­ Three Multichannel Buffered Serial Ports (McBSPs) ­ 8/16-Bit Enhanced Parallel Host-Port Interface (HPI8/16 HPI8/16) Power Consumption Control With IDLE1, IDLE2, and IDLE3 Instructions With Power-Down Modes CLKOUT Off Control to Disable CLKOUT On-Chip Scan-Based Emulation Logic, IEEE Std 1149.1 (JTAG) Boundary Scan Logic 164-Pin Ceramic Quad Flatpack (CQFP) (HFG Suffix) 10-ns Single-Cycle Fixed-Point Instruction Execution Time (100 MIPS) 3.3-V I/O Supply Voltage 1.5-V Core Supply Voltage ­55°C to 115°C Operating Temperature Range, QML Processing IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture. April 2003 SGUS035 SGUS035 1 Introduction 2 Introduction This section describes the main features of the SMJ320VC5416 SMJ320VC5416, lists the pin assignments, and describes the function of each pin. This data manual also provides a detailed description section, electrical specifications, parameter measurement information, and mechanical data about the available packaging. NOTE: This data manual is designed to be used in conjunction with the TMS320C54x DSP Functional Overview (literature number SPRU307 SPRU307). 2.1 Description The SMJ320VC5416 SMJ320VC5416 fixed-point, digital signal processor (DSP) (hereafter referred to as the 5416 unless otherwise specified) is based on an advanced modified Harvard architecture that has one program memory bus and three data memory buses. This processor provides an arithmetic logic unit (ALU) with a high degree of parallelism, application-specific hardware logic, on-chip memory, and additional on-chip peripherals. The basis of the operational flexibility and speed of this DSP is a highly specialized instruction set. Separate program and data spaces allow simultaneous access to program instructions and data, providing a high degree of parallelism. Two read operations and one write operation can be performed in a single cycle. Instructions with parallel store and application-specific instructions can fully utilize this architecture. In addition, data can be transferred between data and program spaces. Such parallelism supports a powerful set of arithmetic, logic, and bit-manipulation operations that can all be performed in a single machine cycle. The 5416 also includes the control mechanisms to manage interrupts, repeated operations, and function calls. 2.2 Pin Assignments Figure 2­1 provides the pin assignments for the 164-pin ceramic quad flatpack (CQFP) package. Table 2­2 lists terminal names, terminal functions, and operating modes for the SMJ320VC5416 SMJ320VC5416. 2 SGUS035 SGUS035 April 2003 Introduction Table 2­1. Terminal Assignments for the SMJ320VC5416HFG SMJ320VC5416HFG (164-Pin CQFP Package) PIN NUMBER PIN NAME PIN NUMBER PIN NAME PIN NUMBER PIN NAME PIN NUMBER PIN NAME 1 42 A19 84 VSS BCLKX1 124 43 VSS BCLKR1 83 2 VSS NC 125 A20 3 A22 44 HCNTL0 85 BFSX1 126 NC 4 NC 45 86 BDX1 127 5 46 87 128 47 BCLKR2 88 DVDD CLKMD1 VSS DVDD 129 D6 7 VSS DVDD A10 VSS BCLKR0 48 BFSR0 89 CLKMD2 130 D7 8 HD7 49 BFSR2 90 CLKMD3 131 D8 6 9 A11 50 BDR0 91 HPI16 HPI16 132 D9 10 A12 51 HCNTL1 92 HD2 133 D10 11 A13 52 93 TOUT 134 D11 12 A14 53 VSS BDR2 94 EMU0 135 13 A15 54 CVDD 95 EMU1/OFF 136 14 NC 55 BCLKX0 96 TDO 137 VSS CVDD D12 15 CVDD HAS 56 BCLKX2 97 138 HD4 57 NC 98 VSS TDI 139 D13 58 VSS HINT 99 CVDD 140 D14 100 TRST 141 D15 19 VSS CVDD HCS 60 NC 101 TCK 142 HD5 20 HR/W 61 CVDD 102 TMS 143 21 READY 62 BFSX0 103 144 VSS NC 22 PS 63 BFSX2 104 VSS NC 145 HDS1 23 CVDD DS 64 HRDY 105 CVDD 146 65 DVDD 106 HPIENA 147 VSS HDS2 66 DVDD 108 VSS CVDD 148 67 VSS HD0 107 26 VSS IS 149 A0 27 R/W 68 BDX0 109 CLKOUT 150 A1 28 MSTRB 69 BDX2 110 HD3 151 CVDD 29 IOSTRB 70 CVDD 111 X1 152 A2 30 MSC 71 IACK 112 X2/CLKIN 153 31 XF 72 113 RS 154 32 HOLDA 73 VSS HBIL VSS A3 114 D0 155 HD6 33 IAQ 74 NMI 115 D1 156 A4 34 HOLD 75 INT0 116 D2 157 A5 35 BIO 76 INT1 117 D3 158 A6 36 MP/MC 77 INT2 118 D4 159 A7 37 DVDD NC 78 INT3 119 D5 160 A8 79 NC 120 A16 161 A9 80 CVDD 121 CVDD 81 HD1 122 VSS A17 162 40 VSS BDR1 163 A21 41 BFSR1 82 NC 123 A18 164 VSS 16 17 18 24 25 38 39 59 DVDD is the power supply for the I/O pins while CVDD is the power supply for the core CPU, and VSS is the ground for both the I/O pins and the core CPU. April 2003 SGUS035 SGUS035 3 Introduction 2.2.1 Pin Assignments for the HFG Package The SMJ320VC5416HFG SMJ320VC5416HFG 164-pin ceramic quad flatpack (CQFP) pin assignments are shown in Figure 2­1. 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 V SS A21 CVDD A9 A8 A7 A6 A5 A4 HD6 A3 VSS A2 CV DD A1 A0 DVDD HDS2 VSS HDS1 NC VSS HD5 D15 D14 D13 HD4 D12 CVDD VSS D11 D10 D9 D8 D7 D6 DVDD VSS NC A20 A19 HFG PACKAGE (TOP VIEW) NC A22 NC V SS DV DD A10 HD7 A11 A12 A13 A14 A15 NC CV DD HAS V SS CV DD HCS HR/W READY PS CV DD DS V SS IS R/W MSTRB IOSTRB MSC XF 30 31 32 33 34 35 36 37 38 39 40 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 41 83 A18 A17 V SS A16 D5 D4 D3 D2 D1 D0 RS X2/CLKIN X1 HD3 CLKOUT CVDD V SS HPIENA CVDD NC V SS TMS TCK TRST CVDD TDI V SS TDO EMU1/OFF EMU0 TOUT HD2 HPI16 HPI16 CLKMD3 CLKMD2 CLKMD1 DVDD BDX1 BFSX1 BCLKX1 V SS VSS BCLKR1 HCNTL0 VSS BCLKR0 BCLKR2 BFSR0 BFSR2 BDR0 HCNTL1 VSS BDR2 CVDD BCLKX0 BCLKX2 NC VSS HINT NC CVDD BFSX0 BFSX2 HRDY DVDD V SS HD0 BDX0 BDX2 CVDD IACK V SS HBIL NMI INT0 INT1 INT2 INT3 NC CVDD HD1 NC HOLDA IAQ HOLD BIO MP/MC DV DD NC V SS BDR1 BFSR1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 V SS NC ­ No internal connection NC = No connection DVDD is the power supply for the I/O pins while CVDD is the power supply for the core CPU, and VSS is the ground for both the I/O pins and the core CPU. Figure 2­1. 164-Pin HFG Ceramic Quad Flatpack (Top View) 4 SGUS035 SGUS035 April 2003 Introduction 2.3 Signal Descriptions Table 2­2 lists each signal, function, and operating mode(s) grouped by function. See Section 2.2 for exact pin locations based on package type. Table 2­2. Signal Descriptions TERMINAL NAME I/O DESCRIPTION DATA SIGNALS A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 (MSB) I/O/Z§ Parallel address bus A22 [most significant bit (MSB)] through A0 [least significant bit (LSB)]. The sixteen LSB lines, A0 to A15, are multiplexed to address external memory (program, data) or I/O. The seven MSB lines, A16 to A22, address external program space memory. A22­A0 is placed in the high-impedance state in the hold mode. A22­A0 also goes into the high-impedance state when OFF is low. A17­A0 are inputs in HPI16 HPI16 mode. These pins can be used to address internal memory via the host-port interface (HPI) when the HPI16 HPI16 pin is high. These pins also have Schmitt trigger inputs. The address bus has a bus holder feature that eliminates passive components and the power dissipation associated with them. The bus holder keeps the address bus at the previous logic level when the bus goes into a high-impedance state. (LSB) D15 (MSB) I/O/Z§ Parallel data bus D15 (MSB) through D0 (LSB). D15­D0 is multiplexed to transfer data between the core CPU D14 and external data/program memory or I/O devices or HPI in HPI16 HPI16 mode (when HPI16 HPI16 pin is high). D15­D0 is D13 placed in the high-impedance state when not outputting data or when RS or HOLD is asserted. D15­D0 also goes D12 into the high-impedance state when OFF is low. These pins also have Schmitt trigger inputs. D11 D10 The data bus has a bus holder feature that eliminates passive components and the power dissipation associated D9 with them. The bus holder keeps the data bus at the previous logic level when the bus goes into the D8 high-impedance state. The bus holders on the data bus can be enabled/disabled under software control. D7 D6 D5 D4 D3 D2 D1 D0 (LSB) I = Input, O = Output, Z = High-impedance, S = Supply These pins have Schmitt trigger inputs. § This pin has an internal bus holder controlled by way of the BSCR register. ¶ This pin has an internal pullup resistor. # This pin has an internal pulldown resistor. April 2003 SGUS035 SGUS035 5 Introduction Table 2­2. Signal Descriptions (Continued) TERMINAL NAME I/O DESCRIPTION INITIALIZATION, INTERRUPT AND RESET OPERATIONS IACK O/Z Interrupt acknowledge signal. IACK indicates receipt of an interrupt and that the program counter is fetching the interrupt vector location designated by A15­A0. IACK also goes into the high-impedance state when OFF is low. INT0 INT1 INT2 INT3 I External user interrupt inputs. INT0­INT3 are maskable and are prioritized by the interrupt mask register (IMR) and the interrupt mode bit. INT0 ­INT3 can be polled and reset by way of the interrupt flag register (IFR). NMI I Nonmaskable interrupt. NMI is an external interrupt that cannot be masked by way of the INTM or the IMR. When NMI is activated, the processor traps to the appropriate vector location. RS I Reset. RS causes the digital signal processor (DSP) to terminate execution and forces the program counter to 0FF80h. When RS is brought to a high level, execution begins at location 0FF80h of program memory. RS affects various registers and status bits. I Microprocessor/microcomputer mode select. If active low at reset, microcomputer mode is selected, and the internal program ROM is mapped into the upper 16K words of program memory space. If the pin is driven high during reset, microprocessor mode is selected, and the on-chip ROM is removed from program space. This pin is only sampled at reset, and the MP/MC bit of the processor mode status (PMST) register can override the mode that is selected at reset. MP/MC MULTIPROCESSING SIGNALS I XF Branch control. A branch can be conditionally executed when BIO is active. If low, the processor executes the conditional instruction. The BIO condition is sampled during the decode phase of the pipeline for the XC instruction, and all other instructions sample BIO during the read phase of the pipeline. O/Z BIO External flag output (latched software-programmable signal). XF is set high by the SSBX XF instruction, set low by RSBX XF instruction or by loading ST1. XF is used for signaling other processors in multiprocessor configurations or used as a general-purpose output pin. XF goes into the high-impedance state when OFF is low, and is set high at reset. MEMORY CONTROL SIGNALS DS PS IS O/Z Data, program, and I/O space select signals. DS, PS, and IS are always high unless driven low for communicating to a particular external space. Active period corresponds to valid address information. DS, PS, and IS are placed into the high-impedance state in the hold mode; these signals also go into the high-impedance state when OFF is low. MSTRB O/Z Memory strobe signal. MSTRB is always high unless low-level asserted to indicate an external bus access to data or program memory. MSTRB is placed in the high-impedance state in the hold mode; it also goes into the high-impedance state when OFF is low. READY I Data ready. READY indicates that an external device is prepared for a bus transaction to be completed. If the device is not ready (READY is low), the processor waits one cycle and checks READY again. Note that the processor performs ready detection if at least two software wait states are programmed. The READY signal is not sampled until the completion of the software wait states. R/W O/Z Read/write signal. R/W indicates transfer direction during communication to an external device. R/W is normally in the read mode (high), unless it is asserted low when the DSP performs a write operation. R/W is placed in the high-impedance state in the hold mode; and it also goes into the high-impedance state when OFF is low. IOSTRB O/Z I/O strobe signal. IOSTRB is always high unless low-level asserted to indicate an external bus access to an I/O device. IOSTRB is placed in the high-impedance state in the hold mode; it also goes into the high-impedance state when OFF is low. I Hold input. HOLD is asserted to request control of the address, data, and control lines. When acknowledged by the 5416, these lines go into the high-impedance state. HOLD I = Input, O = Output, Z = High-impedance, S = Supply These pins have Schmitt trigger inputs. § This pin has an internal bus holder controlled by way of the BSCR register. ¶ This pin has an internal pullup resistor. # This pin has an internal pulldown resistor. 6 SGUS035 SGUS035 April 2003 Introduction Table 2­2. Signal Descriptions (Continued) TERMINAL NAME I/O DESCRIPTION MEMORY CONTROL SIGNALS (CONTINUED) O/Z Hold acknowledge. HOLDA indicates to the external circuitry that the processor is in a hold state and that the address, data, and control lines are in the high-impedance state, allowing them to be available to the external circuitry. HOLDA also goes into the high-impedance state when OFF is low. This pin is driven high during reset. MSC O/Z Microstate complete. MSC indicates completion of all software wait states. When two or more software wait states are enabled, the MSC pin goes active at the beginning of the first software wait state and goes inactive high at the beginning of the last software wait state. If connected to the READY input, MSC forces one external wait state after the last internal wait state is completed. MSC also goes into the high-impedance state when OFF is low. IAQ O/Z Instruction acquisition signal. IAQ is asserted (active low) when there is an instruction address on the address bus and goes into the high-impedance state when OFF is low. HOLDA TIMER SIGNALS CLKOUT O/Z Clock output signal. CLKOUT can represent the machine-cycle rate of the CPU divided by 1, 2, 3, or 4 as configured in the bank-switching control register (BSCR). Following reset, CLKOUT represents the machine-cycle rate divided by 4. CLKMD1 CLKMD2 CLKMD3 I Clock mode select signals. CLKMD1­CLKMD3 allow the selection and configuration of different clock modes such as crystal, external clock, and PLL mode. The external CLKMD1­CLKMD3 pins are sampled to determine the desired clock generation mode while RS is low. Following reset, the clock generation mode can be reconfigured by writing to the internal clock mode register in software. X2/CLKIN I Clock/oscillator input. If the internal oscillator is not being used, X2/CLKIN functions as the clock input. (This is revision-dependent, see Section 3.10 for additional information.) X1 O Output pin from the internal oscillator for the crystal. If the internal oscillator is not used, X1 should be left unconnected. X1 does not go into the high-impedance state when OFF is low. (This is revision-dependent, see Section 3.10 for additional information.) O/Z Timer output. TOUT signals a pulse when the on-chip timer counts down past zero. The pulse is one CLKOUT cycle wide. TOUT also goes into the high-impedance state when OFF is low. TOUT MULTICHANNEL BUFFERED SERIAL PORT 0 (McBSP #0), MULTICHANNEL BUFFERED SERIAL PORT 1 (McBSP #1), AND MULTICHANNEL BUFFERED SERIAL PORT 2 (McBSP #2) SIGNALS BCLKR0 BCLKR1 BCLKR2 I/O/Z Receive clock input. BCLKR can be configured as an input or an output; it is configured as an input following reset. BCLKR serves as the serial shift clock for the buffered serial port receiver. BDR0 BDR1 BDR2 I BFSR0 BFSR1 BFSR2 I/O/Z Frame synchronization pulse for receive input. BFSR can be configured as an input or an output; it is configured as an input following reset. The BFSR pulse initiates the receive data process over BDR. BCLKX0 BCLKX1 BCLKX2 I/O/Z Transmit clock. BCLKX serves as the serial shift clock for the McBSP transmitter. BCLKX can be configured as an input or an output, and is configured as an input following reset. BCLKX enters the high-impedance state when OFF goes low. BDX0 BDX1 BDX2 O/Z Serial data transmit output. BDX is placed in the high-impedance state when not transmitting, when RS is asserted, or when OFF is low. Serial data receive input BFSX0 Frame synchronization pulse for transmit input/output. The BFSX pulse initiates the data transmit process over BFSX1 BDX. BFSX can be configured as an input or an output, and is configured as an input following reset. BFSX goes I/O/Z BFSX2 into the high-impedance state when OFF is low. I = Input, O = Output, Z = High-impedance, S = Supply These pins have Schmitt trigger inputs. § This pin has an internal bus holder controlled by way of the BSCR register. ¶ This pin has an internal pullup resistor. # This pin has an internal pulldown resistor. April 2003 SGUS035 SGUS035 7 Introduction Table 2­2. Signal Descriptions (Continued) TERMINAL NAME I/O DESCRIPTION HOST-PORT INTERFACE SIGNALS I/O/Z Parallel bidirectional data bus. The HPI data bus is used by a host device bus to exchange information with the HPI registers. These pins can also be used as general-purpose I/O pins. HD0­HD7 is placed in the high-impedance state when not outputting data or when OFF is low. The HPI data bus includes bus holders to reduce the static power dissipation caused by floating, unused pins. When the HPI data bus is not being driven by the 5416, the bus holders keep the pins at the previous logic level. The HPI data bus holders are disabled at reset and can be enabled/disabled via the HBH bit of the BSCR. These pins also have Schmitt trigger inputs. HCNTL0¶ HCNTL1¶ I Control inputs. HCNTL0 and HCNTL1 select a host access to one of the three HPI registers. The control inputs have internal pullups that are only enabled when HPIENA = 0. These pins are not used when HPI16 HPI16 = 1. HBIL¶ I Byte identification. HBIL identifies the first or second byte of transfer. The HPIL input has an internal pullup resistor that is only enabled when HPIENA = 0. This pin is not used when HPI16 HPI16 = 1. HCS¶ I Chip select. HCS is the select input for the HPI and must be driven low during accesses. The chip select input has an internal pullup resistor that is only enabled when HPIENA = 0. HDS1¶ HDS2¶ I Data strobe. HDS1 and HDS2 are driven by the host read and write strobes to control the transfer. The strobe inputs have internal pullup resistors that are only enabled when HPIENA = 0. HAS¶ I Address strobe. Host with multiplexed address and data pins requires HAS to latch the address in the HPIA register. HAS input has an internal pullup resistor that is only enabled when HPIENA = 0. HR/W¶ I Read/write. HR/W controls the direction of the HPI transfer. HR/W has an internal pullup resistor that is only enabled when HPIENA = 0. HRDY O/Z Ready output. HRDY goes into the high-impedance state when OFF is low. The ready output informs the host when the HPI is ready for the next transfer. This pin is driven high during reset. HINT O/Z Interrupt output. This output is used to interrupt the host. When the DSP is in reset, HINT is driven high. HINT goes into the high-impedance state when OFF is low. This pin is not used when HPI16 HPI16 = 1. HPIENA# I HPI module select. HPIENA must be tied to DVDD to have HPI selected. If HPIENA is left open or connected to ground, the HPI module is not selected, internal pullup for the HPI input pins are enabled, and the HPI data bus has holders set. HPIENA is provided with an internal pulldown resistor that is always active. HPIENA is sampled when RS goes high and is ignored until RS goes low again. This pin should never be changed while reset is high HPI16 HPI16# I HPI16 HPI16 mode selection CVSS S Ground. Dedicated ground for the core CPU CVDD S DVSS S +VDD. Dedicated power supply for the core CPU Ground. Dedicated ground for I/O pins HD0­HD7§ SUPPLY PINS DVDD S +VDD. Dedicated power supply for I/O pins I = Input, O = Output, Z = High-impedance, S = Supply These pins have Schmitt trigger inputs. § This pin has an internal bus holder controlled by way of the BSCR register. ¶ This pin has an internal pullup resistor. # This pin has an internal pulldown resistor. 8 SGUS035 SGUS035 April 2003 Introduction Table 2­2. Signal Descriptions (Continued) TERMINAL NAME I/O DESCRIPTION TEST PINS TCK¶ I IEEE standard 1149.1 test clock. TCK is normally a free-running clock signal with a 50% duty cycle. The changes on test access port (TAP) of input signals TMS and TDI are clocked into the TAP controller, instruction register, or selected test data register on the rising edge of TCK. Changes at the TAP output signal (TDO) occur on the falling edge of TCK. TDI¶ I IEEE standard 1149.1 test data input. Pin with internal pullup device. TDI is clocked into the selected register (instruction or data) on a rising edge of TCK. TDO O/Z IEEE standard 1149.1 test data output. The contents of the selected register (instruction or data) are shifted out of TDO on the falling edge of TCK. TDO is in the high-impedance state except when the scanning of data is in progress. TDO also goes into the high-impedance state when OFF is low. TMS¶ I IEEE standard 1149.1 test mode select. Pin with internal pullup device. This serial control input is clocked into the TAP controller on the rising edge of TCK. TRST# I IEEE standard 1149.1 test reset. TRST, when high, gives the IEEE standard 1149.1 scan system control of the operations of the device. If TRST is not connected or driven low, the device operates in its functional mode, and the IEEE standard 1149.1 signals are ignored. Pin with internal pulldown device. EMU0 I/O/Z Emulator 0 pin. When TRST is driven low, EMU0 must be high for activation of the OFF condition. When TRST is driven high, EMU0 is used as an interrupt to or from the emulator system and is defined as input/output by way of the IEEE standard 1149.1 scan system. I/O/Z Emulator 1 pin/disable all outputs. When TRST is driven high, EMU1/OFF is used as an interrupt to or from the emulator system and is defined as input/output by way of IEEE standard 1149.1 scan system. When TRST is driven low, EMU1/OFF is configured as OFF. The EMU1/OFF signal, when active low, puts all output drivers into the high-impedance state. Note that OFF is used exclusively for testing and emulation purposes (not for multiprocessing applications). Therefore, for the OFF condition, the following apply: TRST = low, EMU0 = high EMU1/OFF = low EMU1/OFF I = Input, O = Output, Z = High-impedance, S = Supply These pins have Schmitt trigger inputs. § This pin has an internal bus holder controlled by way of the BSCR register. ¶ This pin has an internal pullup resistor. # This pin has an internal pulldown resistor. April 2003 SGUS035 SGUS035 9 Functional Overview 3 Functional Overview The following functional overview is based on the block diagram in Figure 3­1. 54X cLEAD 64K RAM Single Access Program Pbus Dbus Ebus Cbus Pbus Ebus Pbus Ebus Cbus Pbus Dbus P, C, D, E Buses and Control Signals 64K RAM Dual Access Program/Data 16K Program ROM MBus GPIO TI BUS RHEA Bus McBSP1 Enhanced XIO 16HPI 16HPI McBSP2 MBus RHEA bus XIO RHEA Bridge McBSP3 16 HPI xDMA logic RHEAbus TIMER APLL Clocks JTAG Figure 3­1. SMJ320VC5416 SMJ320VC5416 Functional Block Diagram 3.1 Memory The 5416 device provides both on-chip ROM and RAM memories to aid in system performance and integration. 3.1.1 Data Memory The data memory space addresses up to 64K of 16-bit words. The device automatically accesses the on-chip RAM when addressing within its bounds. When an address is generated outside the RAM bounds, the device automatically generates an external access. The advantages of operating from on-chip memory are as follows: · · · · Higher performance because no wait states are required Higher performance because of better flow within the pipeline of the central arithmetic logic unit (CALU) Lower cost than external memory Lower power than external memory The advantage of operating from off-chip memory is the ability to access a larger address space. 10 SGUS035 SGUS035 April 2003 Functional Overview 3.1.2 Program Memory Software can configure their memory cells to reside inside or outside of the program address map. When the cells are mapped into program space, the device automatically accesses them when their addresses are within bounds. When the program-address generation (PAGEN) logic generates an address outside its bounds, the device automatically generates an external access. The advantages of operating from on-chip memory are as follows: · · · Higher performance because no wait states are required Lower cost than external memory Lower power than external memory The advantage of operating from off-chip memory is the ability to access a larger address space. 3.1.3 Extended Program Memory The 5416 uses a paged extended memory scheme in program space to allow access of up to 8192K 8192K of program memory. In order to implement this scheme, the 5416 includes several features which are also present on C548/549/5410 C548/549/5410: · · · Twenty-three address lines, instead of sixteen An extra memory-mapped register, the XPC Six extra instructions for addressing extended program space Program memory in the 5416 is organized into 128 pages that are each 64K in length. The value of the XPC register defines the page selection. This register is memory-mapped into data space to address 001Eh. At a hardware reset, the XPC is initialized to 0. 3.2 On-Chip ROM With Bootloader The 5416 features a 16K-word × 16-bit on-chip maskable ROM that can only be mapped into program memory space. Customers can arrange to have the ROM of the 5416 programmed with contents unique to any particular application. A bootloader is available in the standard 5416 on-chip ROM. This bootloader can be used to automatically transfer user code from an external source to anywhere in the program memory at power up. If MP/MC of the device is sampled low during a hardware reset, execution begins at location FF80h of the on-chip ROM. This location contains a branch instruction to the start of the bootloader program. The standard 5416 devices provide different ways to download the code to accommodate various system requirements: · · · · · April 2003 Parallel from 8-bit or 16-bit-wide EPROM Parallel from I/O space, 8-bit or 16-bit mode Serial boot from serial ports, 8-bit or 16-bit mode Host-port interface boot Warm boot SGUS035 SGUS035 11 Functional Overview The standard on-chip ROM layout is shown in Table 3­1. Table 3­1. Standard On-Chip ROM Layout ADDRESS RANGE DESCRIPTION C000h­D4FFh ROM tables for the GSM EFR speech codec D500h­F7FFh Reserved F800h­FBFFh Bootloader FC00h­FCFFh µ-Law expansion table FD00h­FDFFh A-Law expansion table FE00h­FEFFh Sine look-up table Reserved FF00h­FF7Fh FF80h­FFFFh Interrupt vector table In the 5416 ROM, 128 words are reserved for factory device-testing purposes. Application code to be implemented in on-chip ROM must reserve these 128 words at addresses FF00h­FF7Fh in program space. 3.3 On-Chip RAM The 5416 device contains 64K-word × 16-bit of on-chip dual-access RAM (DARAM) and 64K-word × 16-bit of on-chip single-access RAM (SARAM). The DARAM is composed of eight blocks of 8K words each. Each block in the DARAM can support two reads in one cycle, or a read and a write in one cycle. Four blocks of DARAM are located in the address range 0080h­7FFFh in data space, and can be mapped into program/data space by setting the OVLY bit to one. The other four blocks of DARAM are located in the address range 18000h­1FFFFh in program space. The DARAM located in the address range 18000h­1FFFFh in program space can be mapped into data space by setting the DROM bit to one. The SARAM is composed of eight blocks of 8K words each. Each of these eight blocks is a single-access memory. For example, an instruction word can be fetched from one SARAM block in the same cycle as a data word is written to another SARAM block. The SARAM is located in the address range 28000h­2FFFFh, and 38000h­3FFFFh in program space. 3.4 On-Chip Memory Security The 5416 device has a maskable option to protect the contents of on-chip memories. When the ROM protect bit is set, no externally originating instruction can access the on-chip memory spaces; HPI writes have no restriction, but HPI reads are restricted to 4000h ­ 5FFFh. 12 SGUS035 SGUS035 April 2003 Functional Overview 3.5 Memory Map Hex Page 0 Program 0000 Reserved (OVLY = 1) External (OVLY = 0) 007F Hex Page 0 Program 0000 Reserved (OVLY = 1) External (OVLY = 0) 007F On-Chip 0080 DARAM0­3 (OVLY = 1) External (OVLY = 0) 7FFF 8000 0080 7FFF 8000 BFFF C000 External FF7F FF80 FEFF FF00 FF7F FF80 FFFF Interrupts (External) FFFF Hex 0000 005F Memory-Mapped Registers 0060 007F 0080 On-Chip DARAM0­3 (OVLY = 1) External (OVLY = 0) Scratch-Pad RAM On-Chip DARAM0­3 (32K x 16-bit) 7FFF 8000 External On-Chip DARAM4­7 (DROM=1) or External (DROM=0) On-Chip ROM (4K x 16-bit) Reserved Interrupts (On-Chip) MP/MC= 0 (Microcomputer Mode) MP/MC= 1 (Microprocessor Mode) Data Address ranges for on-chip DARAM in data memory are: FFFF DARAM0: 0080h­1FFFh; DARAM2: 4000h­5FFFh; DARAM4: 8000h­9FFFh; DARAM6: C000h­DFFFh; DARAM1: 2000h­3FFFh DARAM3: 6000h­7FFFh DARAM5: A000h­BFFFh DARAM7: E000h­FFFFh Figure 3­2. Program and Data Memory Map Hex 010000 Program Hex 020000 Program On-Chip On-Chip DARAM0­3 DARAM0­3 (OVLY=1) (OVLY=1) External External 017FFF 017FFF (OVLY=0) 027FFF 027FFF (OVLY=0) 018000 On-Chip DARAM4­7 (MP/MC=0) External (MP/MC=1) 01FFFF 01FFFF 028000 On-Chip SARAM0­3 (MP/MC=0) External (MP/MC=1) 02FFFF 02FFFF Page 1 XPC=1 Hex 030000 Program On-Chip DARAM0­3 (OVLY=1) External (OVLY=0) 047FFF 047FFF 038000 048000 On-Chip SARAM4­7 (MP/MC=0) External (MP/MC=1) Hex 7F0000 7F0000 Program On-Chip DARAM0­3 (OVLY=1) External (OVLY=0) 037FFF 037FFF 03FFFF 03FFFF Page 2 XPC=2 Hex 040000 7F7FFF . Address ranges for on-chip DARAM in program memory are: Address ranges for on-chip SARAM in program memory are: On-Chip DARAM0­3 (OVLY=1) External (OVLY=0) 7F8000 7F8000 External External 7FFFFF 04FFFF 04FFFF Page 3 XPC=3 Program Page 4 XPC=4 DARAM4: 018000h­019FFFh; DARAM6: 01C000h­01DFFFh; SARAM0: 028000h­029FFFh; SARAM2: 02C000h­02DFFFh; SARAM4: 038000h­039FFFh; SARAM6: 03C000h­03DFFFh; Page 127 XPC=7Fh DARAM5: 01A000h­01BFFFh DARAM7: 01E000h­01FFFFh SARAM1: 02A000h­02BFFFh SARAM3: 02E000h­02FFFFh SARAM5: 03A000h­03BFFFh SARAM7: 03E000h­03FFFFh Figure 3­3. Extended Program Memory Map April 2003 SGUS035 SGUS035 13 Functional Overview 3.5.1 Relocatable Interrupt Vector Table The reset, interrupt, and trap vectors are addressed in program space. These vectors are soft - meaning that the processor, when taking the trap, loads the program counter (PC) with the trap address and executes the code at the vector location. Four words, either two 1-word instructions or one 2-word instruction, are reserved at each vector location to accommodate a delayed branch instruction which allows branching to the appropriate interrupt service routine without the overhead. At device reset, the reset, interrupt, and trap vectors are mapped to address FF80h in program space. However, these vectors can be remapped to the beginning of any 128-word page in program space after device reset. This is done by loading the interrupt vector pointer (IPTR) bits in the PMST register with the appropriate 128-word page boundary address. After loading IPTR, any user interrupt or trap vector is mapped to the new 128-word page. NOTE: The hardware reset (RS) vector cannot be remapped because the hardware reset loads the IPTR with 1s. Therefore, the reset vector is always fetched at location FF80h in program space. 15 7 6 5 4 3 IPTR MP/MC OVLY AVIS DROM R/W-1FF MP/MC R/W-0 R/W-0 R/W-0 2 CLK OFF R/W-0 1 0 SMUL SST R/W-0 R/W-0 Pin LEGEND: R = Read, W = Write Figure 3­4. Processor Mode Status (PMST) Register 14 SGUS035 SGUS035 April 2003 Functional Overview Table 3­2. Processor Mode Status (PMST) Register Bit Fields BIT NO. NAME 15­7 IPTR RESET VALUE FUNCTION 1FFh Interrupt vector pointer. The 9-bit IPTR field points to the 128-word program page where the interrupt vectors reside. The interrupt vectors can be remapped to RAM for boot-loaded operations. At reset, these bits are all set to 1; the reset vector always resides at address FF80h in program memory space. The RESET instruction does not affect this field. Microprocessor/microcomputer mode. MP/MC enables/disables the on-chip ROM to be addressable in program memory space. 6 MP/MC MP/MC - MP/MC = 0: The on-chip ROM is enabled and addressable. pin - MP/MC = 1: The on-chip ROM is not available. MP/MC is set to the value corresponding to the logic level on the MP/MC pin when sampled at reset. This pin is not sampled again until the next reset. The RESET instruction does not affect this bit. This bit can also be set or cleared by software. RAM overlay. OVLY enables on-chip dual-access data RAM blocks to be mapped into program space. The values for the OVLY bit are: OVLY 0 - OVLY = 0: The on-chip RAM is addressable in data space but not in program space. - 5 OVLY = 1: The on-chip RAM is mapped into program space and data space. Data page 0 (addresses 0h to 7Fh), however, is not mapped into program space. Address visibility mode. AVIS enables/disables the internal program address to be visible at the address pins. AVIS AVIS = 0: The external address lines do not change with the internal program address. Control and data lines are not affected and the address bus is driven with the last address on the bus. - 4 AVIS = 1: This mode allows the internal program address to appear at the pins of the 5416 so that the internal program address can be traced. Also, it allows the interrupt vector to be decoded in conjunction with IACK when the interrupt vectors reside on on-chip memory. 0 DROM enables on-chip DARAM4­7 to be mapped into data space. The DROM bit values are: DROM 0 - DROM = 0: The on-chip DARAM4­7 is not mapped into data space. - 3 DROM = 1: The on-chip DARAM4­7 is mapped into data space. 2 CLKOFF 0 CLOCKOUT off. When the CLKOFF bit is 1, the output of CLKOUT is disabled and remains at a high level. 1 SMUL N/A Saturation on multiplication. When SMUL = 1, saturation of a multiplication result occurs before performing the accumulation in a MAC of MAS instruction. The SMUL bit applies only when OVM = 1 and FRCT = 1. 0 SST N/A Saturation on store. When SST = 1, saturation of the data from the accumulator is enabled before storing in memory. The saturation is performed after the shift operation. 3.6 On-Chip Peripherals The 5416 device has the following peripherals: · · · · · · · · April 2003 Software-programmable wait-state generator Programmable bank-switching A host-port interface (HPI8/16 HPI8/16) Three multichannel buffered serial ports (McBSPs) A hardware timer A clock generator with a multiple phase-locked loop (PLL) Enhanced external parallel interface (XIO2) A DMA controller (DMA) SGUS035 SGUS035 15 Functional Overview 3.6.1 Software-Programmable Wait-State Generator The software wait-state generator of the 5416 can extend external bus cycles by up to fourteen machine cycles. Devices that require more than fourteen wait states can be interfaced using the hardware READY line. When all external accesses are configured for zero wait states, the internal clocks to the wait-state generator are automatically disabled. Disabling the wait-state generator clocks reduces the power consumption of the 5416. The software wait-state register (SWWSR) controls the operation of the wait-state generator. The 14 LSBs of the SWWSR specify the number of wait states (0 to 7) to be inserted for external memory accesses to five separate address ranges. This allows a different number of wait states for each of the five address ranges. Additionally, the software wait-state multiplier (SWSM) bit of the software wait-state control register (SWCR) defines a multiplication factor of 1 or 2 for the number of wait states. At reset, the wait-state generator is initialized to provide seven wait states on all external memory accesses. The SWWSR bit fields are shown in Figure 3­5 and described in Table 3­3. 15 14 12 11 9 8 6 5 3 2 0 XPA I/O Data Data Program Program R/W-0 R/W-111 R/W-111 R/W-111 R/W-111 R/W-111 R/W-111 R/W-111 R/W-111 R/W-111 R/W-111 LEGEND: R=Read, W=Write, 0=Value after reset Figure 3­5. Software Wait-State Register (SWWSR) [Memory-Mapped Register (MMR) Address 0028h] Table 3­3. Software Wait-State Register (SWWSR) Bit Fields BIT NO. NAME RESET VALUE 15 XPA 0 14­12 I/O 111 I/O space. The field value (0­7) corresponds to the base number of wait states for I/O space accesses within addresses 0000­FFFFh. The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for the base number of wait states. 11­9 Data 111 Upper data space. The field value (0­7) corresponds to the base number of wait states for external data space accesses within addresses 8000­FFFFh. The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for the base number of wait states. 8­6 Data 111 Lower data space. The field value (0­7) corresponds to the base number of wait states for external data space accesses within addresses 0000­7FFFh. The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for the base number of wait states. FUNCTION Extended program address control bit. XPA is used in conjunction with the program space fields (bits 0 through 5) to select the address range for program space wait states. Upper program space. The field value (0­7) corresponds to the base number of wait states for external program space accesses within the following addresses: Program 111 - XPA = 0: xx8000 ­ xxFFFFh - 5­3 XPA = 1: 400000h ­ 7FFFFFh The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for the base number of wait states. Program space. The field value (0­7) corresponds to the base number of wait states for external program space accesses within the following addresses: Program 111 - XPA = 0: xx0000 ­ xx7FFFh - 2­0 XPA = 1: 000000 ­ 3FFFFFh The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for the base number of wait states. 16 SGUS035 SGUS035 April 2003 Functional Overview The software wait-state multiplier bit of the software wait-state control register (SWCR) is used to extend the base number of wait states selected by the SWWSR. The SWCR bit fields are shown in Figure 3­6 and described in Table 3­4. 15 1 0 Reserved SWSM R/W-0 R/W-0 LEGEND: R = Read, W = Write Figure 3­6. Software Wait-State Control Register (SWCR) [MMR Address 002Bh] Table 3­4. Software Wait-State Control Register (SWCR) Bit Fields PIN NO. NAME RESET VALUE 15­1 Reserved 0 FUNCTION These bits are reserved and are unaffected by writes. Software wait-state multiplier. Used to multiply the number of wait states defined in the SWWSR by a factor of 1 or 2. 0 SWSM 0 - SWSM = 0: wait-state base values are unchanged (multiplied by 1). - SWSM = 1: wait-state base values are multiplied by 2 for a maximum of 14 wait states. 3.6.2 Programmable Bank-Switching Programmable bank-switching logic allows the 5416 to switch between external memory banks without requiring external wait states for memories that need additional time to turn off. The bank-switching logic automatically inserts one cycle when accesses cross a 32K-word memory-bank boundary inside program or data space. Bank-switching is defined by the bank-switching control register (BSCR), which is memory-mapped at address 0029h. The bit fields of the BSCR are shown in Figure 3­7 and are described in Table 3­5. R = Read, W = Write 15 14 13 12 11 2 1 0 CONSEC DIVFCT IACKOFF Reserved HBH BH Res R/W-1 R/W-11 R/W-11 R/W-1 R R/W-0 R/W-0 R Figure 3­7. Bank-Switching Control Register (BSCR) [MMR Address 0029h] April 2003 SGUS035 SGUS035 17 Functional Overview Table 3­5. Bank-Switching Control Register (BSCR) Fields BIT NAME RESET VALUE FUNCTION Consecutive bank-switching. Specifies the bank-switching mode. 1 CONSEC = 0: Bank-switching on 32K bank boundaries only. This bit is cleared if fast access is desired for continuous memory reads (i.e., no starting and trailing cycles between read cycles). CONSEC = 1: CONSEC 15 Consecutive bank switches on external memory reads. Each read cycle consists of 3 cycles: starting cycle, read cycle, and trailing cycle. CLKOUT output divide factor. The CLKOUT output is driven by an on-chip source having a frequency equal to 1/(DIVFCT+1) of the DSP clock. DIVFCT = 00: 11 CLKOUT is not divided. CLKOUT is divided by 2 from the DSP clock. CLKOUT is divided by 3 from the DSP clock. DIVFCT = 11: DIVFCT DIVFCT = 01: DIVFCT = 10: 13­14 13 14 CLKOUT is divided by 4 from the DSP clock (default value following reset). IACK signal output off. Controls the output of the IACK signal. IACKOFF is set to 1 at reset. IACKOFF Rsvd 11­3 1 ­ IACKOFF = 0: The IACK signal output off function is disabled. IACKOFF = 1: 12 The IACK signal output off function is enabled. Reserved HPI bus holder. Controls the HPI bus holder. HBH is cleared to 0 at reset. HBH 0 HBH = 0: The bus holder is disabled except when HPI16 HPI16 = 1. HBH = 1: 2 The bus holder is enabled. When not driven, the HPI data bus, HD[7:0] is held in the previous logic level. Bus holder. Controls the bus holder. BH is cleared to 0 at reset. BH 0 Rsvd 0 ­ BH = 0: The bus holder is disabled. BH = 1: 1 The bus holder is enabled. When not driven, the data bus, D[15:0] is held in the previous logic level. Reserved For additional information, see Section 3.11 of this document. The 5416 has an internal register that holds the MSB of the last address used for a read or write operation in program or data space. In the non-consecutive bank switches (CONSEC = 0), if the MSB of the address used for the current read does not match that contained in this internal register, the MSTRB (memory strobe) signal is not asserted for one CLKOUT cycle. During this extra cycle, the address bus switches to the new address. The contents of the internal register are replaced with the MSB for the read of the current address. If the MSB of the address used for the current read matches the bits in the register, a normal read cycle occurs. In non-consecutive bank switches (CONSEC = 0), if repeated reads are performed from the same memory bank, no extra cycles are inserted. When a read is performed from a different memory bank, memory conflicts are avoided by inserting an extra cycle. For more information, see Section 3.11 of this document. The bank-switching mechanism automatically inserts one extra cycle in the following cases: · · · · 18 A memory read followed by another memory read from a different memory bank. A program-memory read followed by a data-memory read. A data-memory read followed by a program-memory read. A program-memory read followed by another program-memory read from a different page. SGUS035 SGUS035 April 2003 Functional Overview 3.6.3 Bus Holders The 5416 has two bus holder control bits, BH (BSCR[1]) and HBH (BSCR[2]), to control the bus keepers of the address bus (A[17­0]), data bus (D[15­0]), and the HPI data bus (HD[7­0]). Bus keeper enabling/disabling is described in Table 3­5. Table 3­6. Bus Holder Control Bits HPI16 HPI16 PIN HBH D[15­0] A[17­0] HD[7­0] 0 0 0 OFF OFF OFF 0 0 1 OFF OFF ON 0 1 0 ON OFF OFF 0 1 1 ON OFF ON 1 0 0 OFF OFF ON 1 0 1 OFF ON ON 1 1 0 ON OFF ON 1 3.7 BH 1 1 ON ON ON Parallel I/O Ports The 5416 has a total of 64K I/O ports. These ports can be addressed by the PORTR instruction or the PORTW instruction. The IS signal indicates a read/write operation through an I/O port. The 5416 can interface easily with external devices through the I/O ports while requiring minimal off-chip address-decoding circuits. 3.7.1 Enhanced 8-/16-Bit Host-Port Interface (HPI8/16 HPI8/16) The 5416 host-port interface, also referred to as the HPI8/16 HPI8/16, is an enhanced version of the standard 8-bit HPI found on earlier TMS320C54x DSPs (542, 545, 548, and 549). The 5416 HPI can be used to interface to an 8-bit or 16-bit host. When the address and data buses for external I/O is not used (to interface to external devices in program/data/IO spaces), the 5416 HPI can be configured as an HPI16 HPI16 to interface to a 16-bit host. This configuration can be accomplished by connecting the HPI16 HPI16 pin to logic "1". When the HPI16 HPI16 pin is connected to a logic "0", the 5416 HPI is configured as an HPI8. The HPI8 is an 8-bit parallel port for interprocessor communication. The features of the HPI8 include: Standard features: · · · Sequential transfers (with autoincrement) or random-access transfers Host interrupt and C54x interrupt capability Multiple data strobes and control pins for interface flexibility The HPI8 interface consists of an 8-bit bidirectional data bus and various control signals. Sixteen-bit transfers are accomplished in two parts with the HBIL input designating high or low byte. The host communicates with the HPI8 through three dedicated registers - the HPI address register (HPIA), the HPI data register (HPID), and the HPI control register (HPIC). The HPIA and HPID registers are only accessible by the host, and the HPIC register is accessible by both the host and the 5416. Enhanced features: · · Access to entire on-chip RAM through DMA bus Capability to continue transferring during emulation stop TMS320C54x and C54x are trademarks of Texas Instruments. April 2003 SGUS035 SGUS035 19 Functional Overview The HPI16 HPI16 is an enhanced 16-bit version of the TMS320C54x DSP 8-bit host-port interface (HPI8). The HPI16 HPI16 is designed to allow a 16-bit host to access the DSP on-chip memory, with the host acting as the master of the interface. Some of the features of the HPI16 HPI16 include: · · · · · · 16-bit bidirectional data bus Multiple data strobes and control signals to allow glueless interfacing to a variety of hosts Only nonmultiplexed address/data modes are supported 18-bit address bus used in nonmultiplexed mode to allow access to all internal memory (including internal extended address pages) HRDY signal to hold off host accesses due to DMA latency The HPI16 HPI16 acts as a slave to a 16-bit host processor and allows access to the on-chip memory of the DSP. NOTE: Only the nonmultiplexed mode is supported when the 5416 HPI is configured as a HPI16 HPI16 (see Figure 3­8). The 5416 HPI functions as a slave and enables the host processor to access the on-chip memory. A major enhancement to the 5416 HPI over previous versions is that it allows host access to the entire on-chip memory range of the DSP. The host and the DSP both have access to the on-chip RAM at all times and host accesses are always synchronized to the DSP clock. If the host and the DSP contend for access to the same location, the host has priority, and the DSP waits for one cycle. Note that since host accesses are always synchronized to the 5416 clock, an active input clock (CLKIN) is required for HPI accesses during IDLE states, and host accesses are not allowed while the 5416 reset pin is asserted. 3.7.2 HPI Nonmultiplexed Mode In nonmultiplexed mode, a host with separate address/data buses can access the HPI16 HPI16 data register (HPID) via the HD 16-bit bidirectional data bus, and the address register (HPIA) via the 18-bit HA address bus. The host initiates the access with the strobe signals (HDS1, HDS2, HCS) and controls the direction of the access with the HR/W signal. The HPI16 HPI16 can stall host accesses via the HRDY signal. Note that the HPIC register is not available in nonmultiplexed mode since there are no HCNTL signals available. All host accesses initiate a DMA read or write access. Figure 3­8 shows a block diagram of the HPI16 HPI16 in nonmultiplexed mode. DATA[15:0] HPI16 HPI16 PPD[15:0] HINT HPID[15:0] DMA Address[17:0] VCC Internal Memory HOST HCNTL0 HCNTL1 HBIL HAS R/W HR/W Data Strobes READY HRDY HDS1, HDS2, HCS 54xx CPU Figure 3­8. Host-Port Interface - Nonmultiplexed Mode 20 SGUS035 SGUS035 April 2003 Functional Overview Address (Hex) 000 0000 Reserved 000 005F 000 0060 000 007F 000 0080 Scratch-Pad RAM DARAM0 ­ DARAM3 000 7FFF 000 8000 Reserved 001 7FFF 001 8000 DARAM4 ­ DARAM7 001 FFFF 002 0000 Reserved 002 7FFF 002 8000 002 FFFF 003 0000 SARAM0 ­ SARAM3 Reserved 003 7FFF 003 8000 SARAM4 ­ SARAM7 003 FFFF 004 0000 Reserved 07F FFFF Figure 3­9. HPI Memory Map April 2003 SGUS035 SGUS035 21 Functional Overview 3.8 Multichannel Buffered Serial Ports (McBSPs) The 5416 device provides three high-speed, full-duplex, multichannel buffered serial ports that allow direct interface to other C54x/LC54x devices, codecs, and other devices in a system. The McBSPs are based on the standard serial-port interface found on other 54x devices. Like their predecessors, the McBSPs provide: · · · Full-duplex communication Double-buffer data registers, which allow a continuous data stream Independent framing and clocking for receive and transmit In addition, the McBSPs have the following capabilities: · Direct interface to: ­ ­ MVIP switching compatible and ST-BUS compliant devices ­ IOM-2 compliant devices ­ AC97-compliant devices ­ IIS-compliant devices ­ · · · · · T1/E1 framers Serial peripheral interface Multichannel transmit and receive of up to 128 channels A wide selection of data sizes, including 8, 12, 16, 20, 24, or 32 bits µ-law and A-law companding Programmable polarity for both frame synchronization and data clocks Programmable internal clock and frame generation The McBSP consists of a data path and control path. The six pins, BDX, BDR, BFSX, BFSR, BCLKX, and BCLKR, connect the control and data paths to external devices. The implemented pins can be programmed as general-purpose I/O pins if they are not used for serial communication. The data is communicated to devices interfacing to the McBSP by way of the data transmit (BDX) pin for transmit and the data receive (BDR) pin for receive. The CPU or DMA reads the received data from the data receive register (DRR) and writes the data to be transmitted to the data transmit register (DXR). Data written to the DXR is shifted out to BDX by way of the transmit shift register (XSR). Similarly, receive data on the BDR pin is shifted into the receive shift register (RSR) and copied into the receive buffer register (RBR). RBR is then copied to DRR, which can be read by the CPU or DMA. This allows internal data movement and external data communications simultaneously. Control information in the form of clocking and frame synchronization is communicated by way of BCLKX, BCLKR, BFSX, and BFSR. The device communicates to the McBSP by way of 16-bit-wide control registers accessible via the internal peripheral bus. The control block consists of internal clock generation, frame synchronization signal generation, and their control, and multichannel selection. This control block sends notification of important events to the CPU and DMA by way of two interrupt signals, XINT and RINT, and two event signals, XEVT and REVT. The on-chip companding hardware allows compression and expansion of data in either µ-law or A-law format. When companding is used, transmitted data is encoded according to the specified companding law and received data is decoded to 2s complement format. The sample rate generator provides the McBSP with several means of selecting clocking and framing for both the receiver and transmitter. Both the receiver and transmitter can select clocking and framing independently. The McBSP allows the multiple channels to be independently selected for the transmitter and receiver. When multiple channels are selected, each frame represents a time-division multiplexed (TDM) data stream. In using time-division multiplexed data streams, the CPU may only need to process a few of them. Thus, to save memory and bus bandwidth, multichannel selection allows independent enabling of particular channels for transmission and reception. All 128 channels in a bit stream consisting of a maximum of 128 channels can be enabled. 22 SGUS035 SGUS035 April 2003 Functional Overview 15 10 9 8 7 6 5 4 2 1 0 Reserved XMCME XPBBLK XPABLK XCBLK XMCM R R/W R/W R/W R R/W 15 10 9 8 7 6 5 4 2 1 0 Reserved RMCME RPBBLK RPABLK RCBLK Resvd RMCM R R/W R/W R/W R R R/W LEGEND: R = Read, W = Write Figure 3­10. Multichannel Control Registers (MCR1 and MCR2) The 5416 McBSP has two working modes: · In the first mode, when (R/X)MCME = 0, it is comparable with the McBSPs used in the 5410 where the normal 32-channel selection is enabled (default). In the second mode, when (R/X)MCME = 1, it has 128-channel selection capability. Multichannel control register Bit 9, (R/X)MCME, is used as the 128-channel selection enable bit. Once (R/X)MCME = 1, twelve new registers (R/X)CERC ­ (R/X)CERH) are used to enable the 128-channel selection. · The clock stop mode (CLKSTP) in the McBSP provides compatibility with the serial port interface protocol. Clock stop mode works with only single-phase frames and one word per frame. The word sizes supported by the McBSP are programmable for 8-, 12-, 16-, 20-, 24-, or 32-bit operation. When the McBSP is configured to operate in SPI mode, both the transmitter and the receiver operate together as a master or as a slave. Although the BCLKS pin is not available on the 5416 HFG package, the 5416 is capable of synchronization to external clock sources. BCLKX or BCLKR can be used by the sample rate generator for external synchronization. The sample rate clock mode extended (SCLKME) bit field is located in the PCR to accommodate this option. 15 13 12 11 10 9 8 Reserved 14 XIOEN RIOEN FSXM FSRM CLKXM CLKRM RW RW RW RW RW RW RW 7 6 5 4 3 2 1 0 SCLKME CLKS STAT DX STAT DR STAT FSXP FSRP CLKXP CLKRP RW RW RW RW RW RW RW RW Legend: R = Read, W = Write Figure 3­11. Pin Control Register (PCR) The selection of sample rate input clock is made by the combination of the CLKSM (bit 13 in SRGR2) bit value and the SCLKME bit value as shown in Table 3­7. Table 3­7. Sample Rate Input Clock Selection SCLKME SAMPLE RATE CLOCK MODE 0 0 Reserved (CLKS pin unavailable) 0 1 CPU clock 1 0 BCLKR 1 April 2003 CLKSM 1 BCLKX SGUS035 SGUS035 23 Functional Overview When the SCLKME bit is cleared to 0, the CLKSM bit is used, as before, to select either the CPU clock or the CLKS pin (not bonded out on the 5416 device package) as the sample rate input clock. Setting the SCLKME bit to 1 enables the CLKSM bit to select between the BCLKR pin or BCLKX pin for the sample rate input clock. When either the BCLKR or CLKX is configured this way, the output buffer for the selected pin is automatically disabled. For example, with SCLKME = 1 and CLKSM = 0, the BCLKR pin is configured as the input of the sample rate generator. Both the transmitter and receiver circuits can be synchronized to the sample rate generator output by setting the CLKXM and CLKRM bits of the pin configuration register (PCR) to 1. Note that the sample rate generator output will only be driven on the BCLKX pin since the BCLKR output buffer is automatically disabled. The McBSP is fully static and operates at arbitrary low clock frequencies. For maximum operating frequency, see Section 5.14. 3.9 Hardware Timer The 5416 device features a 16-bit timing circuit with a 4-bit prescaler. The timer counter is decremented by one every CLKOUT cycle. Each time the counter decrements to 0, a timer interrupt is generated. The timer can be stopped, restarted, reset, or disabled by specific status bits. 3.10 Clock Generator The clock generator provides clocks to the 5416 device, and consists of a phase-locked loop (PLL) circuit. The clock generator requires a reference clock input, which can be provided from an external clock source. The reference clock input is then divided by two (DIV mode) to generate clocks for the 5416 device, or the PLL circuit can be used (PLL mode) to generate the device clock by multiplying the reference clock frequency by a scale factor, allowing use of a clock source with a lower frequency than that of the CPU. The PLL is an adaptive circuit that, once synchronized, locks onto and tracks an input clock signal. When the PLL is initially started, it enters a transitional mode during which the PLL acquires lock with the input signal. Once the PLL is locked, it continues to track and maintain synchronization with the input signal. Then, other internal clock circuitry allows the synthesis of new clock frequencies for use as master clock for the 5416 device. This clock generator allows system designers to select the clock source. The sources that drive the clock generator are: · · A crystal resonator circuit. The crystal resonator circuit is connected across the X1 and X2/CLKIN pins of the 5416 to enable the internal oscillator. An external clock. The external clock source is directly connected to the X2/CLKIN pin, and X1 is left unconnected. NOTE: The crystal oscillator function is not supported by all die revisions of the 5416 device. See the TMS320VC5416 TMS320VC5416 Silicon Errata (literature number SPRZ172 SPRZ172) to verify which die revisions support this functionality. The software-programmable PLL features a high level of flexibility, and includes a clock scaler that provides various clock multiplier ratios, capability to directly enable and disable the PLL, and a PLL lock timer that can be used to delay switching to PLL clocking mode of the device until lock is achieved. Devices that have a built-in software-programmable PLL can be configured in one of two clock modes: · · PLL mode. The input clock (X2/CLKIN) is multiplied by 1 of 31 possible ratios. DIV (divider) mode. The input clock is divided by 2 or 4. Note that when DIV mode is used, the PLL can be completely disabled in order to minimize power dissipation. The software-programmable PLL is controlled using the 16-bit memory-mapped (address 0058h) clock mode register (CLKMD). The CLKMD register is used to define the clock configuration of the PLL clock module. Note that upon reset, the CLKMD register is initialized with a predetermined value dependent only upon the state of the CLKMD1 ­ CLKMD3 pins. For more programming information, see the TMS320C54x DSP Reference Set, Volume 1: CPU and Peripherals (literature number SPRU131 SPRU131). The CLKMD pin configured clock options are shown in Table 3­8. 24 SGUS035 SGUS035 April 2003 Functional Overview Table 3­8. Clock Mode Settings at Reset CLKMD1 CLKMD2 CLKMD3 CLKMD RESET VALUE 0 0 0 0000h 1/2 (PLL disabled) 0 0 1 9007h PLL x 10 0 1 0 4007h PLL x 5 1 0 0 1007h PLL x 2 1 1 0 F007h PLL x 1 1 1 1 0000h 1/2 (PLL disabled) 1 0 1 F000h 1/4 (PLL disabled) 0 1 1 - CLOCK MODE Reserved (Bypass mode) The external CLKMD1­CLKMD3 pins are sampled to determine the desired clock generation mode while RS is low. Following reset, the clock generation mode can be reconfigured by writing to the internal clock mode register in software. 3.11 Enhanced External Parallel Interface (XIO2) The 5416 external interface has been redesigned to include several improvements, including: simplification of the bus sequence, more immunity to bus contention when transitioning between read and write operations, the ability for external memory access to the DMA controller, and optimization of the power-down modes. The bus sequence on the 5416 still maintains all of the same interface signals as on previous 54x devices, but the signal sequence has been simplified. Most external accesses now require 3 cycles composed of a leading cycle, an active (read or write) cycle, and a trailing cycle. The leading and trailing cycles provide additional immunity against bus contention when switching between read operations and write operations. To maintain high-speed read access, a consecutive read mode that performs single-cycle reads as on previous 54x devices is available. April 2003 SGUS035 SGUS035 25 Functional Overview Figure 3­12 shows the bus sequence for three cases: all I/O reads, memory reads in nonconsecutive mode, or single memory reads in consecutive mode. The accesses shown in Figure 3­12 always require 3 CLKOUT cycles to complete. CLKOUT A[22:0] D[15:0] READ R/W MSTRB or IOSTRB PS/DS/IS Leading Cycle Read Cycle Trailing Cycle Figure 3­12. Nonconsecutive Memory Read and I/O Read Bus Sequence 26 SGUS035 SGUS035 April 2003 Functional Overview Figure 3­13 shows the bus sequence for repeated memory reads in consecutive mode. The accesses shown in Figure 3­13 require (2 + n) CLKOUT cycles to complete, where n is the number of consecutive reads performed. CLKOUT A[22:0] READ D[15:0] READ READ R/W MSTRB PS/DS Leading Cycle Read Cycle Read Cycle Read Cycle Trailing Cycle Figure 3­13. Consecutive Memory Read Bus Sequence (n = 3 reads) April 2003 SGUS035 SGUS035 27 Functional Overview Figure 3­14 shows the bus sequence for all memory writes and I/O writes. The accesses shown in Figure 3­14 always require 3 CLKOUT cycles to complete. CLKOUT A[22:0] WRITE D[15:0] R/W MSTRB or IOSTRB PS/DS/IS Leading Cycle Write Cycle Trailing Cycle Figure 3­14. Memory Write and I/O Write Bus Sequence The enhanced interface also provides the ability for DMA transfers to extend to external memory. For more information on DMA capability, see the DMA sections that follow. The enhanced interface improves the low-power performance already present on the TMS320C5000 TMS320C5000 DSP platform by switching off the internal clocks to the interface when it is not being used. This power-saving feature is automatic, requires no software setup, and causes no latency in the operation of the interface. Additional features integrated in the enhanced interface are the ability to automatically insert bank-switching cycles when crossing 32K memory boundaries (see Section 3.6.2), the ability to program up to 14 wait states through software (see Section 3.6.1), and the ability to divide down CLKOUT by a factor of 1, 2, 3, or 4. Dividing down CLKOUT provides an alternative to wait states when interfacing to slower external memory or peripheral devices. While inserting wait states extends the bus sequence during read or write accesses, it does not slow down the bus signal sequences at the beginning and the end of the access. Dividing down CLKOUT provides a method of slowing the entire bus sequence when necessary. The CLKOUT divide-down factor is controlled through the DIVFCT field in the bank-switching control register (BSCR) (see Table 3­5). 3.12 DMA Controller The 5416 direct memory access (DMA) controller transfers data between points in the memory map without intervention by the CPU. The DMA allows movements of data to and from internal program/data memory, internal peripherals (such as the McBSPs), or external memory devices to occur in the background of CPU operation. The DMA has six independent programmable channels, allowing six different contexts for DMA operation. TMS320C5000 TMS320C5000 is a trademark of Texas Instruments. 28 SGUS035 SGUS035 April 2003 Functional Overview 3.12.1 Features The DMA has the following features: · · · · · · · · 3.12.2 The DMA operates independently of the CPU. The DMA has six channels. The DMA can keep track of the contexts of six independent block transfers. The DMA has higher priority than the CPU for both internal and external accesses. Each channel has indepe