SMJ320C80 SGUS025B IEEE-754 MILPRF38535 100-MFLOPS IEEE-1149 IEEE1149 4064M - Datasheet Archive

 

DIGITAL SIGNAL PROCESSOR SGUS025B ­ AUGUST 1998 ­ REVISED JUNE 2002 D Single-Chip Parallel Multiple D D D D D D D D D D D

 

SMJ320C80 SMJ320C80 DIGITAL SIGNAL PROCESSOR SGUS025B SGUS025B ­ AUGUST 1998 ­ REVISED JUNE 2002 D Single-Chip Parallel Multiple D D D D D D D D D D D D Instruction/Multiple Data (MIMD) Digital Signal Processor (DSP) More Than Two Billion RISC-Equivalent Operations per Second Master Processor (MP) ­ 32-Bit Reduced Instruction Set Computing (RISC) Processor ­ IEEE-754 IEEE-754 Floating-Point Capability ­ 4K-Byte Instruction Cache ­ 4K-Byte Data Cache Four Parallel Processors (PP) ­ 32-Bit Advanced DSPs ­ 64-Bit Opcode Provides Many Parallel Operations per Cycle ­ 2K-Byte Instruction Cache and 8K-Byte Data RAM per PP Transfer Controller (TC) ­ 64-Bit Data Transfers ­ Up to 400 Megabytes per Second (MBps) Transfer Rate ­ 32-Bit Addressing ­ Direct DRAM/VRAM Interface With Dynamic Bus Sizing ­ Intelligent Queuing and Cycle Prioritization Video Controller (VC) ­ Provides Video Timing and Video Random-Access Memory (VRAM) Control ­ Dual-Frame Timers for Two Simultaneous Image-Capture and/or Display Systems Big- or Little-Endian Operation 50K-Byte On-Chip RAM 4G-Byte Address Space 20-ns Cycle Time 3.3-V Operation IEEE Standard 1149.1 Test Access Port (JTAG) Operating Temperature Range ­55°C to 125°C - M-Temperature ­40°C to 85°C - A-Temperature GF PACKAGE (BOTTOM VIEW) 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 AR AP AN AM AL AK AH AF AJ AG AD AB Y V T P M K H F D B AE AC AA W U R N L J G E C A HFH PACKAGE (TOP VIEW) 320 1 241 240 161 160 80 81 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. IEEE Standard 1149.1­1990, IEEE Standard Test Access Port and Boundary-Scan Architecture Copyright 2002, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 1443 On products compliant to MILPRF38535 MILPRF38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters. · HOUSTON, TEXAS 77251­1443 1 SMJ320C80 SMJ320C80 DIGITAL SIGNAL PROCESSOR SGUS025B SGUS025B ­ AUGUST 1998 ­ REVISED JUNE 2002 Table of Contents description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 GF Pin Assignments ­ Numerical Listing . . . . . . . . . . . . . . . . 3 GF Pin Assignments ­ Alphabetical Listing . . . . . . . . . . . . . . 5 HFH Pin Assignments ­ Numerical Listing . . . . . . . . . . . . . . 7 HFH Pin Assignments ­ Alphabetical Listing . . . . . . . . . . . . 9 Terminal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 master processor (MP) architecture . . . . . . . . . . . . . . . . . . . 17 MP control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 MP parameter RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 MP interrupt vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 PP architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 PP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 PP data-unit registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 PP address-unit registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 PP program flow control (PFC) unit registers . . . . . . . . . . . 40 PP cache architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 PP parameter RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 PP-interrupt vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 PP data-unit architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 PP multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 PP program-flow-control unit architecture . . . . . . . . . . . . . . 46 PP address-unit architecture . . . . . . . . . . . . . . . . . . . . . . . . . 48 PP instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 PP opcode formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 EALU operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 TC architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 local memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 external memory timing examples . . . . . . . . . . . . . . . . . . . . 73 host interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . absolute maximum ratings over specified temperature ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . recommended operating conditions . . . . . . . . . . . . . . . . . . electrical characteristics over recommended range of supply voltage and specified temperature . . . . . . . . signal transition levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . timing parameter symbology . . . . . . . . . . . . . . . . . . . . . . . . general notes on timing parameters . . . . . . . . . . . . . . . . . . CLKIN timing requirements . . . . . . . . . . . . . . . . . . . . . . . . . local-bus switching characteristics over full operating range: CLKOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . device reset timing requirements . . . . . . . . . . . . . . . . . . . . local bus timing requirements: cycle configuration inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . local bus timing: cycle completion inputs . . . . . . . . . . . . . . general output signal characteristics over operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . data input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . local bus timing: 2-cycle/column CAS timing . . . . . . . . . . . external interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . XPT input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . host-interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . video interface timing: SCLK timing . . . . . . . . . . . . . . . . . . video interface timing: FCLK input and video outputs . . . video interface timing: external sync inputs . . . . . . . . . . . emulator interface connection . . . . . . . . . . . . . . . . . . . . . . . MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 128 129 129 129 130 131 132 132 132 133 134 135 138 140 141 142 143 144 145 146 147 148 151 152 description The SMJ320C80 SMJ320C80 is a single-chip, MIMD parallel processor capable of performing over two billion operations per second. It consists of a 32-bit RISC master processor with a 100-MFLOPS 100-MFLOPS (million floating-point operations per second) IEEE floating-point unit, four 32-bit parallel processing digital signal processors (DSPs), a transfer controller with up to 400-MBps off-chip transfer rate, and a video controller. All the processors are coupled tightly through an on-chip crossbar that provides shared access to on-chip RAM. This performance and programmability make the 'C80 ideally suited for video, imaging, and high-speed telecommunications applications. 2 POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 SMJ320C80 SMJ320C80 DIGITAL SIGNAL PROCESSOR SGUS025B SGUS025B ­ AUGUST 1998 ­ REVISED JUNE 2002 GF Pin Assignments ­ Numerical Listing PIN NUMBER PIN PIN PIN NAME NUMBER NAME NUMBER NAME A5 CT1 C21 VDD HACK C23 VDD W E33 A7 E35 C25 DBEN F2 C27 C29 VSS CAREA0 F4 A13 VSS CAS/DQM7 A15 CAS/DQM5 C31 CBLNK0/VBLNK0 F10 A17 D2 RETRY F12 A19 VDD VSS D4 F14 A21 RAS D6 VDD VSS A23 DSF D8 AS0 F18 A25 VSS SCLK1 D10 UTIME F20 D12 F22 D14 A31 VDD EINT1 VSS RESET D16 REQ0 F26 B2 NC D18 F28 B4 BS1 D20 VSS CAS/DQM0 B6 D22 FCLK1 F34 B8 VDD PS1 D24 B10 REQ1 D26 VSS CAREA1 B12 D28 SCLK0 B14 VDD CAS/DQM6 D30 EINT2 R5 CAS/DQM3 D32 G33 CBLNK1/VBLNK1 R31 B18 D34 G35 E1 AS1 H2 VDD STATUS0 R33 B20 VDD CAS/DQM1 VSS VDD VSYNC0 G31 B16 B22 TRG/CAS E3 FAULT H4 A3 T2 VSS A5 B24 E5 CSYNC1/HBLNK1 T4 A13 E7 VSS STATUS2 H32 B26 VDD DDIN H34 TDI T32 D62 B28 FCLK0 E9 READY J1 STATUS1 T34 EMU0 B30 VDD CSYNC0/HBLNK0 E11 BS0 J3 J5 U3 VDD A10 J31 VSS VDD VDD U1 E13 U5 PS3 A9 A11 A27 A29 B32 NUMBER NAME HSYNC0 L5 TCK L31 VSS VSS VDD VSS L33 TRST L35 XPT1 VDD VSS M2 VDD VSS VDD PS0 M32 VSS CT2 N1 VSS VDD VDD N3 A8 N5 N31 VSS VSS VDD VSS N33 TMS N35 VDD VSS P2 VDD A4 P4 A9 P32 TDO G1 VDD VDD P34 XPT0 G3 A2 R1 G5 A1 R3 VSS VDD VDD F8 F16 VDD VSS F24 F32 M4 M34 R35 VDD VDD E15 C5 VSS STATUS3 VSS HREQ E17 CAS/DQM4 J33 NC AS2 E19 RL J35 VSS EMU1 U31 C7 U33 D61 C9 VSS CT0 E21 STATUS5 K2 STATUS4 U35 C11 E23 K4 A6 V2 VDD VDD C13 PS2 E25 VSS CLKOUT K32 VSYNC1 V4 C15 VDD CLKIN E27 LINT4 K34 HSYNC1 V32 C17 E29 EINT3 L1 A0 V34 C19 CAS/DQM2 E31 VSS L3 A7 W1 C3 POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 VSS VSS VDD A11 3 SMJ320C80 SMJ320C80 DIGITAL SIGNAL PROCESSOR SGUS025B SGUS025B ­ AUGUST 1998 ­ REVISED JUNE 2002 GF Pin Assignments ­ Numerical Listing (Continued) PIN NUMBER PIN NAME NUMBER PIN NAME NUMBER PIN NAME NUMBER NAME W3 A18 AG1 A16 AL17 D20 AN29 D35 W5 AG3 VSS VDD AL19 D21 AN31 D45 W31 VSS VSS AL21 D24 AN33 W33 D59 AG31 AL23 VDD A27 D63 AG33 AL25 VSS D29 AP4 W35 VDD VSS Y2 A12 AG35 D57 AL27 D32 AP8 VDD D5 Y4 A19 AH2 A20 AL29 D38 AP10 D8 Y32 XPT2 AH4 A30 AL31 AP12 Y34 D56 AH32 D44 AL33 VSS D48 AP14 VDD D13 AA1 VSS VDD AH34 D54 AL35 D53 AP16 D17 AJ1 A24 AP18 AJ3 VDD A31 AM2 VDD VDD AM4 AP20 VDD D26 AM6 AP22 D34 AJ31 AM8 D2 AP24 AA35 VDD VSS VSS VSS VDD VSS AJ33 D42 AM10 D6 AP26 VDD D39 AB2 A14 AJ35 D41 AK2 AM14 VSS D14 AP28 A21 VDD VDD AM12 AB4 AP30 AB32 D55 AK4 AM16 D19 AP32 VDD D47 AB34 D60 AK8 VSS VDD AM18 D0 VDD A22 AK10 VSS VDD AM20 VSS D23 AR5 AC1 AR7 AM22 D25 AR9 VDD D7 AK14 AM26 VSS D31 AR11 AK16 VSS VDD AM24 AC31 VSS VSS AR13 VSS D11 AC33 D52 AK18 NC AM28 D33 AR15 D15 AC35 VDD VDD AK20 VSS D27 AM30 AR17 AM32 VSS VDD AR19 VSS VDD VSS VSS AK24 VDD VSS AM34 D50 AR21 D30 AN5 A29 AR23 D36 VDD A15 AK28 VDD VSS AN7 D1 AR25 AE1 AN9 AR27 VSS D40 AE3 A26 AK34 AN11 AE5 AL1 AN13 D12 AR31 AE31 VSS VSS VDD A23 VSS D9 AL3 A25 AN15 AE33 D51 AL5 AN17 AE35 D58 AL7 VSS D3 VDD D18 AN19 D22 AF2 A17 AL9 D4 AN21 AF4 A28 AL11 D10 AN23 VDD D28 AF32 D46 AL13 AN25 D37 AF34 D49 AL15 VSS D16 AN27 VSS AA3 AA5 AA31 AA33 AC3 AC5 AD2 AD4 AD32 AD34 4 AG5 AJ5 AK12 AK22 AK26 AK32 POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 AP6 AR29 VDD D43 SMJ320C80 SMJ320C80 DIGITAL SIGNAL PROCESSOR SGUS025B SGUS025B ­ AUGUST 1998 ­ REVISED JUNE 2002 GF Pin Assignments ­ Alphabetical Listing PIN NAME PIN NUMBER NAME A0 L1 A1 G5 A2 A3 A4 PIN NUMBER NAME CAS/DQM1 B20 CAS/DQM2 C19 G3 CAS/DQM3 H4 CAS/DQM4 P2 A5 A6 A7 PIN NUMBER NAME NUMBER D24 AL21 DBEN C25 D25 AM22 DDIN B26 B16 D26 AP20 DSF A23 E17 D27 AK22 EINT1 A31 CAS/DQM5 A15 D28 AN23 EINT2 G31 T2 CAS/DQM6 B14 D29 AL25 EINT3 E29 K4 CAS/DQM7 A13 D30 AR21 EMU0 T34 L3 CBLNK0/VBLNK0 C31 D31 AM26 EMU1 J35 A8 N3 CBLNK1/VBLNK1 G33 D32 AL27 FAULT E3 A9 P4 CLKIN C17 D33 AM28 FCLK0 B28 D22 A10 U3 CLKOUT E25 D34 AP22 FCLK1 A11 W1 CSYNC0/HBLNK0 B32 D35 AN29 HACK A9 A12 Y2 CSYNC1/HBLNK1 H32 D36 AR23 HREQ E15 A13 T4 CT0 C11 D37 AN25 HSYNC0 E33 A14 AB2 CT1 A5 D38 AL29 HSYNC1 K34 A15 AE1 CT2 F18 D39 AP26 LINT4 E27 A16 AG1 D0 AR5 D40 AR27 NC B2 A17 AF2 D1 AN7 D41 AP28 NC U31 A18 W3 D2 AM8 D42 AJ33 NC AK18 A19 Y4 D3 AL7 D43 AR31 PS0 F14 A20 AH2 D4 AL9 D44 AH32 PS1 B8 A21 AB4 D5 AP8 D45 AN31 PS2 C13 A22 AC3 D6 AM10 D46 AF32 PS3 U5 A23 AL1 D7 AR9 D47 AP32 RAS A21 A24 AM2 D8 AP10 D48 AL33 READY E9 A25 AL3 D9 AN11 D49 AF34 REQ0 D16 A26 AE3 D10 AL11 D50 AM34 REQ1 B10 A27 AP4 D11 AR13 D51 AE33 RESET D14 A28 AF4 D12 AN13 D52 AC33 RETRY D2 A29 AN5 D13 AP14 D53 AL35 RL E19 A30 AH4 D14 AM14 D54 AH34 SCLK0 D28 A31 AJ3 D15 AR15 D55 AB32 SCLK1 A27 AS0 D8 D16 AL15 D56 Y34 STATUS0 H2 AS1 E1 D17 AP16 D57 AG35 STATUS1 J1 AS2 C7 D18 AN17 D58 AE35 STATUS2 E7 BS0 E11 D19 AM16 D59 W33 STATUS3 C5 STATUS4 K2 BS1 B4 D20 AL17 D60 AB34 CAREA0 C29 D21 AL19 D61 U33 CAREA1 D26 D22 AN19 D62 T32 CAS/DQM0 D20 D23 AM20 D63 W35 POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 5 SMJ320C80 SMJ320C80 DIGITAL SIGNAL PROCESSOR SGUS025B SGUS025B ­ AUGUST 1998 ­ REVISED JUNE 2002 GF Pin Assignments ­ Alphabetical Listing (Continued) PIN PIN PIN PIN NAME NUMBER NAME NUMBER NAME NUMBER NAME NUMBER STATUS5 E21 VDD VSS AR29 VSS VSS AA35 E35 VDD VDD R31 TCK VSS VSS A19 VSS VSS AC31 VSS VSS C3 VSS VSS AD32 VSS VSS C27 VSS VSS AE31 VSS VSS D12 VSS VSS AG33 VSS VSS D24 VSS VSS AJ31 VSS VSS E5 VSS VSS AK10 VSS VSS AK20 VSS VSS AK32 VSS VSS AL13 VSS VSS AL31 VSS VSS AM12 VSS VSS AM24 TDI H34 TDO P32 TMS N33 TRG/CAS B22 TRST L33 UTIME D10 VDD VDD A17 A7 VDD VDD A29 VDD VDD B12 VDD VDD B24 VDD VDD C15 VDD VDD B6 B18 B30 C21 D4 D32 VDD VDD VDD VDD F12 VDD VDD F24 VDD VDD F34 VDD VDD G35 VDD VDD J31 VDD VDD M34 VDD VDD N35 VDD 6 F2 F8 F20 F28 G1 J5 M2 VDD VDD VDD VDD R33 U1 U35 V2 V34 VDD VDD AA3 VDD VDD AA31 VDD VDD VDD VDD VDD VDD VDD VDD AA5 AA33 AC1 AC35 AD2 AD34 AG5 AG31 AJ1 AJ35 VDD VDD AK2 VDD VDD AK12 VDD VDD AK24 VDD VDD AK34 VDD VDD AM32 VDD VDD AN21 VDD VDD AP6 AK8 AK16 AK28 AM4 AN15 AN33 AP12 VDD VDD AP18 AP30 R3 VDD VDD R5 VDD N1 AP24 A11 A25 C9 D6 D18 D30 E13 VSS VSS E23 VSS VSS F4 E31 F10 VSS VSS F16 VSS VSS F26 VSS VSS J3 F22 F32 J33 VSS VSS L31 VSS VSS M32 VSS VSS N31 VSS VSS VSS VSS L5 M4 N5 R1 AC5 AD4 AE5 AG3 AJ5 AK4 AK14 AK26 AL5 AL23 AM6 AM18 AM30 VSS VSS AN27 AN9 VSS VSS AR17 AR11 AR25 R35 VSS VSYNC0 V4 VSYNC1 K32 V32 D34 W C23 W5 XPT0 P34 AR7 VSS VSS W31 XPT1 L35 AR19 VSS AA1 XPT2 Y32 POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 SMJ320C80 SMJ320C80 DIGITAL SIGNAL PROCESSOR SGUS025B SGUS025B ­ AUGUST 1998 ­ REVISED JUNE 2002 HFH Pin Assignments ­ Numerical Listing PIN PIN PIN NUMBER NAME NUMBER NAME NUMBER 1 STATUS3 41 CAS/DQM6 2 42 3 VSS STATUS2 VSS CAS/DQM5 4 STATUS1 44 5 45 6 VDD STATUS0 VDD CAS/DQM4 46 7 AS2 47 8 AS1 PIN NAME NUMBER NAME 81 LINT4 121 82 EINT3 122 VDD D59 83 EINT2 123 84 EINT1 124 85 CBLNK1/VBLNK1 125 CAS/DQM3 86 CBLNK0/VBLNK0 126 VDD D57 CT2 87 127 XPT2 48 CAS/DQM2 88 VSS VSS 128 VSS CAS/DQM1 89 CSYNC1/HBLNK1 129 VSS D56 90 130 43 9 AS0 49 10 FAULT 50 VSS D58 11 READY 51 91 12 RETRY 52 VDD CAS/DQM0 VDD VDD 92 CSYNC0/HBLNK0 132 D55 13 UTIME 53 RL 93 VSYNC1 133 14 BS1 54 RAS 94 VSYNC0 134 VSS D54 15 BS0 55 95 CT1 56 96 VSS VSS 135 16 VSS VSS 17 CT0 57 97 HSYNC1 137 18 PS2 58 VSS TRG/CAS 98 138 19 PS1 59 VDD VDD 139 D52 20 PS0 60 140 21 VDD RESET 61 101 141 VDD D51 62 VDD VDD VDD HSYNC0 102 TRST 142 D50 63 W 103 TCK 143 D49 24 VSS HREQ 64 STATUS5 104 TMS 144 25 HACK 65 105 TDI 145 VSS VSS 26 66 106 TDO 146 D48 27 VSS VSS VDD DSF EMU1 147 REQ1 68 VSS DBEN 107 28 108 XPT0 148 VDD VDD 29 REQ0 69 XPT1 149 VDD VDD 70 VDD DDIN 109 30 110 150 VDD D47 71 CLKOUT 111 VSS VSS 151 D46 VSS VDD VSS 72 CAREA1 112 EMU0 152 D45 73 VSS SCLK1 113 153 114 VDD D63 VSS VSS VSS CLKIN 75 VDD FCLK0 115 D62 155 D44 116 156 VSS CAS/DQM7 77 VSS SCLK0 117 VSS D61 VDD VDD 158 VDD VDD 79 119 VSS D60 159 VDD D43 120 VDD 160 D42 22 23 31 32 33 34 35 36 37 38 39 40 67 74 76 78 80 VDD FCLK1 VDD CAREA0 POST OFFICE BOX 1443 99 100 118 · HOUSTON, TEXAS 77251­1443 131 136 154 157 VDD VDD VDD D53 VSS VSS 7 SMJ320C80 SMJ320C80 DIGITAL SIGNAL PROCESSOR SGUS025B SGUS025B ­ AUGUST 1998 ­ REVISED JUNE 2002 HFH Pin Assignments ­ Numerical Listing (Continued) PIN NUMBER PIN NAME NUMBER NAME NUMBER 161 D41 162 163 VSS VSS 201 D20 202 203 VDD VDD 164 D40 204 D19 165 205 166 VDD D39 167 D38 207 168 D37 208 169 VSS D36 209 170 171 206 210 PIN NAME NUMBER NAME 241 D0 281 242 282 VDD VDD 243 VDD VDD 244 A31 284 VDD A15 VDD D18 245 285 PS3 246 VSS A30 286 A14 VSS D17 247 A29 287 248 288 VSS VSS 249 VSS VSS VSS VDD 289 A13 250 A28 290 VDD VDD 291 VSS VSS 292 A12 293 VDD A11 283 211 D16 251 212 213 VDD D15 252 173 VSS VDD D35 174 D34 214 D14 254 VDD A27 175 D33 215 D13 255 A26 295 176 VSS D32 216 VSS VSS 256 A25 296 217 257 297 218 D12 258 179 VDD VDD VSS VSS 219 220 VSS A24 299 D31 VDD VDD 259 180 181 D30 221 222 VDD VDD 301 D29 VDD D11 261 182 302 VDD A7 183 VSS VSS 223 D10 263 303 A6 224 D9 264 VDD A23 304 VSS D28 225 VSS D8 265 A22 305 VSS VSS 266 306 A5 227 307 228 VDD VDD 267 188 VDD VDD VDD A21 308 VSS A4 189 D27 229 D7 269 VSS VSS 190 D26 230 D6 270 A20 310 191 D25 231 D5 271 311 192 VSS D24 232 VSS VSS 272 VDD VDD 312 273 A19 313 VDD VDD 234 D4 274 235 275 196 D23 236 VDD D3 VSS A18 314 195 276 A17 316 197 D22 237 D2 277 A0 238 318 239 VSS D1 278 199 VSS D21 VSS VSS 317 198 319 200 VSS 240 VSS 280 VSS A16 VDD STATUS4 320 VSS 172 177 178 184 185 186 187 193 194 8 226 233 POST OFFICE BOX 1443 253 260 262 268 279 · HOUSTON, TEXAS 77251­1443 294 298 300 309 315 VSS A10 VDD A9 VSS A8 VDD VDD VDD A3 VDD A2 VSS A1 SMJ320C80 SMJ320C80 DIGITAL SIGNAL PROCESSOR SGUS025B SGUS025B ­ AUGUST 1998 ­ REVISED JUNE 2002 HFH Pin Assignments ­ Alphabetical Listing PIN PIN PIN PIN NAME NUMBER NAME NUMBER NAME NUMBER NAME NUMBER A0 317 CAS/DQM1 50 D30 181 DBEN 68 A1 316 CAS/DQM2 48 D31 180 DDIN 70 A10 296 CAS/DQM3 46 D32 177 DSF 66 A11 294 CAS/DQM4 45 D33 175 EINT1 84 A12 292 CAS/DQM5 43 D34 174 EINT2 83 A13 289 CAS/DQM6 41 D35 173 EINT3 82 A14 286 CAS/DQM7 38 D36 170 EMU0 112 A15 284 CBLNK0/VBLNK0 86 D37 168 EMU1 107 A16 280 CBLNK1/VBLNK1 85 D38 167 FAULT 10 A17 276 CLKIN 36 D39 166 FCLK0 76 A18 275 CLKOUT 71 D4 234 FCLK1 60 A19 273 CSYNC0/HBLNK0 92 D40 164 HACK 25 A2 314 CSYNC1/HBLNK1 89 D41 161 HREQ 24 A20 270 CT0 17 D42 160 HSYNC0 101 A21 267 CT1 16 D43 159 HSYNC1 97 A22 265 CT2 47 D44 155 LINT4 81 A23 264 D0 241 D45 152 PS0 20 A24 260 D1 239 D46 151 PS1 19 A25 256 D10 223 D47 150 PS2 18 A26 255 D11 222 D48 146 PS3 285 A27 254 D12 218 D49 143 RAS 54 A28 250 D13 215 D5 231 READY 11 A29 247 D14 214 D50 142 REQ0 29 A3 312 D15 213 D51 141 REQ1 28 A30 246 D16 211 D52 139 RESET 22 A31 244 D17 208 D53 136 RETRY 12 A4 308 D18 206 D54 134 RL 53 A5 306 D19 204 D55 132 SCLK0 78 A6 303 D2 237 D56 129 SCLK1 74 A7 302 D20 201 D57 126 STATUS0 6 A8 300 D21 199 D58 124 STATUS1 4 A9 298 D22 197 D59 122 STATUS2 3 AS0 9 D23 196 D6 230 STATUS3 1 AS1 8 D24 193 D60 119 STATUS4 319 AS2 7 D25 191 D61 117 STATUS5 64 BS0 15 D26 190 D62 115 TCK 103 TDI 105 BS1 14 D27 189 D63 114 CAREA0 80 D28 186 D7 229 CAREA1 72 D29 182 D8 226 CAS/DQM0 52 D3 236 D9 224 POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 9 SMJ320C80 SMJ320C80 DIGITAL SIGNAL PROCESSOR SGUS025B SGUS025B ­ AUGUST 1998 ­ REVISED JUNE 2002 HFH Pin Assignments ­ Alphabetical Listing (Continued) PIN PIN PIN PIN NAME NUMBER NAME NUMBER NAME NUMBER NAME NUMBER TDO 106 VSS VSS 110 VSS VSS 259 104 VDD VDD 243 TMS VDD VDD 252 VSS VSS 116 VSS VSS 268 VDD VDD 261 VSS VSS 123 VSS VSS 27 VDD VDD 263 VSS VSS 133 VDD VDD 271 VSS VSS 138 VDD VDD 281 VSS VSS 145 VDD VDD 283 VSS VSS 154 VDD VDD 293 VSS VSS 163 VDD VDD 30 VSS VSS 171 VSS VSS 183 VSS VSS 185 VSS VSS 198 VSS VSS 200 VSS VSS 209 VSS VSS 217 VSS VSS 23 TRG/CAS 58 TRST 102 UTIME 13 VDD VDD 100 VDD VDD 120 VDD VDD 125 VDD VDD 131 VDD VDD 140 VDD VDD 148 VDD VDD 156 VDD VDD 158 VDD VDD 172 VDD VDD 179 VDD VDD 188 VDD VDD 195 VDD VDD 203 VDD VDD 113 121 130 135 147 149 157 165 178 187 194 202 205 21 212 VDD VDD VDD VDD 251 253 262 266 272 282 288 297 301 309 310 311 313 VDD VDD 318 VDD VDD 40 VDD VDD 44 VDD VDD 51 VDD VDD 61 VDD VDD 65 VDD VDD 75 VDD VDD 90 39 33 5 59 62 118 128 137 144 153 162 169 176 184 192 2 207 216 225 232 26 269 274 VSS VSS 277 VSS VSS 279 VSS VSS 290 VSS VSS 295 VSS VSS 304 VSS VSS 307 VSS VSS 320 VSS VSS 35 VSS VSS 42 VSS VSS 55 VSS VSS 57 VSS VSS 73 VSS VSS 87 95 278 287 291 299 305 315 34 37 49 56 67 77 88 VSS VSS 233 238 VSS VSS VSS VSS 240 VSYNC0 94 245 VSYNC1 93 VSS VSS 248 W 63 249 XPT0 108 VDD VDD VDD VDD 221 VDD VDD 228 XPT1 109 99 VSS VSS 257 31 VDD VDD 98 VDD 210 XPT2 127 VDD 10 219 242 VSS 32 VSS 258 220 227 235 69 111 79 91 POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 96 SMJ320C80 SMJ320C80 DIGITAL SIGNAL PROCESSOR SGUS025B SGUS025B ­ AUGUST 1998 ­ REVISED JUNE 2002 Terminal Functions TERMINAL NAME DESCRIPTION TYPE LOCAL MEMORY INTERFACE A31­A0 O Address bus. A31­A0 output the 32-bit byte address of the external memory cycle. The address can be multiplexed for DRAM accesses. AS2­AS0 I Address-shift selection. AS2­AS0 determine how the column address appears on the address bus. Eight shift values are supported, including zero. BS1­BS0 I Bus size selection. BS1­BS0 indicate the bus size of the memory or other devices being accessed, allowing dynamic bus sizing for data buses less than 64 bits wide. CT2­CT0 I Cycle timing selection. CT2­CT0 signals determine the timing of the current memory access. D63­D0 I/O Data bus. D63­D0 transfer up to 64 bits of data per memory cycle into or out of the 'C80. DBEN O Data-buffer enable. DBEN drives the active-low output enables of bidirectional transceivers that can be used to buffer input and output data on D63­D0. DDIN O Data direction indicator. DDIN indicates the direction of the data that passes through the transceivers. When DDIN is low, the transfer is from external memory into the 'C80. FAULT I Fault. FAULT is driven low by external circuitry to inform the 'C80 that a fault has occurred on the current memory row access. PS3­PS0 I Page size indication. PS3­PS0 indicate the page size of the memory device(s) being accessed by the current cycle. The 'C80 uses this information to determine when to begin a new row access. READY I Ready. READY indicates that the external device is ready to complete the memory cycle. READY is driven low by external circuitry to insert wait states into a memory cycle. RL O Row latch. The high-to-low transition of RL can be used to latch the valid 32-bit byte address that is present on A31­A0. RETRY I Retry. RETRY is driven low by external circuitry to indicate that the addressed memory is busy. The 'C80 memory cycle is rescheduled. STATUS5­STATUS0 O Status code. At row time, STATUS5­STATUS0 indicate the type of cycle being performed. At column time, they identify the processor and type of request that initiated the cycle. UTIME I User-timing selection. UTIME causes the timing of RAS and CAS/DQM7­CAS/DQM0 to be modified so that custom memory timings can be generated. During reset, UTIME selects the endian mode in which the 'C80 operates. CAS/DQM7­ CAS/DQM0 O Column-address strobes. CAS/DQM7­CAS/DQM0 drive the CAS inputs of DRAMs and VRAMs, or the DQM input of synchronous dynamic random-access memories (SDRAMs). The eight strobes provide byte-write access to memory. DSF O Special function. DSF selects special VRAM functions such as block-write, load color register, split-register transfer, and synchronous graphics random-access memory (SGRAM) block write. RAS O Row-address strobe. RAS drives the RAS inputs of DRAMs, VRAMs, and SDRAMs. TRG/CAS O Transfer/output enable or column-address strobe. TRG/CAS is used as an output enable for DRAMs and VRAMs, and also as a transfer enable for VRAMs. TRG/CAS also drives the CAS inputs of SDRAMs. W O Write enable. W is driven low before CAS during write cycles. W controls the direction of the transfer during VRAM transfer cycles. DRAM, VRAM, AND SDRAM CONTROL I = input, O = output, Z = high-impedance This pin has an internal pullup and can be left unconnected during normal operation. § This pin has an internal pulldown and can be left unconnected during normal operation. ¶ For proper operation, all VDD and VSS pins must be connected externally. POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 11 SMJ320C80 SMJ320C80 DIGITAL SIGNAL PROCESSOR SGUS025B SGUS025B ­ AUGUST 1998 ­ REVISED JUNE 2002 Terminal Functions (Continued) TERMINAL NAME DESCRIPTION TYPE HOST INTERFACE O Host acknowledge. The 'C80 drives HACK output low following an active HREQ to indicate that it has driven the local memory bus signals to the high-impedance state and is relinquishing the bus. HACK is driven high asynchronously following HREQ being detected inactive, and then the 'C80 resumes driving the bus. HREQ I Host request. An external device drives HREQ low to request ownership of the local memory bus. When HREQ is high, the 'C80 owns and drives the bus. HREQ is synchronized internally to the 'C80's internal clock. Also, HREQ is used at reset to determine the power-up state of the MP. If HREQ is low at the rising edge of RESET, the MP comes up running. If HREQ is high, the MP remains halted until the first interrupt occurrence on EINT3. REQ1, REQ0 O Internal cycle request. REQ1 and REQ0 provide a two-bit code indicating the highest-priority memory cycle request that is being received by the TC. External logic can monitor REQ1 and REQ0 to determine if it is necessary to relinquish the local memory bus to the 'C80. CLKIN I Input clock. CLKIN generates the internal 'C80 clocks to which all processor functions (except the frame timers) are synchronous. CLKOUT O Local output clock. CLKOUT provides a way to synchronize external circuitry to internal timings. All 'C80 output signals (except the VC signals) are synchronous to this clock. EINT1, EINT2, EINT3 I Edge-triggered interrupts. EINT1, EINT2 and EINT3 allow external devices to interrupt the master processor (MP) on one of three interrupt levels (EINT1 is the highest priority). The interrupts are rising-edge triggered. EINT3 also serves as an unhalt signal. If the MP is powered-up halted, the first rising edge on EINT3 causes the MP to unhalt and fetch its reset vector (the EINT3 interrupt-pending bit is not set in this case). LINT4 I Level-triggered interrupt. LINT4 provides an active-low level-triggered interrupt to the MP. Its priority falls below that of the edge-triggered interrupts. Any interrupt request should remain low until it is recognized by the 'C80. RESET I Reset. RESET is driven low to reset the 'C80 (all processors). During reset, all internal registers are set to their initial state and all outputs are driven to their inactive or high-impedance levels. During the rising edge of RESET, the MP reset mode and the 'C80's operating endian mode are determined by the levels of HREQ and UTIME pins, respectively. XPT2­XPT0 I External packet transfer. XPT2­XPT0 are used by external devices to request a high-priority XPT by the TC. I/O Emulation pins. EMU0 and EMU1 are used to support emulation host interrupts, special functions targeted at a single processor, and multiprocessor halt-event communications. TCK I Test clock. TCK provides the clock for the 'C80 IEEE-1149 IEEE-1149.1 logic, allowing it to be compatible with other IEEE-1149 IEEE-1149.1 devices, controllers, and test equipment designed for different clock rates. TDI I Test data input. TDI provides input data for all IEEE-1149 IEEE-1149.1 instructions and data scans of the 'C80. TDO TMS O Test data output. TDO provides output data for all IEEE-1149 IEEE-1149.1 instructions and data scans of the 'C80. I Test-mode select. TMS controls the IEEE-1149 IEEE-1149.1 state machine. TRST§ I Test reset. TRST resets the 'C80 IEEE-1149 IEEE-1149.1 module. When low, all boundary-scan logic is disabled, allowing normal 'C80 operation. HACK SYSTEM CONTROL EMULATION CONTROL EMU0, EMU1 I = input, O = output, Z = high-impedance This pin has an internal pullup and can be left unconnected during normal operation. § This pin has an internal pulldown and can be left unconnected during normal operation. ¶ For proper operation, all VDD and VSS pins must be connected externally. 12 POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 SMJ320C80 SMJ320C80 DIGITAL SIGNAL PROCESSOR SGUS025B SGUS025B ­ AUGUST 1998 ­ REVISED JUNE 2002 Terminal Functions (Continued) TERMINAL NAME DESCRIPTION TYPE VIDEO INTERFACE CAREA0, CAREA1 O Composite area. CAREA0 and CAREA1 define a special area such as an overscan boundary. This area represents the logical OR of the internal horizontal and vertical area signals. Composite blanking/vertical blanking. Each of CBLNK0/VBLNK0 and CBLNK1/VBLNK1 provides one of two blanking functions, depending on the configuration of the CSYNC/HBLNK pin: CBLNK0/VBLNK0, CBLNK1/VBLNK1 O Composite blanking disables pixel display/capture during both horizontal and vertical retrace periods and is enabled when CSYNC is selected for composite-sync video systems. Vertical blanking disables pixel display/capture during vertical retrace periods and is enabled when HBLNK is selected for separate-sync video systems. Following reset, CBLNK0/VBLNK0 and CBLNK1 / VBLNK1 are configured as CBLNK0 and CBLNK1, respectively. Composite sync/horizontal blanking. CSYNC0/HBLNK0 and CSYNC1/HBLNK1 can be programmed for one of two functions: CSYNC0/HBLNK0, CSYNC1/HBLNK1 I/O/Z Composite sync is for use on composite-sync video systems and can be programmed as an input, output, or high-impedance signal. As an input, the 'C80 extracts horizontal and vertical sync information from externally generated active-low sync pulses. As an output, the active-low composite-sync pulses are generated from either external HSYNC and VSYNC signals or the 'C80's internal video timers. In the high-impedance state, the pin is neither driven nor allowed to drive circuitry. Horizontal blank disables pixel display/capture during horizontal retrace periods in separate-sync video systems and can be used as an output only. Immediately following reset, CSYNC0/HBLNK0 and high-impedance CSYNC0 and CSYNC1, respectively. FCLK0, FCLK1 HSYNC0, HSYNC1 SCLK0, SCLK1 VSYNC0, VSYNC1 CSYNC1/HBLNK1 are configured as I Frame clock. FCLK0 and FCLK1 are derived from the external video system's dotclock and are used to drive the 'C80 video logic for frame timer 0 and frame timer 1. I/O/Z Horizontal sync. HSYNC0 and HSYNC1 control the video system. They can be programmed as input, output, or high impedance signals. As an input, HSYNC synchronizes the video timer to externally generated horizontal sync pulses. As an output, HSYNC is an active-low horizontal sync pulse generated by the 'C80 on-chip frame timer. In the high-impedance state, the pin is not driven, and no internal synchronization is allowed to occur. Immediately following reset, HSYNC0 and HSYNC1 are in the high-impedance state. I Serial data clock. SCLK0 and SCLK1 are used by the 'C80 shift register transfer (SRT) controller to track the VRAM tap point when using midline reload. SCLK0 and SCLK1 should be the same signals that clock the serial register on the VRAMs controlled by frame timer 0 and frame timer 1, respectively. I/O/Z Vertical sync. VSYNC0 and VSYNC1 control the video system. They can be programmed as inputs, outputs, or high-impedance signals. As inputs, VSYNCx synchronize the frame timer to externally generated vertical-sync pulses. As outputs, VSYNCx are active-low vertical-sync pulses generated by the 'C80 on-chip frame timer. In the high-impedance state, the pin is not driven and no internal synchronization is allowed to occur. Immediately following reset, VSYNCx is in the high-impedance state. POWER VSS¶ VDD¶ I Ground. Electrical ground inputs I Power. Nominal 3.3-V power supply inputs MISCELLANEOUS NC No connect serves as an alignment key or is for factory use and must be left unconnected. I = input, O = output, Z = high-impedance This pin has an internal pullup and can be left unconnected during normal operation. § This pin has an internal pulldown and can be left unconnected during normal operation. ¶ For proper operation, all VDD and VSS pins must be connected externally. POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 13 SMJ320C80 SMJ320C80 DIGITAL SIGNAL PROCESSOR SGUS025B SGUS025B ­ AUGUST 1998 ­ REVISED JUNE 2002 architecture Figure 1 shows the major components of the 'C80: the master processor (MP), the parallel digital signal processors (PPs), the transfer controller (TC), and the IEEE-1149 IEEE-1149.1 emulation interface. Shared access to on-chip RAM is achieved through the crossbar. Crossbar connections are represented by . Each PP can perform three accesses per cycle through its local (L), global (G), and instruction (I) ports. The MP can access two RAMs per cycle through its crossbar/data (C/D) and instruction (I) ports, and the TC can access one RAM through its crossbar interface. Up to nine simultaneous accesses are supported in each cycle. Addresses can be changed every cycle, allowing the crossbar matrix to be changed on a cycle-by-cycle basis. Contention between processors for the same RAM in the same cycle is resolved by a round-robin priority scheme. In addition to the crossbar, a 32-bit data path exists between the MP and the TC and VC. This allows the MP to access TC control registers that are memory-mapped into the MP memory space. The 'C80 has a 4G-byte address space as shown in Figure 2. The lower 32M bytes are used to address internal RAM and memory-mapped registers. 14 POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 SMJ320C80 SMJ320C80 DIGITAL SIGNAL PROCESSOR SGUS025B SGUS025B ­ AUGUST 1998 ­ REVISED JUNE 2002 architecture (continued) ADSP3 ADSP2 ADSP1 ADSP0 MP VC OCR L G I 32 64 L G I 32 64 32 L G I 32 64 32 L G I 32 C/D I 64 32 32 32 IEEE1149 IEEE1149.1 (JTAG) 32 64 64 L G I C/D Instruction Cache Data Cache Instruction Cache Data Cache Parameter RAM Data RAM0 Instruction Cache Data RAM1 Data RAM2 Parameter RAM Instruction Cache Data RAM0 Data RAM1 Data RAM2 Parameter RAM Data RAM0 Instruction Cache Data RAM1 Data RAM2 Parameter RAM Data RAM0 Instruction Cache Data RAM1 Data RAM2 Parameter RAM 64 TC Local port Global port Instruction port Crossbar/data port Figure 1. Block Diagram Showing Data Paths POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 15 SMJ320C80 SMJ320C80 DIGITAL SIGNAL PROCESSOR SGUS025B SGUS025B ­ AUGUST 1998 ­ REVISED JUNE 2002 architecture (continued) 0xFFFFFFFF ADSP3 Parameter RAM (2K bytes) Reserved (2K bytes) ADSP2 Parameter RAM (2K bytes) External Memory (4064M 4064M bytes) Reserved (2K bytes) ADSP1 Parameter RAM (2K bytes) Reserved (8063K 8063K bytes) Memory-Mapped VC Registers (512 bytes) Memory-Mapped TC Registers (512 bytes) Reserved (28K bytes) MP Instruction Cache (4K bytes) Reserved (28K bytes) MP Data Cache (4K bytes) Reserved (32K bytes) ADSP3 Instruction Cache (2K bytes) Reserved (6K bytes) ADSP2 Instruction Cache (2K bytes) Reserved (6K bytes) ADSP1 Instruction Cache (2K bytes) Reserved (6K bytes) ADSP0 Instruction Cache (2K bytes) Reserved (2K bytes) 0x02000000 0x01FFFFFF 0x01820400 0x018203FF ADSP0 Parameter RAM (2K bytes) ADSP3 Data RAM2 (2K bytes) 0x01820000 0x0181FFFF Reserved (2K bytes) 0x01819000 0x01818FFF ADSP2 Data RAM2 (2K bytes) 0x01818000 0x01817FFF Reserved (2K bytes) 0x01811000 0x01810FFF ADSP1 Data RAM2 (2K bytes) 0x01810000 0x0180FFFF Reserved (2K bytes) 0x01808000 0x01807FFF ADSP0 Data RAM2 (2K bytes) 0x01807800 0x018077FF 0x01805800 0x018057FF ADSP3 Data RAM1 (2K bytes) 0x01804000 0x01803FFF ADSP3 Data RAM0 (2K bytes) 0x01803800 0x018037FF ADSP2 Data RAM1 (2K bytes) 0x01802000 0x01801FFF ADSP2 Data RAM0 (2K bytes) 0x01801800 0x018017FF ADSP1 Data RAM1 (2K bytes) ADSP1 Data RAM0 (2K bytes) 0x01010800 0x010107FF ADSP0 Data RAM1 (2K bytes) 0x01010000 0x0100FFFF ADSP0 Data RAM0 (2K bytes) 0x01003800 Figure 2. Memory Map POST OFFICE BOX 1443 0x01002800 0x010027FF 0x01002000 0x01001FFF 0x01001800 0x010017FF 0x01001000 0x01000FFF 0x01000800 0x010007FF 0x01000000 0x00FFFFFF 0x0000B800 0x0000B7FF 0x0000B000 0x0000AFFF 0x0000A800 0x0000A7FF 0x0000A000 0x00009FFF 0x00009800 0x000097FF 0x00009000 0x00008FFF 0x00008800 0x000087FF 0x00008000 0x00007FFF Reserved (16K bytes) 0x01806000 0x01805FFF Registers (50K bytes) 16 0x01003000 0x01002FFF Reserved (16338K 16338K bytes) 0x01820200 0x018201FF Registers (8132K 8132K bytes) MP Parameter RAM (2K bytes) 0x010037FF · HOUSTON, TEXAS 77251­1443 0x00004000 0x00003FFF 0x00003800 0x000037FF 0x00003000 0x00002FFF 0x00002800 0x000027FF 0x00002000 0x00001FFF 0x00001800 0x000017FF 0x00001000 0x00000FFF 0x00000800 0x000007FF 0x00000000 SMJ320C80 SMJ320C80 DIGITAL SIGNAL PROCESSOR SGUS025B SGUS025B ­ AUGUST 1998 ­ REVISED JUNE 2002 master processor (MP) architecture The master processor (MP) is a 32-bit RISC processor with an integral IEEE-754 IEEE-754 floating-point unit. The MP is designed for effective execution of C code and is capable of performing at well over 130000 dhrystones/s. Major tasks which the MP typically performs are: D Task control and user interface D Information processing and analysis D IEEE-754 IEEE-754 floating point (including graphics transforms) MP functional block diagram Figure 3 shows a block diagram of the master processor. Key features of the MP include: D 32-bit RISC processor ­ Load/store architecture ­ Three operand arithmetic and logical instructions D 4K-byte instruction cache and 4K-byte data cache ­ ­ Least-recently-used (LRU) information replacement ­ D D D D D D D D Four-way set associative Data writeback 4K-byte noncached parameter RAM Thirty-one 32-bit general-purpose registers Register and accumulator scoreboard 15-bit or 32-bit immediate constants 32-bit byte addressing Scalable timer Leftmost-one and rightmost-one logic IEEE-754 IEEE-754 floating-point hardware ­ Four double-precision floating-point vector accumulators ­ Vector floating-point instructions Floating-point operation and parallel load or store Multiply and accumulate D High performance ­ 50 million instructions per second (MIPS) ­ 100 million floating-point operations per second (MFLOPS) ­ Over 130000 dhrystones/s POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 17 SMJ320C80 SMJ320C80 DIGITAL SIGNAL PROCESSOR SGUS025B SGUS025B ­ AUGUST 1998 ­ REVISED JUNE 2002 MP functional block diagram (continued) Register File (Thirty-One 32-Bit Registers) Scoreboard Barrel Rotator Mask Generator Double-Precision Floating-Point Multiplier (Single-Precision Core) Zero Comparator Integer Arithmetic and Logic Unit (ALU) Leftmost/Rightmost One Double-Precision Floating-Point Accumulators Timer Control Registers Double-Precision Floating-Point Adder Instruction Register Program Counters (PCs) PC Incrementer Emulation Logic Endian Multiplexers Instruction Cache Controller Data-Cache Controller Crossbar Interface Figure 3. MP Block Diagram MP general-purpose registers The MP contains 31 32-bit general-purpose registers, R1­R31. Register R0 always reads as zero and writes to it are discarded. Double-precision values are always stored in an even-odd register pair with the higher-numbered register always holding the sign bit and exponent. The R0/R1 pair is not available for this use. A scoreboard keeps track of which registers are awaiting loads or the result of a previous instruction and stalls the instruction pipeline until the register contains valid data. As a recommended software convention, R1 is typically used as a stack pointer and R31 as a return-address link register. Figure 4 shows the MP general-purpose registers. 18 POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 SMJ320C80 SMJ320C80 DIGITAL SIGNAL PROCESSOR SGUS025B SGUS025B ­ AUGUST 1998 ­ REVISED JUNE 2002 MP general-purpose registers (continued) Zero/Discard Not Available R1 R2 R2, R2 R3 R3 R4 R4 R5 R4, R5 · · · · · · R30 R30, R30 R31 R31 32-Bit Registers 64-Bit Register Pairs Figure 4. MP General-Purpose Registers The 32-bit registers can contain signed-integer, unsigned-integer, or single-precision floating-point values. Signed and unsigned bytes and halfwords are sign-extended or zero-filled. Doublewords can be stored in a 64-bit even/odd register pair. Double-precision floating-point values are referenced using the even register number or the register pair. Figure 5 through Figure 7 show the register data formats. 31 Si l P i i Single-Precision Floating Point 22 0 S E E E E E E E E M M M M M M M M M M M M M M M M M M M M M M M MS LS 31 Si d 32 bit Signed 32-bit Integer S 0 I I I I I I I I I I I I I I I I I I I I MS I I I I I I I I I 0 U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U LS MS S E M I U MS LS I LS 31 U i d 32 Bit Unsigned 32-Bit Integer I Sign bit Exponent Value Signed integer value Unsigned integer value Most significant Least signficant Figure 5. MP Register 32-Bit Data Formats POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 19 SMJ320C80 SMJ320C80 DIGITAL SIGNAL PROCESSOR SGUS025B SGUS025B ­ AUGUST 1998 ­ REVISED JUNE 2002 MP general-purpose registers (continued) 31 Signed Byte 7 S S S S S S S S S S S S S S S S S S S S S S S S S 0 I I I I I I MS 31 Unsigned Byte 0 LS 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 U U U U U U U U MS 31 Signed Halfword 0 I I I I I I MS 31 U i d Unsigned Halfword 0 15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I I I I I I I I I LS 0 U U U U U U U U U U U U U U U U MS S I U MS LS LS 15 S S S S S S S S S S S S S S S S S I LS Sign bit(s) Signed byte/halfword value Unsigned byte/halfword value Most significant Least signficant Figure 6. MP Register 8-Bit and 16-Bit Data Formats 31 Odd Register 0 Most Significant 32-Bit Word MS 31 Even Register 0 Least Significant 32-Bit Word LS 31 Odd Register 19 0 S E E E E E E E E E E E M M M M M M M M M M M M M M M M M M M M MS 31 Even Register 0 M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M LS S E I U MS LS Sign bit(s) Exponent Signed byte/halfword value Unsigned byte/halfword value Most significant Least signficant Figure 7. MP Register 64-Bit Data Formats 20 POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 SMJ320C80 SMJ320C80 DIGITAL SIGNAL PROCESSOR SGUS025B SGUS025B ­ AUGUST 1998 ­ REVISED JUNE 2002 MP double-precision floating-point accumulators There are four double-precision floating-point registers (see Figure 8) to accumulate intermediate floating-point results. 63 0 a0 Accumulator 0 a1 Accumulator 1 a2 Accumulator 2 a3 Accumulator 3 MSB S E M MS LS LSB Sign bit Exponent Value Most significant Least signficant Figure 8. Double-Precision Floating-Point Accumulators MP control registers In addition to the general-purpose registers, there are a number of control registers that are used to represent the state of the processor. Table 1 shows the control register numbers of the accessible registers. Table 1. Control Register Numbers NUMBER NAME DESCRIPTION NUMBER NAME 0x0000 EPC Exception Program Counter 0x0015­0x001F - 0x0001 EIP Exception Instruction Pointer 0x0020 SYSSTK System Stack Pointer 0x0002 CONFIG Configuration 0x0021 SYSTMP System Temporary Register 0x0003 - 0x0022­0x002F - 0x0004 INTPEN Interrupt Pending Register 0x0030 MPC Emulator Exception Program Counter 0x0005 - Reserved 0x0031 MIP Emulator Exception Instruction Pointer 0x0006 IE Interrupt Enable Register 0x0032 - 0x0007 - Reserved 0x0033 ECOMCNTL 0x0008 FPST Floating-Point Status 0x0034 ANASTAT 0x0009 - 0x000A PPERROR 0x000B - 0x000C - Reserved Reserved DESCRIPTION Reserved Reserved Reserved Emulator Communication Control Emulation Analysis Status Register 0x0035­0x0038 - 0x0039 BRK1 Emulation Breakpoint 1 Register Reserved 0x003A BRK2 Emulation Breakpoint 2 Register Reserved 0x003B­0x01FF - 0x0200 ­ 0x020F iCACHET Instruction Cache Tags 0 to 15 PP Error Register Reserved Reserved 0x000D PKTREQ Packet-Transfer Request Register 0x000E TCOUNT Current Counter Value 0x0300 iCACHEL Instruction Cache LRU Register 0x000F TSCALE Counter Reload Value 0x0010 FLTOP 0x0400­0x040F dCACHET Data Cache Tags 0 to 15 Faulting Operation 0x0500 dCACHEL Data Cache LRU Register 0x0011 FLTADR Faulting Address 0x4000 IN0P Vector Load Pointer 0 0x0012 FLTTAG Faulting Tag 0x4001 IN1P Vector Load Pointer 1 0x0013 FLTDTL Faulting Data (low) 0x4002 OUTP Vector Store Pointer 0x0014 FLTDTH Faulting Data (high) POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 21 SMJ320C80 SMJ320C80 DIGITAL SIGNAL PROCESSOR SGUS025B SGUS025B ­ AUGUST 1998 ­ REVISED JUNE 2002 MP pipeline registers The MP uses a three-stage fetch, execute, access (FEA) pipeline. The primary pipeline registers are manipulated implicitly by branch and trap instructions and are not accessible by the user. The exception and emulation pipeline registers are user-accessible as control registers. All pipeline registers are 32 bits. Program Execution Mode Normal Exception Emulation PC EPC MPC Instruction Pointer IP EIP MIP Instruction Register IR Program Counter · · · · Instruction register (IR) contains the instruction being executed. Instruction pointer (IP) points to the instruction being executed. Program counter (PC) points to the instruction being fetched. · Exception/emulator instruction pointer (EIP/MIP) points to the instruction that would have been executed had the exception / emulation trap not occurred. Exception/emulator program counter (EPC/MPC) points to the instruction to be fetched on returning from the exception/emulation trap. Figure 9. MP FEA Pipeline Registers configuration (CONFIG) register (0x0002) The CONFIG register controls or reflects the state of certain options as shown in Figure 10. 3 1 3 0 2 9 2 8 2 7 E R T H X E R T H X Type Release 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 Reserved 1 6 1 5 1 4 1 3 1 2 Type 1 1 1 0 Reserved Endian mode; 0 = big-endian, 1 = little-endian, read only PPData RAM round robin; 0 = fixed, 1 = variable, read/write TC packet transfer (PT) round robin; 0 = variable, 1 = fixed, read/write High priority MP events; 0 = disabled, 1 = enabled, read/write Externally initiated packet transfers; 0 = disabled, 1 = enabled, read/write Number of PPs in device, read only SMJ320C80 SMJ320C80 version number Figure 10. CONFIG Register 22 POST OFFICE BOX 1443 9 · HOUSTON, TEXAS 77251­1443 8 7 6 5 Release 4 3 2 1 Reserved 0 SMJ320C80 SMJ320C80 DIGITAL SIGNAL PROCESSOR SGUS025B SGUS025B ­ AUGUST 1998 ­ REVISED JUNE 2002 interrupt-enable (IE) register (0x0006) The IE register contains enable bits for each of the interrupts/traps as shown in Figure 11. The global-interrupt-enable (ie) bit and the appropriate individual interrupt-enable bit must be set in order for an interrupt to occur. 3 1 3 0 2 9 2 8 2 7 2 6 2 5 p e x 4 x 3 b p p b p c m i pe x4 x3 bp pb pc mi p3 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 p 3 p 2 p 1 p 0 i o m f PP error External interrupt 4 (LINT4) External interrupt 3 (EINT3) Bad packet transfer Packet transfer busy Packet transfer complete MP message interrupt PP3 message interrupt p2 p1 p0 io mf x2 x1 ti 1 3 1 2 1 1 1 0 9 8 7 6 5 x 2 x 1 ti f 1 f 0 f x f u f o f1 f0 fx fu fo fz fi ie Frame-timer 1 interrupt Frame-timer 0 interrupt Floating-point inexact Floating-point underflow Floating-point overflow Floating-point divide-by-zero Floating-point invalid Global-interrupt enable PP2 message interrupt PP1 message interrupt PP0 message interrupt Integer overflow Memory fault External interrupt 2 (EINT2) External interrupt 1 (EINT1) MP timer interrupt 4 3 2 fz 1 fi 0 ie Figure 11. IE Register interrupt-pending (INTPEN) register (0x0004) The bits in INTPEN register show the current state of each interrupt/trap. Pending interrupts do not occur unless the ie bit and corresponding interrupt-enable bit are set. Software must write a 1 to the appropriate INTPEN bit to clear an interrupt. Figure 12 shows the INTPEN register locations. 3 1 3 0 2 9 2 8 2 7 2 6 2 5 p e x 4 x 3 b p p b p c m i pe x4 x3 bp pb pc mi p3 2 4 2 3 PP error External interrupt 4 (LINT4) External interrupt 3 (EINT3) Bad packet transfer Packet transfer busy Packet transfer complete MP message interrupt PP3 message interrupt 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 p 3 p 2 p 1 p 0 i o m f p2 p1 p0 io mf x2 x1 ti 1 3 1 2 1 1 1 0 9 8 7 6 5 x 2 x 1 ti f 1 f 0 f x f u f o f1 f0 fx fu fo fz fi ie Frame-timer 1 interrupt Frame-timer 0 interrupt Floating-point inexact Floating-point underflow Floating-point overflow Floating-point divide-by-zero Floating-point invalid Global-interrupt enable PP2 message interrupt PP1 message interrupt PP0 message interrupt Integer overflow Memory fault External interrupt 2 (EINT2) External interrupt 1 (EINT1) MP timer interrupt 4 3 2 fz 1 0 fi Figure 12. INTPEN Register POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 23 SMJ320C80 SMJ320C80 DIGITAL SIGNAL PROCESSOR SGUS025B SGUS025B ­ AUGUST 1998 ­ REVISED JUNE 2002 floating-point status (FPST) register (0x0008) FPST contains status and control information for the floating-point unit (FPU) as shown in Figure 13. Bits 17­21 are read/write FPU control bits. Bits 22­26 are read/write accumulated status bits. All other bits show the status of the last FPU instruction to complete and are read only. 3 1 3 0 2 9 2 8 2 7 dest ai az ao au ax sm fs vm drm opcode e1 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 ai dest 2 6 1 7 a z a o a u a x s m f s v m 1 6 drm 1 5 1 4 1 3 1 2 e 1 opcode 1 0 e 0 9 pd 8 7 6 rm mo i z o u x 5 4 3 2 1 0 mo rm The ninth MSB of exponent Destination precision 00 ­ single float 01 ­ double float Rounding mode 00 ­ nearest 01 ­ zero Int multiply overflow Invalid Divide-by-zero Overflow Underflow Inexact e0 pd Destination register value Accumulated value invalid Accumulated divide-by-zero Accumulated overflow Accumulated underflow Accumulated inexact Sequential mode select Floating-point stall Vector fast mode Rounding mode 00 ­ nearest 10 ­ positive 01 ­ zero 11 ­ negative Last opcode The tenth MSB of exponent 1 1 i z o u x 10 ­ signed int 11 ­ unsigned int 10 ­ positive 11 ­ negative Figure 13. FPST Register PP error (PPERROR) register (0x000A) The bits in the PPERROR register reflect parallel processor errors (see Figure 14). The MP can use these when a PP error interrupt occurs to determine the cause of the error. 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 PP# h I f 0 1 1 8 1 7 1 6 h Reserved 1 9 h h h 3 2 1 0 1 5 1 4 1 3 1 2 1 1 i i i i PP# 3 2 1 0 Reserved PPhalted PP illegal instruction PP fault type icache Direct external access (DEA) Figure 14. PPERROR Register 24 POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 1 0 9 8 7 6 5 4 3 f f f f PP# 3 2 1 0 Reserved 2 1 0 SMJ320C80 SMJ320C80 DIGITAL SIGNAL PROCESSOR SGUS025B SGUS025B ­ AUGUST 1998 ­ REVISED JUNE 2002 packet-transfer request (PKTREQ) register (0x000D) PKTREQ controls the submission and priority of packet-transfer requests as shown in Figure 15. It also indicates that a packet transfer is currently active. 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 I F S Q P 2 1 0 I Reserved 3 F S Q P Immediate (urgent) priority selected High (foreground) priority selected Suspend packet transfer Packet transfer queued; read only Submit packet-transfer request Figure 15. PKTREQ Register memory-fault registers The five read-only memory-fault registers contain information about memory address exceptions, as shown in Figure 16. FLTOP (0x0010) FLTTAG (0x0011) 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 Dest 3 1 3 0 2 9 2 3 2 2 2 1 2 0 1 9 1 8 1 7 Reserved 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 1 6 1 5 1 4 2 0 1 9 1 8 1 7 SZ 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 i d x r 1 2 1 1 1 0 9 8 7 6 5 4 3 2 P K 1 3 D P D P D P D 22-Bit Cache Tag Address 8 7 6 5 4 3 2 Reserved 3 2 1 0 Block 1 1 0 0 Sub-Block 31 0 FLTADR (0x0012) Faulting Address Accessed by the Instruction FLTDTH (0x0013) Faulting Write Most-Significant-Data Word FLTDTL (0x0014) Faulting Write Least-Significant-Data Word Dest K SZ Destination Register Number Kind of Operation: 00 ­ load 01 ­ unsigned load 10 ­ store 11 ­ cache flush/clean Size of Data: 00 ­ 8-bit 01 ­ 16-bit 10 ­ 32-bit 11 ­ 64-bit i d x r Block P D MP icache fault MP dcache fault DEA Fault Modified return sequence Faulting block number Sub-block is present. Dirty bit set Figure 16. Memory-Fault Registers POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 25 SMJ320C80 SMJ320C80 DIGITAL SIGNAL PROCESSOR SGUS025B SGUS025B ­ AUGUST 1998 ­ REVISED JUNE 2002 MP cache registers The ILRU and DLRU registers track least-recently-used (LRU) information for the sixteen instruction-cache and sixteen data-cache blocks. The ITAGxx registers contain block addresses and the present flags for each sub-block. DTAGxx registers are identical to ITAGxx registers but include dirty bits for each sub-block. Figure 17 shows the cache registers. ILRU (0x0300) DLRU (0x0500) 3 1 3 0 MRU 2 9 2 8 NMRU 2 7 2 6 NLRU 2 5 2 4 LRU 2 3 2 2 MRU 2 1 2 0 NMRU Set 3 1 9 1 8 NLRU 1 7 1 6 LRU 1 5 1 4 MRU 1 3 1 2 NMRU Set 2 1 1 1 0 NLRU 9 8 LRU 7 6 MRU 5 4 NMRU Set 1 3 2 NLRU 1 0 LRU Set 0 ITAG0­ITAG15 ITAG15 (0x0200­0x020F) 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 22-Bit Cache Tag Address 9 8 P 7 6 P 3 5 4 P 2 3 2 1 0 2 1 0 P 1 0 Sub-Block DTAG0­DTAG15 DTAG15 (0x0400­0x040F) 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 22-Bit Cache Tag Address 1 0 9 8 D P 3 7 6 P D 2 5 4 P 3 D P 1 Sub-Block MRU NMRU NLRU Most-recently-used Next most-recently-used Next least-recently-used LRU P D Least-recently-used Sub-block present Sub-block dirty mru, nmru, nlru, and lru have the value 0, 1, 2, or 3 representing the block number and are mutually exclusive for each set. Figure 17. Cache Registers 26 POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 D 0 SMJ320C80 SMJ320C80 DIGITAL SIGNAL PROCESSOR SGUS025B SGUS025B ­ AUGUST 1998 ­ REVISED JUNE 2002 MP cache architecture The MP contains two four-way set-associative, 4K caches for instructions and data. Each cache is divided into four sets with four blocks in each set. Each block represents 256 bytes of contiguous instructions or data and is aligned to a 256-byte address boundary. Each block is partitioned into four sub-blocks that each contain sixteen 32-bit words and are aligned to 64-byte boundaries within the block. Cache misses cause one sub-block to be loaded into cache. Figure 18 shows the cache architecture for one of the four sets in each cache. Figure 19 shows how addresses map into the cache using the cache tags and address bits. Block 0 Block 1 LRU in SET 0 Tag Reg 0 (Block 0) Tag Reg 1 (Block 1) Sub-Blocks NLRU in SET 0 NMRU in SET 0 Set 0 Block 2 Block 3 MRU in SET 0 Tag Reg 2 (Block 2) Tag Reg 3 (Block 3) LRU Stack for SET 0 LRU NLRU NMRU MRU Least-recently-used Next least-recently-used Next most-recently-used Most-recently-used Figure 18. MP Cache Architecture (x4 Sets) 32-Bit Logical Address 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 2 1 0 T T T T T T T T T T T T T T T T T T T T T T S S s s W W W W B B 4 3 On-Chip MP 4K Cache RAMS Bank 0 Bank 1 Set 0 Set 2 Set 1 Set 3 11 10 9 8 7 6 5 4 3 2 1 0 S S A A s s W W W W B B Address in On-Chip Cache Bank T ­ Tag Address Bits s ­ Sub-Block (within block) Select (0­3) B ­ Byte (within word) Select (0­3) S ­ Set Select Bits (0­3) W ­ Word (within sub-block) Select (0­15) A ­ Block Select (which tag matched) (0­3) Figure 19. MP Cache Addressing POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 27 SMJ320C80 SMJ320C80 DIGITAL SIGNAL PROCESSOR SGUS025B SGUS025B ­ AUGUST 1998 ­ REVISED JUNE 2002 MP parameter RAM The parameter RAM is a noncachable, 2K-byte, on-chip RAM that contains MP interrupt vectors, MP-requested TC task buffers, and a general-purpose area. Figure 20 shows the parameter RAM address map. 0x001010000­0x0101007F Suspended PT Parameters (128 Bytes) 0x001010800­0x010100DF Reserved (64 Bytes) 0x0010100E0­0x010100FB XPT Linked List Start Addresses (60 Bytes) 0x0010100FC­0x010100FF MP Linked List Start Address 0x001010100­0x0101017F Off-Chip to Off-Chip PT Buffer (128 Bytes) 0x001010180­0x0101021F Interrupt and Trap Vectors (160 Bytes) 0x001010220­0x0101029F 0x0010102A0­0x010107FF XPTf Linked List Start Add. XPTe Linked List Start Add. XPTd Linked List Start Add. XPTc Linked List Start Add. XPTb Linked List Start Add. XPTa Linked List Start Add. XPT9 Linked List Start Add. XPT8 Linked List Start Add. XPT7 Linked List Start Add. 0x010100E0 XPT6 Linked List Start Add. 0x010100E4 XPT Off-Chip to Off-Chip PT Buffer (128 Bytes) XPT5 Linked List Start Add. 0x010100E8 XPT4 Linked List Start Add. 0x010100EC General-Purpose RAM (3472 Bytes) XPT3 Linked List Start Add. 0x010100F0 XPT2 Linked List Start Add. 0x010100F4 XPT1 Linked List Start Add. 0x010100F8 Figure 20. MP Parameter RAM 28 POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 SMJ320C80 SMJ320C80 DIGITAL SIGNAL PROCESSOR SGUS025B SGUS025B ­ AUGUST 1998 ­ REVISED JUNE 2002 MP interrupt vectors Table 2 and Table 3 show the MP interrupts and traps and their vector addresses. Table 2. Maskable Interrupts IE BIT (TRAP#) NAME VECTOR ADDRESS 0 ie 0x01010180 2 fi 0x01010188 Floating-point invalid 3 fz 0x0101018C Floating-point divide-by-zero 5 fo 0x01010194 Floating-point overflow 6 fu 0x01010198 Floating-point underflow 7 fx 0x0101019C Floating-point inexact 8 f0 0x010101A0 Reserved 9 f1 0x010101A4 Reserved MASKABLE INTERRUPT 10 ti 0x010101A8 MP timer interrupt 11 x1 0x010101AC External interrupt 1 (EINT1) 12 x2 0x010101B0 External interrupt 2 (EINT2) 14 mf 0x010101B8 Memory fault 15 io 0x010101BC Integer overflow 16 p0 0x010101C0 PP0 message interrupt 17 p1 0x010101C4 PP1 message interrupt 18 p2 0x010101C8 Reserved 19 p3 0x010101CC Reserved 25 mi 0x010101E4 MP message interrupt 26 pc 0x010101E8 Packet-transfer complete 27 pb 0x010101EC Packet-transfer busy 28 bp 0x010101F0 Bad packet transfer 29 x3 0x010101F4 External interrupt 3 (EINT3) 30 x4 0x010101F8 External interrupt 4 (LINT4) 31 pe 0x010101FC PP error Table 3. Nonmaskable Traps TRAP NUMBER NAME VECTOR ADDRESS 32 e1 0x01010200 Emulator trap1 (reserved) 33 e2 0x01010204 Emulator trap2 (reserved) 34 e3 0x01010208 Emulator trap3 (reserved) 35 e4 0x0101020C Emulator trap4 (reserved) 36 fe 0x01010210 Floating-point error 0x01010214 Reserved 0x01010218 Illegal MP instruction 39 0x0101021C Reserved 72 to 415 0x010102A0 to 0x010107FC 37 38 er POST OFFICE BOX 1443 NONMASKABLE TRAP System- or user-defined · HOUSTON, TEXAS 77251­1443 29 SMJ320C80 SMJ320C80 DIGITAL SIGNAL PROCESSOR SGUS025B SGUS025B ­ AUGUST 1998 ­ REVISED JUNE 2002 MP opcode formats The three basic classes of MP instruction opcodes are: short immediate, three register, and long immediate. Figure 21 shows the opcode structure for each class of instruction. 31 Short Immediate 27 26 Dest 31 Three Register Dest Source 2 1 1 15-Bit Immediate 13 12 11 1 Opcode 22 21 20 19 Source 2 0 Opcode 22 21 20 19 27 26 Dest 15 14 Source 2 27 26 31 Long Immediate 22 21 0 5 4 Options 13 12 11 1 Opcode 1 0 Source 1 5 4 Options 0 Source 1 32-Bit Long Immediate Figure 21. MP Opcode Formats MP opcode summary Table 4 through Table 6 show the opcode formats for the MP. Table 7 summarizes the master processor instruction set. 30 POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 SMJ320C80 SMJ320C80 DIGITAL SIGNAL PROCESSOR SGUS025B SGUS025B ­ AUGUST 1998 ­ REVISED JUNE 2002 MP opcode summary (continued) Table 4. Short-Immediate Opcodes 3 1 3 0 trap ­ ­ cmnd ­ ­ illop0 2 9 2 8 2 7 2 6 2 5 ­ ­ E ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ Dest swcr Dest brcr ­ ­ ­ 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 0 0 0 0 0 0 0 Unsigned Immediate 0 0 0 0 0 0 1 Unsigned Trap Number ­ 0 0 0 0 0 1 0 Unsigned Immediate ­ 0 0 0 0 1 0 0 Unsigned Control Register Number 0 0 0 0 1 0 1 Unsigned Control Register Number Source Dest rdcr 2 4 Source ­ ­ ­ ­ ­ ­ ­ 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 0 0 0 1 1 0 shift.dz Dest Source 0 0 0 1 0 0 0 ­ ­ ­ i n Endmask Dest Source 0 0 0 1 0 0 1 ­ ­ ­ i n Endmask Rotate shift.ds Dest Source 0 0 0 1 0 1 0 ­ ­ ­ i n Endmask Rotate shift.ez Dest Source 0 0 0 1 0 1 1 ­ ­ ­ i n Endmask Rotate shift.em Dest Source 0 0 0 1 1 0 0 ­ ­ ­ i n Endmask Rotate shift.es Dest Source 0 0 0 1 1 0 1 ­ ­ ­ i n Endmask Rotate shift.iz Dest Source 0 0 0 1 1 1 0 ­ ­ ­ i n Endmask Rotate ­ ­ ­ i n Endmask 0 0 Rotate shift.dm 0 1 Unsigned Control Register Number Rotate shift.im Dest Source 0 0 0 1 1 1 1 and.tt Dest Source2 0 0 1 0 0 0 1 Unsigned Immediate and.tf Dest Source2 0 0 1 0 0 1 0 Unsigned Immediate and.ft Dest Source2 0 0 1 0 1 0 0 Unsigned Immediate xor Dest Source2 0 0 1 0 1 1 0 Unsigned Immediate or.tt Dest Source2 0 0 1 0 1 1 1 Unsigned Immediate and.ff Dest Source2 0 0 1 1 0 0 0 Unsigned Immediate xnor Dest Source2 0 0 1 1 0 0 1 Unsigned Immediate or.tf Dest Source2 0 0 1 1 0 1 1 Unsigned Immediate or.ft Dest Source2 0 0 1 1 1 0 1 Unsigned Immediate or.ff Dest Source2 0 0 1 1 1 1 0 Unsigned Immediate ld Dest Base 0 1 0 0 M SZ Signed Offset ld.u Dest Base 0 1 0 1 M SZ Signed Offset Base 0 1 1 0 M SZ Signed Offset Source2 0 1 1 1 M st dcache Source ­ ­ ­ ­ F ­ ­ ­ ­ 0 Signed Offset bsr Link 1 0 0 0 0 0 A Signed Offset jsr Link Base 1 0 0 0 1 0 A Signed Offset bbz BITNUM Source 1 0 0 1 0 0 A Signed Offset bbo BITNUM Source 1 0 0 1 0 1 A Signed Offset bcnd Cond Source 1 0 0 1 1 0 A Signed Offset cmp Dest Source2 1 0 1 1 0 0 0 Signed Immediate add Dest Source2 1 0 1 1 0 0 U Signed Immediate sub ­ A E F i ­ 0 Dest Source2 1 0 1 1 0 1 U Signed Immediate Reserved bit (code as 0) Annul delay slot instruction if branch taken Emulation trap bit Clear present flags Invert endmask POST OFFICE BOX 1443 M n SZ U Modify, write modified address back to register Rotate sense for shifting Size (0 = byte, 1 = halfword, 2 = word, 3 = doubleword) Unsigned form · HOUSTON, TEXAS 77251­1443 31 SMJ320C80 SMJ320C80 DIGITAL SIGNAL PROCESSOR SGUS025B SGUS025B ­ AUGUST 1998 ­ REVISED JUNE 2002 MP opcode summary (continued) Table 5. Long-Immediate and Three-Register Opcodes 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 trap ­ ­ ­ ­ E ­ ­ ­ ­ ­ 1 1 0 0 0 0 0 0 1 I ­ ­ ­ ­ ­ ­ ­ IND TR cmnd ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ 1 1 0 0 0 0 0 1 0 I ­ ­ ­ ­ ­ ­ ­ Source1 ­ ­ ­ ­ ­ 1 1 0 0 0 0 1 0 0 I ­ ­ ­ ­ ­ ­ ­ IND CR 1 1 0 0 0 0 1 0 1 I ­ ­ ­ ­ ­ ­ ­ IND CR 1 1 0 0 0 0 1 1 0 I ­ ­ ­ ­ ­ ­ ­ IND CR rdcr Dest swcr Dest brcr ­ ­ ­ Source ­ ­ ­ ­ ­ ­ ­ 0 4 0 3 0 2 0 1 shift.dz Dest Source 1 1 0 0 0 1 0 0 0 I i n Endmask Rotate shift.dm Dest Source 1 1 0 0 0 1 0 0 1 I i n Endmask Rotate shift.ds Dest Source 1 1 0 0 0 1 0 1 0 I i n Endmask Rotate shift.ez Dest Source 1 1 0 0 0 1 0 1 1 I i n Endmask Rotate shift.em Dest Source 1 1 0 0 0 1 1 0 0 I i n Endmask Rotate shift.es Dest Source 1 1 0 0 0 1 1 0 1 I i n Endmask Rotate shift.iz Dest Source 1 1 0 0 0 1 1 1 0 I i n Endmask Rotate shift.im Dest Source 1 1 0 0 0 1 1 1 1 I i n Endmask Rotate and.tt Dest Source2 1 1 0 0 1 0 0 0 1 I ­ ­ ­ ­ ­ ­ ­ Source1 and.tf Dest Source2 1 1 0 0 1 0 0 1 0 I ­ ­ ­ ­ ­ ­ ­ Source1 and.ft Dest Source2 1 1 0 0 1 0 1 0 0 I ­ ­ ­ ­ ­ ­ ­ Source1 xor Dest Source2 1 1 0 0 1 0 1 1 0 I ­ ­ ­ ­ ­ ­ ­ Source1 or.tt Dest Source2 1 1 0 0 1 0 1 1 1 I ­ ­ ­ ­ ­ ­ ­ Source1 and.ff Dest Source2 1 1 0 0 1 1 0 0 0 I ­ ­ ­ ­ ­ ­ ­ Source1 xnor Dest Source2 1 1 0 0 1 1 0 0 1 I ­ ­ ­ ­ ­ ­ ­ Source1 or.tf Dest Source2 1 1 0 0 1 1 0 1 1 I ­ ­ ­ ­ ­ ­ ­ Source1 or.ft Dest Source2 1 1 0 0 1 1 1 0 1 I ­ ­ ­ ­ ­ ­ ­ Source1 or.ff Dest Source2 1 1 0 0 1 1 1 1 0 I ­ ­ ­ ­ ­ ­ ­ Source1 ld Dest Base 1 1 0 1 0 0 M SZ I S D ­ ­ ­ ­ ­ Offset ld.u Dest Base 1 1 0 1 0 1 M SZ I S D ­ ­ ­ ­ ­ Offset Source Base 1 1 0 1 1 0 M SZ I S D ­ ­ ­ ­ ­ Offset 1 1 0 1 1 1 M 0 0 I 0 0 ­ ­ ­ ­ ­ Source 1 1 1 0 0 0 0 0 A I ­ ­ ­ ­ ­ ­ ­ 0 0 Offset st dcache bsr ­ ­ ­ ­ F Link Source2 ­ ­ ­ ­ ­ jsr 1 1 1 0 0 0 1 0 A I ­ ­ ­ ­ ­ ­ ­ Offset Source 1 1 1 0 0 1 0 0 A I ­ ­ ­ ­ ­ ­ ­ Target BITNUM Source 1 1 1 0 0 1 0 1 A I ­ ­ ­ ­ ­ ­ ­ Target bcnd Cond Source 1 1 1 0 0 1 1 0 A I ­ ­ ­ ­ ­ ­ ­ Target cmp Dest Source2 1 1 1 0 1 0 0 0 0 I ­ ­ ­ ­ ­ ­ ­ Source1 add Dest Source2 1 1 1 0 1 1 0 0 U I ­ ­ ­ ­ ­ ­ ­ Source1 sub 32 Base BITNUM bbo ­ D E F i Link bbz Dest Source2 1 1 1 0 1 1 0 1 U I ­ ­ ­ ­ ­ ­ ­ Source1 Reserved bit (code as 0) Direct external access bit Emulation trap bit Clear present flags Invert endmask l M n S SZ POST OFFICE BOX 1443 Long immediate Modify, write modified address back to register Rotate sense for shifting Scale offset by data size Size (0 = byte, 1 = halfword, 2 = word, 3 = doubleword · HOUSTON, TEXAS 77251­1443 SMJ320C80 SMJ320C80 DIGITAL SIGNAL PROCESSOR SGUS025B SGUS025B ­ AUGUST 1998 ­ REVISED JUNE 2002 MP opcode summary (continued) Table 6. Miscellaneous Instruction Opcodes 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 vadd Mem Src/Dst Source2/Dest 1 1 1 1 0 ­ 0 0 0 I ­ m P ­ d m s Source1 vsub Mem Src/Dst Source2/Dest 1 1 1 1 0 ­ 0 0 1 I ­ m P ­ d m s 0 0 Source1 vmpy Mem Src/Dst Source2/Dest 1 1 1 1 0 ­ 0 1 0 I ­ m P ­ d m s Source1 vmsub Mem Src/Dst Dest 1 1 1 1 0 a 0 1 1 I a m P Z ­ m ­ Source1 vrnd(FP) Mem Src/Dst Dest 1 1 1 1 0 a 1 0 0 I a m P m s Source1 vrnd(Int) Mem Src/Dst Dest 1 1 1 1 0 ­ 1 0 1 I ­ m P ­ d m s Source1 vmac Mem Src/Dst Source2 1 1 1 1 0 a 1 1 0 I a m P Z ­ m ­ Source1 vmac Mem Src/Dst Source2 1 1 1 1 0 a 1 1 1 I a m P Z ­ m ­ Source1 fadd Dest Source2 1 1 1 1 1 0 0 0 0 I ­ PD P2 P1 Source1 fsub Dest Source2 1 1 1 1 1 0 0 0 1 I ­ PD P2 P1 Source1 fmpy Dest Source2 1 1 1 1 1 0 0 1 0 I ­ PD P2 P1 Source1 fdiv Dest Source2 1 1 1 1 1 0 0 1 1 I ­ PD P2 P1 Source1 frndx Dest ­ 1 1 1 1 1 0 1 0 0 I ­ PD RM P1 Source1 1 1 1 1 1 0 1 0 1 I ­ ­ P2 P1 Source1 ­ 1 1 1 1 1 0 1 1 1 I ­ PD P1 Source1 ­ ­ ­ ­ ­ ­ Source2 PD fcmp Dest fsqrt Dest lmo Dest Source 1 1 1 1 1 1 0 0 0 ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ rmo Dest Source 1 1 1 1 1 1 0 0 1 ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ estop ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ 1 1 1 1 1 1 1 1 0 ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ illopF ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ 1 1 1 1 1 1 1 1 1 C ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ a C d l m Mem Src/Dst Dest Reserved bit (code as 0) Floating-point accumulator select Constant operands rather than register Destination precision for vector (0 = sp, 1 = dp) Long immediate 32-bit data Parallel memory operation specifier Vector store or load source/dst register Destination register POST OFFICE BOX 1443 P P1 P2 PD RM S Z Destination precision for parallel load/store (0 = single, 1 = double) Precision of source1 operand Precision of source2 operand Precision of destination result Rounding Mode (0 = N, 1 = Z, 2 = P, 3 = M) Scale offset by data size Use 0 rather than accumulator · HOUSTON, TEXAS 77251­1443 33 SMJ320C80 SMJ320C80 DIGITAL SIGNAL PROCESSOR SGUS025B SGUS025B ­ AUGUST 1998 ­ REVISED JUNE 2002 MP opcode summary (continued) Table 7. Summary of MP Opcodes INSTRUCTION add DESCRIPTION INSTRUCTION DESCRIPTION Signed integer add or.ff Bitwise OR with 1s complement and.tt Bitwise AND or.ft Bitwise OR with 1s complement and.ff Bitwise AND with 1s complement or.tf Bitwise OR with 1s complement and.ft Bitwise AND with 1s complement rdcr Read control register and.tf Bitwise AND with 1s complement rmo Rightmost one bbo Branch bit one shift.dz Shift, disable mask, zero extend bbz Branch bit zero shift.dm Shift, disable mask, merge bcnd Branch conditional shift.ds Shift, disable mask, sign extend Branch always shift.ez Shift, enable mask, zero extend brcr Branch control register shift.em Shift, enable mask, merge bsr br Branch and save return shift.es Shift, enable mask, sign extend cmnd Send command shift.iz Shift, invert mask, zero extend cmp Integer compare shift.im Shift, invert mask, merge dcache Flush data cache sub-block st Store register into memory estop Emulation stop sub Signed integer subtract fadd Floating-point add swcr Swap control register fcmp Floating-point compare trap Trap Floating-point divide vadd Vector floating-point add fmpy Floating-point multiply vmac Vector floating-point multiply and add to accumulator frndx Floating-point convert/round vmpy Vector floating-point multiply fsqrt Floating-point square root vmsc Vector floating-point multiply and subtract from accumulator fsub Floating-point subtract vmsub Vector floating-point subtract accumulator from source illop Illegal operation vrnd(FP) Vector round with floating-point input jsr Jump and save return vrnd(Int) Vector round with integer input ld Load signed into register vsub Vector floating-point subtract ld.u Load unsigned into register xnor Bitwise exclusive NOR lmo Leftmost one xor Bitwise exclusive OR or.tt Bitwise OR fdiv 34 POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 SMJ320C80 SMJ320C80 DIGITAL SIGNAL PROCESSOR SGUS025B SGUS025B ­ AUGUST 1998 ­ REVISED JUNE 2002 PP architecture The parallel processor (PP) is a 32-bit integer DSP optimized for imaging and graphics applications. Each PP can execute in parallel: a multiply, ALU operation, and two memory accesses within a single instruction. This internal parallelism allows a single PP to achieve over 500 million operations per second for certain algorithms. The PP has a three-input ALU that supports all 256 three input Boolean combinations and many combinations of arithmetic and Boolean functions. Data-merging and bit-to-byte, bit-to-word, and bit-to-halfword translations are supported by hardware in the input data path to the ALU. Typical tasks performed by a PP include: D Pixel-intensive processing ­ Motion estimation ­ Convolution ­ PixBLTs ­ Warp ­ Histogram ­ Mean square error D Domain transforms ­ Discrete Cosine Transform (DCT) ­ Fast Fourier Transform (FFT) ­ Hough D Core graphics functions ­ Line ­ Circle ­ Shaded fills ­ Fonts D Image analysis ­ Segmentation ­ Feature extraction D Bit-stream encoding/decoding ­ Data merging ­ Table look-ups POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 35 SMJ320C80 SMJ320C80 DIGITAL SIGNAL PROCESSOR SGUS025B SGUS025B ­ AUGUST 1998 ­ REVISED JUNE 2002 PP functional block diagram Figure 22 shows a block diagram of a parallel processor. Key features of the PP include: D 64-bit instruction word (supports multiple parallel operations) D Three-stage pipeline for fast instruction cycle D Numerous registers ­ 8 data, 10 address, 6 index registers ­ 20 other user-visible registers D Data Unit ­ 16 x 16 integer multiplier (optional dual 8 x 8) ­ Splittable 3-input ALU ­ 32-bit barrel rotator ­ Mask generator ­ Multiple status flag expander for translations to/from 1 bit-per-pixel space. ­ Conditional assignment of data unit results ­ Conditional source selection ­ Special processing hardware Leftmost one/rightmost one Leftmost bit change/rightmost bit change D Memory addressing ­ Two address units (global and local) provide up to two 32-bit accesses in parallel with data unit operation. ­ 12 addressing modes (immediate and indexed) ­ Byte, halfword, and word addressability ­ Scaled indexed addressing ­ Conditional assignment for loads ­ Conditional source selection for stores D Program flow ­ Three hardware loop controllers Zero overhead looping/branching Nested loops Multiple loop endpoints ­ Instruction cache management ­ PC mapped to register file ­ Interrupts for messages and context switching D Algebraic assembly language 36 POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 SMJ320C80 SMJ320C80 DIGITAL SIGNAL PROCESSOR SGUS025B SGUS025B ­ AUGUST 1998 ­ REVISED JUNE 2002 PP functional block diagram (continued) Data Unit d0­d7 Multiplier Data Path ALU Data Path Expander Mask Generator Barrel Rotator Three-Input ALU mf and sr Registers Figure 22. PP Block Diagram POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 37 SMJ320C80 SMJ320C80 DIGITAL SIGNAL PROCESSOR SGUS025B SGUS025B ­ AUGUST 1998 ­ REVISED JUNE 2002 PP registers The PP contains many general-purpose registers, status registers, and configuration registers. All PP registers are 32-bit registers. Figure 23 shows the accessible registers of the PP blocks. Data-Unit Registers Data Registers Multiple Flags Status d0/EALU Operation mf sr d1 d2 d3 d4 d5 d6 d7 Address-Unit Registers Global-Address Unit Address Registers Index Flags Local-Address Unit Address Registers Index Flags a8 x8 a0 x0 a9 x9 a1 x1 a10 x10 a2 x2 a11 a3 a12 a14/sp a15 = 0 a4 Stack Pointer Same Physical Register Program Flow Control (PFC) Unit Registers PC-Related Registers Loop Addresses a6/sp a7 = 0 Loop Counts Communications pc (br, call) ls0 lr0 comm iprs ls1 lr1 Interrupts ipa (read only) ls2 lr2 lntflg ipe (read only) le0 lc0 inten Cache Tags le1 lc1 tag0 (read only) le2 lc2 tag1 (read only) tag2 (read only) Loop Control tag3 (read only) lctl Figure 23. PP Registers 38 POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 SMJ320C80 SMJ320C80 DIGITAL SIGNAL PROCESSOR SGUS025B SGUS025B ­ AUGUST 1998 ­ REVISED JUNE 2002 PP data-unit registers The data unit contains eight 32-bit general-purpose data registers (d0­d7) referred to as the D registers. The d0 register also acts as the control register for extended ALU (EALU) operations. d0 register Figure 24 shows the format when d0 is used as the EALU control register. 31 30 29 28 FMOD FMOD A C I S N 27 26 A 25 24 23 22 21 20 19 17 16 15 14 13 12 11 10 9 C EALU Function Code 18 I S N E F T ­ ­ DMS E F DMS M R DBR Function modifiers Arithmetic enable EALU carry-In Invert-carry-In Sign extend Nonmultiple mask 8 7 6 5 4 3 M R U 2 1 0 DBR Explicit multiple carry-in Expanded multiple flags Default multiply shift amount Split multiply Rounded multiply Default barrel rotate amount Figure 24. d0 Format for EALU Operations multiple flags (mf) register The mf register records status information from each split ALU segment for multiple arithmetic operations. The mf register can be expanded to generate a mask for the ALU. Figure 25 shows the mf register format. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 7 6 5 6 5 4 3 2 4 3 2 1 0 1 0 Figure 25. mf Register Format status register (sr) The sr contains status and control bits for the PP ALU. See Figure 26. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 N C V Z ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ MSS N C V Z R Negative status bit Carry status bit Overflow status bit Zero status bit Rotation bit MSS Msize Asize R Msize Asize mf status selection 00 ­ set by zero 10 ­ set by extended result 01 ­ set by sign 11 ­ reserved Expander data size Split ALU data size Figure 26. sr Format PP address-unit registers address registers The address unit contains ten 32-bit address registers which contain the base address for address computations or which can be used for general-purpose data. The registers a0 ­ a4 are used for local-address computations and registers a8­a12 are used for global-address computations. POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 39 SMJ320C80 SMJ320C80 DIGITAL SIGNAL PROCESSOR SGUS025B SGUS025B ­ AUGUST 1998 ­ REVISED JUNE 2002 index registers The six 32-bit index registers contain index values for use with the address registers in address computations or they can be used for general-purpose data. Registers x0­x3 are used by the local-address unit and registers x8­x9 are used by the global-address unit. stack pointer (sp) The sp contains the address of the top of the PP's system stack. The stack pointer is addressed as a6 by the local-address unit and as a14 by the global-address unit. Figure 27 shows the sp register format. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 Word-Aligned Address 0 Figure 27. sp Register Format zero registers The zero registers are read-as-zero address registers for the local address unit (a7) and global-address unit (a15). Writes to the registers are ignored and can be specified when operational results are to be discarded. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 28. Zero Registers PP program flow control (PFC) unit registers loop registers The loop registers control three levels of zero-overhead loops. The 32-bit loop-start registers (ls0 ­ ls2) and loop-end registers (le0 ­ le2) contain the starting and ending addresses for the loops. The loop-counter registers (lc0 ­ lc2) contain the number of repetitions remaining in their associated loops. The lr0 ­ lr2 registers are loop reload registers used to support nested loops. The format for the loop-control (lctl) register is shown in Figure 29. There are also six special write-only mappings of the loop-reload registers. The lrs0 ­ lrs2 codes are used for fast initialization of lsn, lrn, and lcn registers for multi-instruction loops while the lrse0 ­ lrse2 codes are used for single instruction-loop fast initialization. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ E E LCDn Loop-end enable Loop-counter designator 000 ­ None 010 ­ lc1 001 ­ lc0 011 ­ lc2 1xx ­ reserved 10 9 LCD2 le2 8 7 E 6 5 LCD1 le1 4 3 E 2 1 0 LCD0 le0 Figure 29. lctl Register pipeline registers The PFC unit contains a pointer to each stage of the PP pipeline. The pc contains the program counter which points to the instruction being fetched. The ipa points to the instruction in the address stage of the pipeline and the ipe points to the instruction in the execute stage of the pipeline. The instruction pointer return-from-subroutine (iprs) register contains the return address for a subroutine call. 40 POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 SMJ320C80 SMJ320C80 DIGITAL SIGNAL PROCESSOR SGUS025B SGUS025B ­ AUGUST 1998 ­ REVISED JUNE 2002 pipeline registers (continued) 31 30 29 28 27 26 25 24 23 22 21 pc 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 PC (29-Bit Doubleword Address) G ­ Global Interrupt Enable 31 30 29 28 27 26 25 24 23 22 21 ipa 20 19 2 1 0 ­ G L L ­ Loop Inhibit 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 32-Bit Copy of the Previous pc Register Value 31 30 29 28 27 26 25 24 23 22 ipe 21 20 19 18 17 16 15 14 13 12 11 10 32-Bit Copy of the Previous ipa Register Value 31 30 29 28 27 26 25 24 23 22 21 iprs 20 19 18 17 16 15 14 13 12 11 10 2 1 0 ­ 29-Bit Doubleword Return Address ­ ­ Figure 30. Pipeline Registers interrupt registers The interrupt-enable (inten) register allows individual interrupts to be enabled and configures the interrupt flag (intflg) register operation. The intflg register contains the interrupt flag bits. Interrupt priority increases moving from left to right on intflg. 31 inten 30 29 28 r r r r 27 24 23 22 21 20 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 E E E E 26 25 ­ ­ ­ E E E E ­ ­ E ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ W P P P P 3 2 M M S S G G P P 1 M S G 19 18 M P M S G P P 0 M S G P T E N D P T E R R P T Q 0 T A S K 31 intflg 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r r r r I I I I ­ ­ ­ I I I I ­ ­ I ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ r E W PPnMSG Reserved (write as 0) Enable interrupt Write mode 0 ­ writing 1 clears intflg 1 ­ writing 1 sets intflg PPn message interrupt MPMSG PTEND PTERR PTQ TASK MP message interrupt Packet transfer complete Packet-transfer error Packet transfer queued MP task interrupt Figure 31. PP-Interrupt Registers POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 41 SMJ320C80 SMJ320C80 DIGITAL SIGNAL PROCESSOR SGUS025B SGUS025B ­ AUGUST 1998 ­ REVISED JUNE 2002 communication (comm) register The comm register contains the packet-transfer handshake bits and PP indicator bits. 31 30 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 H S Q P 29 ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ H S Q P PP# High-priority packet transfer Packet-transfer suspend Packet transfer queued Submit packet transfer request 2 1 0 PP# PP Number (read only) 000 ­ PP0 010 ­ PP2 001 ­ PP1 011 ­ PP3 1xx ­ Not implemented Figure 32. comm Register cache-tag registers The tag0 ­ tag3 registers contain the tag address and sub-block present bits for each cache block. 31