SM320C6414-EP SM320C6415-EP SM320C6416-EP SGUS043D C6414/15/16 C6416 - Datasheet Archive

 

FIXED-POINT DIGITAL SIGNAL PROCESSORS www.ti.com SGUS043D ­ MAY 2003 ­ REVISED SEPTEMBER 2008 1 Introduction 1.1 Features

 

SM320C6414-EP SM320C6414-EP, SM320C6415-EP SM320C6415-EP, SM320C6416-EP SM320C6416-EP FIXED-POINT DIGITAL SIGNAL PROCESSORS www.ti.com SGUS043D SGUS043D ­ MAY 2003 ­ REVISED SEPTEMBER 2008 1 Introduction 1.1 Features · · · · · · · Highest-Performance Fixed-Point Digital Signal Processors (DSPs) ­ 2-ns Instruction Cycle Time ­ 500-MHz Clock Rate ­ Eight 32-Bit Instructions/Cycle ­ 28 Operations/Cycle ­ 4000 MIPS ­ Fully Software Compatible With C62xTM ­ C6414/15/16 C6414/15/16 Devices Pin Compatible VelociTI.2TM Extensions to VelociTITM Advanced Very Long Instruction Word (VLIW) TMS320C64xTM DSP Core ­ Eight Highly Independent Functional Units With VelociTI.2 Extensions With Six ALUs and Two Multipliers ­ Nonaligned Load-Store Architecture ­ 64 32-Bit General-Purpose Registers ­ Instruction Packing Reduces Code Size ­ All Instructions Conditional Instruction Set Features ­ Byte-Addressable (8-/16-/32-/64-Bit Data) ­ 8-Bit Overflow Protection ­ Bit-Field Extract, Set, Clear ­ Normalization, Saturation, Bit Counting ­ VelociTI.2 Increased Orthogonality Viterbi Decoder Coprocessor (VCP) (C6416 C6416) ­ Supports Over 500 7.95-Kbps Adaptive Multi-Rate (AMR) ­ Programmable Code Parameters Turbo Decoder Coprocessor (TCP) (C6416 C6416) ­ Supports up to Six 2-Mbps 3GPP (Six Iterations) ­ Programmable Turbo Code and Decoding Parameters L1/L2 Memory Architecture ­ 128K-Bit (16K-Byte) L1P Program Cache ­ 128K-Bit (16K-Byte) L1D Data Cache ­ 8M-Bit (1024K-Byte) L2 Unified Mapped RAM/Cache Two External Memory Interfaces (EMIFs) for · · · · · · · · · · · · (1) 1280M-Byte Addressable External Memory Enhanced Direct Memory Access (EDMA) Controller (64 Independent Channels) Host-Port Interface (HPI) ­ User-Configurable Bus Width (32/16 Bit) 32-Bit/33-MHz, 3.3-V PCI Master/Slave Interface Conforms to PCI Specification 2.2 (C6415/C6416 C6415/C6416) ­ Three PCI Bus Address Registers ­ Four-Wire Serial EEPROM Interface ­ PCI Interrupt Request Under DSP Program Control ­ DSP Interrupt Via PCI I/O Cycle Three Multichannel Buffered Serial Ports (McBSPs) ­ Direct Interface to T1/E1, MVIP, and SCSA Framers ­ Up to 256 Channels Each ­ ST Bus Switching, AC97 Compatible ­ Serial Peripheral Interface (SPI) Compatible (Motorola) Three 32-Bit General-Purpose Timers Universal Test and Operations Physical Layer (PHY) Interface for ATM (UTOPIA) (C6415/C6416 C6415/C6416) ­ UTOPIA Level-2 Slave ATM Controller ­ 8-Bit Transmit and Receive Operations up to 50 MHz per Direction ­ User-Defined Cell Format up to 64 Bytes 16 General-Purpose I/O (GPIO) Pins Flexible Phase-Locked Loop (PLL) Clock Generator IEEE Std 1149.1 (JTAG (1) Boundary Scan Compatible 532-Pin Ball Grid Array (BGA) Package (GLZ Suffix), 0.8-mm Ball Pitch 0.13-µm/6-Level Metal Process (CMOS) 3.3-V I/Os, 1.25-V Internal (500 MHz) IEEE Std 1149.1-1990 Standard Test-Access Port and Boundary Scan Architecture Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this document. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2003­2008, Texas Instruments Incorporated SM320C6414-EP SM320C6414-EP, SM320C6415-EP SM320C6415-EP, SM320C6416-EP SM320C6416-EP FIXED-POINT DIGITAL SIGNAL PROCESSORS SGUS043D SGUS043D ­ MAY 2003 ­ REVISED SEPTEMBER 2008 www.ti.com 1.2 SUPPORTS DEFENSE, AEROSPACE, AND MEDICAL APPLICATIONS · · · · Controlled Baseline One Assembly/Test Site One Fabrication Site Available in A-Version (­40°C/105 C/105°C) and S-Version (­55°C/105 C/105°C) Temperature · · · (2) Ranges (2) Extended Product Life Cycle Extended Product-Change Notification Product Traceability S-Version currently available for C6415 C6415 only. Additional custom temperature ranges available upon request. 1.3 Description The TMS320C64xTM DSPs (including the SM320C6414-EP SM320C6414-EP, SM320C6415-EP SM320C6415-EP, and SM320C6416-EP SM320C6416-EP devices) are the highest-performance fixed-point DSP generation in the TMS320C6000TM TMS320C6000TM DSP platform. The SM320C64xTM (C64xTM) device is based on the second-generation, high-performance, advanced VelociTITM very-long-instruction word (VLIW) architecture (VelociTI.2TM) developed by Texas Instruments (TI), making these DSPs an excellent choice for multichannel and multifunctional applications. The C64xTM is a code-compatible member of the C6000TM C6000TM DSP platform. With performance of up to 4000 million instructions per second (MIPS) at a clock rate of 500 MHz, the C64x devices offer cost-effective solutions to high-performance DSP programming challenges. The C64x DSPs possess the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units ­ 2 multipliers for a 32-bit result and 6 arithmetic logic units (ALUs) ­ with VelociTI.2 extensions. The VelociTI.2 extensions in the eight functional units include new instructions to accelerate the performance in key applications and extend the parallelism of the VelociTI architecture. The C64x can produce four 32-bit multiply-accumulates (MACs) per cycle for a total of 2400 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 4800 MMACS. The C64x DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000 C6000 DSP platform devices. The C6416 C6416 device has two high-performance embedded coprocessors [Viterbi decoder coprocessor (VCP) and turbo decoder coprocessor (TCP)] that significantly speed up channel-decoding operations on chip. The VCP operating at CPU clock divided-by-4 can decode over 500 7.95-Kbps adaptive multi-rate (AMR) (K = 9, R = 1/3) voice channels. The VCP supports constraint lengths K = 5, 6, 7, 8, and 9, rates R = 1/2, 1/3, and 1/4, and flexible polynomials, while generating hard decisions or soft decisions. The TCP operating at CPU clock divided-by-2 can decode up to 36 384-Kbps or 6 2-Mbps turbo encoded channels (assuming iterations). The TCP implements the max*log-map algorithm and is designed to support all polynomials and rates required by Third-Generation Partnership Projects (3GPP and 3GPP2), with fully programmable frame length and turbo interleaver. Decoding parameters, such as the number of iterations and stopping criteria, are also programmable. Communications between the VCP/TCP and the CPU are carried out through the EDMA controller. The C64x uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. The level 1 program (L1P) cache is a 128K-bit direct-mapped cache and the level 1 data (L1D) cache is a 128K-bit 2-way set-associative cache. The level 2 memory/cache (L2) consists of an 8M-bit memory space that is shared between program and data space. L2 memory can be configured as mapped memory or combinations of cache (up to 256K bytes) and mapped memory. The peripheral set includes 3 multichannel buffered serial ports (McBSPs), an 8-bit universal test and operations PHY interface for asynchronous transfer mode (ATM) slave (UTOPIA slave) port (C6415/C6416 C6415/C6416 only), 3 32-bit general-purpose timers, a user-configurable 16-bit or 32-bit host-port interface (HPI16/HPI32 HPI16/HPI32), a peripheral component interconnect (PCI) (C6415/C6416 C6415/C6416 only), a general-purpose input/output port (GPIO) with 16 GPIO pins, and two glueless external memory interfaces (64-bit EMIFA and 16-bit EMIFB), both of which are capable of interfacing to synchronous and asynchronous memories and peripherals. 2 Introduction Submit Documentation Feedback SM320C6414-EP SM320C6414-EP, SM320C6415-EP SM320C6415-EP, SM320C6416-EP SM320C6416-EP FIXED-POINT DIGITAL SIGNAL PROCESSORS www.ti.com SGUS043D SGUS043D ­ MAY 2003 ­ REVISED SEPTEMBER 2008 The C64x has a complete set of development tools that includes an advanced C compiler with C64x-specific enhancements, an assembly optimizer to simplify programming and scheduling, and a WindowsTM debugger interface for visibility into source code execution. (3) (4) (3) (4) Throughout the remainder of this document, the SM320C6414-EP SM320C6414-EP, SM320C6415-EP SM320C6415-EP, and SM320C6416-EP SM320C6416-EP are referred to as SM320C64x or C64x where generic and, where specific, their individual full device part numbers are used or abbreviated as C6414 C6414, C6415 C6415, or C6416 C6416, respectively. These C64x devices have two EMIFs (64-bit EMIFA and 16-bit EMIFB). The prefix "A" in front of a signal name indicates it is an EMIFA signal whereas a prefix "B" in front of a signal name indicates it is an EMIFB signal. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix "A" or "B" may be omitted from the signal name. 1.4 Ball-Grid Array (BGA) Package GLZ 532-PIN 532-PIN BALL GRID ARRAY (BGA) PACKAGE ( BOTTOM VIEW ) AF AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A 1 3 2 Submit Documentation Feedback 5 4 7 6 9 8 11 13 15 17 19 21 23 25 10 12 14 16 18 20 22 24 26 Introduction 3 SM320C6414-EP SM320C6414-EP, SM320C6415-EP SM320C6415-EP, SM320C6416-EP SM320C6416-EP FIXED-POINT DIGITAL SIGNAL PROCESSORS SGUS043D SGUS043D ­ MAY 2003 ­ REVISED SEPTEMBER 2008 www.ti.com 1.4.1 Device Characteristics Table 1-1 provides an overview of the C6414 C6414, C6415 C6415, and C6416 C6416 DSPs. Table 1-1 shows significant features of the C64x devices, including the capacity of on-chip RAM, the peripherals, the CPU frequency, and the package type with pin count. Table 1-1. Characteristics of the C6414 C6414, C6415 C6415, and C6416 C6416 Processors HARDWARE FEATURES EMIFA (64-bit bus width) (default clock source = AECLKIN) Peripherals C6414 C6414, C6415 C6415, AND C6416 C6416 1 EMIFB (16-bit bus width) (default clock source = BECLKIN) 1 Not all peripherals pins EDMA (64 independent channels) are available at the same HPI (32- or 16-bit user selectable) time. (For more details, see the Device PCI (32-bit) [DeviceID Register value 0xA106] Configuration section.) McBSPs Peripheral performance is (default internal clock source = CPU/4 clock frequency) dependent on chip-level UTOPIA (8-bit mode) configuration. 32-bit timers (default internal clock source = CPU/8 clock frequency) General-purpose input/output 0 (GP0) Decoder coprocessors CPU ID + CPU Rev ID 3 1 (C6415/C6416 C6415/C6416 only) 3 16 1 (C6416 C6416 only) TCP 1 (C6416 C6416 only) Organization Control Status Register (CSR[31:16]) Device_ID Silicon Revision Identification Register (DEVICE_REV[19:16]) Address: 0x01B0 0200 Frequency MHz Cycle time ns Voltage 1 (C6415/C6416 C6415/C6416 only) VCP Size (bytes) On-chip memory 1 1 (HPI16 HPI16 or HPI32 HPI32) Core (V) I/O (V) 1056K 1056K 16K-byte (16KB) L1 program (L1P) cache 16KB L1 data (L1D) cache 1024KB 1024KB unified mapped RAM/cache (L2) 0x0C01 DEVICE_REV[19:16] 1111 0001 0010 Silicon revision 1.03 or earlier 1.03 1.1 500 2 ns (C6414-50A C6414-50A, C6415-50A C6415-50A, C6416-50A C6416-50A) (500-MHz CPU, 100-MHz EMIF) (1) 1.25 V (-50A) 3.3 V PLL options CLKIN frequency multiplier Bypass (x1), x6, x12 BGA package 23 mm × 23 mm 532-pin BGA (GLZ) Process technology CMOS Product status Product Preview (PP) Advance Information (AI) Production Data (PD) (1) 4 0.3 µm PD On these C64x devices, the rated EMIF speed affects only the SDRAM interface on EMIFA. For more detailed information, see the EMIF Device Speed section of this data manual. Introduction Submit Documentation Feedback SM320C6414-EP SM320C6414-EP, SM320C6415-EP SM320C6415-EP, SM320C6416-EP SM320C6416-EP FIXED-POINT DIGITAL SIGNAL PROCESSORS www.ti.com SGUS043D SGUS043D ­ MAY 2003 ­ REVISED SEPTEMBER 2008 1.4.2 Device Compatiblity The C64x generation of devices has a diverse and powerful set of peripherals. The common peripheral set and pin compatibility that the C6414 C6414, C6415 C6415, and C6416 C6416 devices offer lead to easier system designs and faster time to market. Table 1-2 identifies the peripherals and coprocessors that are available on the C6414 C6414, C6415 C6415, and C6416 C6416 devices. The C6414 C6414, C6415 C6415, and C6416 C6416 devices are pin-for-pin compatible, provided the following conditions are met: · All devices use the same peripherals. ­ The C6414 C6414 is pin-for-pin compatible with the C6415/C6416 C6415/C6416 when the PCI and UTOPIA peripherals on the C6415/C6416 C6415/C6416 are disabled. ­ The C6415 C6415 is pin-for-pin compatible with the C6416 C6416 when they are in the same peripheral selection mode. For more information on peripheral selection, see the Device Configurations section of this data manual. · The BEA[9:7] pins are properly pulled up/down. ­ For more details on the device-specific BEA[9:7] pin configurations, see the Terminal Functions table of this data manual. Table 1-2. Peripherals and Coprocessors Available on C6414 C6414, C6415 C6415, and C6416 C6416 Devices (1) PERIPHERALS/COPROCESSORS (2) C6414 C6414 C6415 C6415 C6416 C6416 EMIFA (64-bit bus width) EMIFB (16-bit bus width) EDMA (64 independent channels) HPI (32- or 16-bit user selectable) PCI (32 bit) (specification v2.2) - McBSPs (McBSP0, McBSP1, McBSP2) UTOPIA (8-bit mode) (specification v1.0) - Timers (32 bit) (TIMER0, TIMER1, TIMER2) GPIOs (GP[15:0]) VCP/TCP coprocessors - - (1) (2) - denotes peripheral/coprocessor is not available on this device. Not all peripherals pins are available at the same time. (For more details, see the Device Configuration section.) Submit Documentation Feedback Introduction 5 SM320C6414-EP SM320C6414-EP, SM320C6415-EP SM320C6415-EP, SM320C6416-EP SM320C6416-EP FIXED-POINT DIGITAL SIGNAL PROCESSORS SGUS043D SGUS043D ­ MAY 2003 ­ REVISED SEPTEMBER 2008 www.ti.com For more detailed information on the device compatibility and similarities/differences among the C6414 C6414, C6415 C6415, and C6416 C6416 devices, see the How To Begin Development Today With the TMS320C6414 TMS320C6414, TMS320C6415 TMS320C6415, and TMS320C6416 TMS320C6416 DSPs application report (literature number SPRA718 SPRA718). 1.4.3 Functional Block and CPU (DSP Core) Diagram C64x Digital Signal Processor VCP(A) L1P Cache Direct-Mapped 16K Bytes Total TCP(A) SDRAM 64 SBSRAM 16 EMIF A EMIF B C64x DSP Core ZBT SRAM Instruction Fetch Timer 2 FIFO SRAM Control Registers Instruction Dispatch Advanced Instruction Packet Timer 1 ROM/FLASH Control Logic Instruction Decode Timer 0 I/O Devices Data Path A A Register File A31-A16 A31-A16 A15-A0 A15-A0 McBSP2 .L1 UTOPIA(B) UTOPIA: Up to 400 Mbps Master ATMC or McBSPs: Framing Chips: H.100, MVIP, SCSA, T1, E1 AC97 Devices, SPI Devices, Codecs Enhanced DMA Controller (64-channel) .S1 .M1 .D1 Data Path B Test B Register File B31-B16 B31-B16 B15-B0 B15-B0 .D2 .M2 .S2 Advanced In-Circuit Emulation .L2 L2 Memory 1024K 1024K Bytes Interrupt Control McBSP1(B) L1D Cache 2-Way Set-Associative 16K Bytes Total McBSP0 16 GPIO[8:0] GPIO[15:9](B) 32 HPI or PCI(B) Boot Configuration PLL (x1, x6, x12) Power-Down Logic Interrupt Selector A. 6 VCP and TCP decoder coprocessors are applicable to the C6416 C6416 device only. B. For the C6415 C6415 and C6416 C6416 devices, the UTOPIA peripheral is multiplexed with McBSP1, and the PCI peripheral is multiplexed with the HPI peripheral and the GPIO[15:9] port. For more details on the multiplexed pins of these peripherals, see the Device Configurations section of this data manual. Introduction Submit Documentation Feedback SM320C6414-EP SM320C6414-EP, SM320C6415-EP SM320C6415-EP, SM320C6416-EP SM320C6416-EP FIXED-POINT DIGITAL SIGNAL PROCESSORS www.ti.com SGUS043D SGUS043D ­ MAY 2003 ­ REVISED SEPTEMBER 2008 1.4.4 CPU (DSP Core) Description The CPU fetches VelociTI advanced very-long instruction words (VLIWs) (256 bits wide) to supply up to eight 32-bit instructions to the eight functional units during every clock cycle. The VelociTI VLIW architecture features controls by which all eight units do not have to be supplied with instructions if they are not ready to execute. The first bit of every 32-bit instruction determines if the next instruction belongs to the same execute packet as the previous instruction, or whether it should be executed in the following clock as a part of the next execute packet. Fetch packets are always 256 bits wide; however, the execute packets can vary in size. The variable-length execute packets are a key memory-saving feature, distinguishing the C64x CPUs from other VLIW architectures. The C64x VelociTI.2 extensions add enhancements to the TMS320C62xTM DSP VelociTI architecture. These enhancements include: · Register file enhancements · Data-path extensions · Quad 8-bit and dual 16-bit extensions with data-flow enhancements · Additional functional unit hardware · Increased orthogonality of the instruction set · Additional instructions that reduce code size and increase register flexibility The CPU features two sets of functional units. Each set contains four units and a register file. One set contains functional units .L1, .S1, .M1, and .D1. The other set contains units .D2, .M2, .S2, and .L2. The two register files each contain 32 32-bit registers for a total of 64 general-purpose registers. In addition to supporting the packed 16-bit and 32-/40-bit fixed-point data types found in the C62x VelociTI VLIW architecture, the C64x register files also support packed 8-bit data and 64-bit fixed-point data types. The two sets of functional units, along with two register files, compose sides A and B of the CPU [see the functional block and CPU (DSP core) diagram, and Figure 1-1]. The four functional units on each side of the CPU can freely share the 32 registers belonging to that side. Additionally, each side features a data cross path ­ a single data bus connected to all the registers on the other side, by which the two sets of functional units can access data from the register files on the opposite side. The C64x CPU pipelines data-cross-path accesses over multiple clock cycles. This allows the same register to be used as a data-cross-path operand by multiple functional units in the same execute packet. All functional units in the C64x CPU can access operands via the data cross path. Register access by functional units on the same side of the CPU as the register file can service all the units in a single clock cycle. On the C64x CPU, a delay clock is introduced when an instruction attempts to read a register via a data cross path if that register was updated in the previous clock cycle. In addition to the C62x DSP fixed-point instructions, the C64x DSP includes a comprehensive collection of quad 8-bit and dual 16-bit instruction set extensions. These VelociTI.2 extensions allow the C64x CPU to operate directly on packed data to streamline data flow and increase instruction set efficiency. Another key feature of the C64x CPU is the load/store architecture, where all instructions operate on registers (as opposed to data in memory). Two sets of data-addressing units (.D1 and .D2) are responsible for all data transfers between the register files and the memory. The data address driven by the .D units allows data addresses generated from one register file to be used to load or store data to or from the other register file. The C64x .D units can load and store bytes (8 bits), half words (16 bits), and words (32 bits) with a single instruction. And with the new data-path extensions, the C64x .D unit can load and store doublewords (64 bits) with a single instruction. Furthermore, the nonaligned load and store instructions allow the .D units to access words and doublewords on any byte boundary. The C64x CPU supports a variety of indirect addressing modes using either linear or circular addressing with 5- or 15-bit offsets. All instructions are conditional, and most can access any one of the 64 registers. Some registers, however, are singled out to support specific addressing modes or to hold the condition for conditional instructions (if the condition is not automatically true). Submit Documentation Feedback Introduction 7 SM320C6414-EP SM320C6414-EP, SM320C6415-EP SM320C6415-EP, SM320C6416-EP SM320C6416-EP FIXED-POINT DIGITAL SIGNAL PROCESSORS SGUS043D SGUS043D ­ MAY 2003 ­ REVISED SEPTEMBER 2008 www.ti.com The two .M functional units perform all multiplication operations. Each of the C64x .M units can perform two 16-bit × 16-bit multiplies or four 8-bit × 8-bit multiplies per clock cycle. The .M unit can also perform 16-bit × 32-bit multiply operations, dual 16-bit × 16-bit multiplies with add/subtract operations, and quad 8-bit × 8-bit multiplies with add operations. In addition to standard multiplies, the C64x .M units include bit-count, rotate, Galois field multiplies, and bidirectional variable shift hardware. The two .S and .L functional units perform a general set of arithmetic, logical, and branch functions, with results available every clock cycle. The arithmetic and logical functions on the C64x CPU include single 32-bit, dual 16-bit, and quad 8-bit operations. The processing flow begins when a 256-bit-wide instruction fetch packet is fetched from a program memory. The 32-bit instructions destined for the individual functional units are linked together by "1" bits in the least significant bit (LSB) position of the instructions. The instructions that are chained together for simultaneous execution (up to eight in total) compose an execute packet. A "0" in the LSB of an instruction breaks the chain, effectively placing the instructions that follow it in the next execute packet. A C64x DSP device enhancement now allows execute packets to cross fetch-packet boundaries. In the TMS320C62x/TMS320C67xTM DSP devices, if an execute packet crosses the fetch-packet boundary (256 bits wide), the assembler places it in the next fetch packet, while the remainder of the current fetch packet is padded with no-operation (NOP) instructions. In the C64x DSP device, the execute boundary restrictions have been removed, thereby, eliminating all of the NOPs added to pad the fetch packet and, thus, decreasing the overall code size. The number of execute packets within a fetch packet can vary from one to eight. Execute packets are dispatched to their respective functional units at the rate of one per clock cycle, and the next 256-bit fetch packet is not fetched until all the execute packets from the current fetch packet have been dispatched. After decoding, the instructions simultaneously drive all active functional units for a maximum execution rate of eight instructions every clock cycle. While most results are stored in 32-bit registers, they can be subsequently moved to memory as bytes, halfwords, words, or doublewords. All load and store instructions are byte, halfword, word, or doubleword addressable. For more details on the C64x CPU functional units enhancements, see the following documents: · TMS320C6000 TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189 SPRU189) · TMS320C64xTM Technical Overview (literature number SPRU395 SPRU395) · How to Begin Development Today With the TMS320C6414 TMS320C6414, TMS320C6415 TMS320C6415, and TMS320C6416 TMS320C6416 DSPs application report (literature number SPRA718 SPRA718) 8 Introduction Submit Documentation Feedback SM320C6414-EP SM320C6414-EP, SM320C6415-EP SM320C6415-EP, SM320C6416-EP SM320C6416-EP FIXED-POINT DIGITAL SIGNAL PROCESSORS www.ti.com SGUS043D SGUS043D ­ MAY 2003 ­ REVISED SEPTEMBER 2008 src1 .L1 src2 dst long dst long src ST1b (Store Data) ST1a (Store Data) 8 8 32 MSBs 32 LSBs long src long dst dst src1 .S1 Data Path A 8 8 Register File A (A0-A31 A0-A31) src2 See Note A See Note A long dst dst .M1 src1 src2 LD1b (Load Data) LD1a (Load Data) 32 MSBs 32 LSBs DA1 (Address) .D1 dst src1 src2 2X 1X src2 .D2 src1 dst DA2 (Address) LD2a (Load Data) LD2b (Load Data) 32 LSBs 32 MSBs src2 .M2 src1 dst long dst See Note A See Note A Register File B (B0- B31) src2 Data Path B .S2 src1 dst long dst long src ST2a (Store Data) ST2b (Store Data) 8 8 32 MSBs 32 LSBs long src long dst dst 8 8 .L2 src2 src1 Control Register File A. For the .M functional units, the long dst is 32 MSBs and the dst is 32 LSBs. Figure 1-1. SM320C64xTM CPU (DSP Core) Data Paths Submit Documentation Feedback Introduction 9 SM320C6414-EP SM320C6414-EP, SM320C6415-EP SM320C6415-EP, SM320C6416-EP SM320C6416-EP FIXED-POINT DIGITAL SIGNAL PROCESSORS SGUS043D SGUS043D ­ MAY 2003 ­ REVISED SEPTEMBER 2008 www.ti.com 1.4.5 Memory Map Summary Table 1-3 shows the memory map address ranges of the SM320C64x device. Internal memory is always located at address 0 and can be used as both program and data memory. The external memory address ranges in the C64x device begin at the hex address locations 0x6000 0000 for EMIFB and 0x8000 0000 for EMIFA. Table 1-3. SM320C64x Memory Map Summary MEMORY BLOCK DESCRIPTION BLOCK SIZE (BYTES) HEX ADDRESS RANGE Internal RAM (L2) 1M 0000 0000­000F FFFF Reserved 23M 0010 0000­017F FFFF External Memory Interface A (EMIFA) Registers 256K 0180 0000­0183 FFFF L2 Registers 256K 0184 0000­0187 FFFF HPI Registers 256K 0188 0000­018B FFFF McBSP 0 Registers 256K 018C 0000­018F FFFF McBSP 1 Registers 256K 0190 0000­0193 FFFF Timer 0 Registers 256K 0194 0000­0197 FFFF Timer 1 Registers 256K 0198 0000­019B FFFF Interrupt Selector Registers 256K 019C 0000­019F FFFF EDMA RAM and EDMA Registers 256K 01A0 0000­01A3 FFFF McBSP 2 Registers 256K 01A4 0000­01A7 FFFF EMIFB Registers 256K 01A8 0000­01AB FFFF Timer 2 Registers 256K 01AC 0000­01AF FFFF GPIO Registers 256K 01B0 0000­01B3 FFFF UTOPIA Registers (C6415 C6415 and C6416 C6416 only) (1) 256K 01B4 0000­01B7 FFFF TCP/VCP Registers (C6416 C6416 only) (2) 256K 01B8 0000­01BB FFFF Reserved 256K 01BC 0000­01BF FFFF PCI Registers (C6415 C6415 and C6416 C6416 only) (1) 256K 01C0 0000­01C3 FFFF 4M­256K 01C4 0000­01FF FFFF Reserved QDMA Registers 52 0200 0000­0200 0033 736M­52 0200 0034­2FFF FFFF McBSP 0 Data 64M 3000 0000­33FF FFFF McBSP 1 Data 64M 3400 0000­37FF FFFF McBSP 2 Data 64M 3800 0000­3BFF FFFF UTOPIA Queues (C6415 C6415 and C6416 C6416 only) (1) 64M 3C00 0000­3FFF FFFF Reserved 256K 4000 0000­4FFF FFFF Reserved TCP/VCP (C6416 C6416 only) (2) 256K 5000 0000­5FFF FFFF EMIFB CE0 64M 6000 0000­63FF FFFF EMIFB CE1 64M 6400 0000­67FF FFFF EMIFB CE2 64M 6800 0000­6BFF FFFF EMIFB CE3 64M 6C00 0000­6FFF FFFF Reserved 256K 7000 0000­7FFF FFFF EMIFA CE0 256K 8000 0000­8FFF FFFF EMIFA CE1 256K 9000 0000­9FFF FFFF EMIFA CE2 256K A000 0000­AFFF FFFF EMIFA CE3 256K B000 0000­BFFF FFFF 1G C000 0000­FFFF FFFF Reserved (1) (2) 10 For the C6414 C6414 device, these memory address locations are reserved. The C6414 C6414 device does not support the UTOPIA and PCI peripherals. Only the C6416 C6416 device supports the VCP/TCP coprocessors. For the C6414 C6414 and C6415 C6415 devices, these memory address locations are reserved. Introduction Submit Documentation Feedback SM320C6414-EP SM320C6414-EP, SM320C6415-EP SM320C6415-EP, SM320C6416-EP SM320C6416-EP FIXED-POINT DIGITAL SIGNAL PROCESSORS www.ti.com SGUS043D SGUS043D ­ MAY 2003 ­ REVISED SEPTEMBER 2008 1.4.6 Peripheral Register Descriptions Table 1-4 through Table 1-24 identify the peripheral registers for the C6414 C6414, C6415 C6415, and C6416 C6416 devices by their register names, acronyms, and hex address or hex address range. For more detailed information on the register contents and bit names and their descriptions, see the TMS320C6000 TMS320C6000 Peripherals Reference Guide (literature number SPRU190 SPRU190). Table 1-4. EMIFA Registers HEX ADDRESS ACRONYM REGISTER NAME 0180 0000 GBLCTL EMIFA Global Control 0180 0004 CECTL1 EMIFA CE1 Space Control 0180 0008 CECTL0 EMIFA CE0 Space Control 0180 000C ­ 0180 0010 CECTL2 EMIFA CE2 Space Control 0180 0014 CECTL3 EMIFA CE3 Space Control 0180 0018 SDCTL EMIFA SDRAM Control 0180 001C SDTIM EMIFA SDRAM Refresh Control 0180 0020 SDEXT EMIFA SDRAM Extension 0180 0024­0180 003C ­ Reserved Reserved 0180 0040 PDTCTL Peripheral Device Transfer (PDT) Control 0180 0044 CESEC1 EMIFA CE1 Space Secondary Control 0180 0048 CESEC0 EMIFA CE0 Space Secondary Control 0180 004C ­ 0180 0050 CESEC2 EMIFA CE2 Space Secondary Control 0180 0054 CESEC3 EMIFA CE3 Space Secondary Control 0180 0058­0183 FFFF ­ Reserved Reserved Table 1-5. EMIFB Registers HEX ADDRESS ACRONYM 01A8 0000 GBLCTL EMIFB Global Control 01A8 0004 CECTL1 EMIFB CE1 Space Control 01A8 0008 CECTL0 EMIFB CE0 Space Control 01A8 000C ­ 01A8 0010 CECTL2 EMIFB CE2 Space Control 01A8 0014 CECTL3 EMIFB CE3 Space Control 01A8 0018 SDCTL EMIFB SDRAM Control 01A8 001C SDTIM EMIFB SDRAM Refresh Control 01A8 0020 SDEXT EMIFB SDRAM Extension 01A8 0024­01A8 003C ­ 01A8 0040 PDTCTL Peripheral Device Transfer (PDT) Control 01A8 0044 CESEC1 EMIFB CE1 Space Secondary Control 01A8 0048 CESEC0 EMIFB CE0 Space Secondary Control 01A8 004C ­ 01A8 0050 CESEC2 EMIFB CE2 Space Secondary Control 01A8 0054 CESEC3 EMIFB CE3 Space Secondary Control 01A8 0058­01AB FFFF ­ Submit Documentation Feedback REGISTER NAME Reserved Reserved Reserved Reserved Introduction 11 SM320C6414-EP SM320C6414-EP, SM320C6415-EP SM320C6415-EP, SM320C6416-EP SM320C6416-EP FIXED-POINT DIGITAL SIGNAL PROCESSORS SGUS043D SGUS043D ­ MAY 2003 ­ REVISED SEPTEMBER 2008 www.ti.com Table 1-6. L2 Cache Registers HEX ADDRESS ACRONYM 0184 0000 CCFG REGISTER NAME Cache Configuration 0184 0004­0184 0FFC ­ 0184 1000 EDMAWEIGHT Reserved 0184 1004­0184 1FFC ­ 0184 2000 L2ALLOC0 L2 Allocation 0 0184 2004 L2ALLOC1 L2 Allocation 1 0184 2008 L2ALLOC2 L2 Allocation 2 0184 200C L2ALLOC3 L2 Allocation 3 L2 EDMA Access Control Reserved 0184 2010­0184 3FFC ­ 0184 4000 L2FBAR Reserved L2 Flush Base Address Register 0184 4004 L2FWC L2 Flush Word Count 0184 4010 L2CBAR L2 Clean Base Address Register 0184 4014 L2CWC L2 Clean Word Count 0184 4020 L1PFBAR L1P Flush Base Address Register 0184 4024 L1PFWC L1P Flush Word Count 0184 4030 L1DFBAR L1D Flush Base Address Register 0184 4034 L1DFWC L1D Flush Word Count 0184 4038­0184 4FFC ­ Reserved 0184 5000 L2FLUSH L2 Flush 0184 5004 L2CLEAN L2 Clean 0184 5008­0184 7FFC ­ Reserved 0184 8000­0184 817C MAR0 to MAR95 MAR95 Reserved 0184 8180 MAR96 MAR96 Controls EMIFB CE0 range 6000 0000­60FF FFFF 0184 8184 MAR97 MAR97 Controls EMIFB CE0 range 6100 0000­61FF FFFF 0184 8188 MAR98 MAR98 Controls EMIFB CE0 range 6200 0000­62FF FFFF 0184 818C MAR99 MAR99 Controls EMIFB CE0 range 6300 0000­63FF FFFF 0184 8190 MAR100 MAR100 Controls EMIFB CE1 range 6400 0000­64FF FFFF 0184 8194 MAR101 MAR101 Controls EMIFB CE1 range 6500 0000­65FF FFFF 0184 8198 MAR102 MAR102 Controls EMIFB CE1 range 6600 0000­66FF FFFF 0184 819C MAR103 MAR103 Controls EMIFB CE1 range 6700 0000­67FF FFFF 0184 81A0 MAR104 MAR104 Controls EMIFB CE2 range 6800 0000­68FF FFFF 0184 81A4 MAR105 MAR105 Controls EMIFB CE2 range 6900 0000­69FF FFFF 0184 81A8 MAR106 MAR106 Controls EMIFB CE2 range 6A00 0000­6AFF FFFF 0184 81AC MAR107 MAR107 Controls EMIFB CE2 range 6B00 0000­6BFF FFFF 0184 81B0 MAR108 MAR108 Controls EMIFB CE3 range 6C00 0000­6CFF FFFF 0184 81B4 MAR109 MAR109 Controls EMIFB CE3 range 6D00 0000­6DFF FFFF 0184 81B8 MAR110 MAR110 Controls EMIFB CE3 range 6E00 0000­6EFF FFFF 0184 81BC MAR111 MAR111 Controls EMIFB CE3 range 6F00 0000­6FFF FFFF 0184 81C0­0184 81FC MAR112 MAR112 to MAR127 MAR127 0184 8200 MAR128 MAR128 Controls EMIFA CE0 range 8000 0000­80FF FFFF 0184 8204 MAR129 MAR129 Controls EMIFA CE0 range 8100 0000­81FF FFFF Reserved 0184 8208 Controls EMIFA CE0 range 8200 0000­82FF FFFF MAR131 MAR131 Controls EMIFA CE0 range 8300 0000­83FF FFFF 0184 8210 MAR132 MAR132 Controls EMIFA CE0 range 8400 0000­84FF FFFF 0184 8214 MAR133 MAR133 Controls EMIFA CE0 range 8500 0000­85FF FFFF 0184 8218 12 MAR130 MAR130 0184 820C MAR134 MAR134 Controls EMIFA CE0 range 8600 0000­86FF FFFF Introduction Submit Documentation Feedback SM320C6414-EP SM320C6414-EP, SM320C6415-EP SM320C6415-EP, SM320C6416-EP SM320C6416-EP FIXED-POINT DIGITAL SIGNAL PROCESSORS www.ti.com SGUS043D SGUS043D ­ MAY 2003 ­ REVISED SEPTEMBER 2008 Table 1-6. L2 Cache Registers (continued) HEX ADDRESS ACRONYM 0184 821C MAR135 MAR135 Controls EMIFA CE0 range 8700 0000­87FF FFFF REGISTER NAME 0184 8220 MAR136 MAR136 Controls EMIFA CE0 range 8800 0000­88FF FFFF 0184 8224 MAR137 MAR137 Controls EMIFA CE0 range 8900 0000­89FF FFFF 0184 8228 MAR138 MAR138 Controls EMIFA CE0 range 8A00 0000­8AFF FFFF 0184 822C MAR139 MAR139 Controls EMIFA CE0 range 8B00 0000­8BFF FFFF 0184 8230 MAR140 MAR140 Controls EMIFA CE0 range 8C00 0000­8CFF FFFF 0184 8234 MAR141 MAR141 Controls EMIFA CE0 range 8D00 0000­8DFF FFFF 0184 8238 MAR142 MAR142 Controls EMIFA CE0 range 8E00 0000­8EFF FFFF 0184 823C MAR143 MAR143 Controls EMIFA CE0 range 8F00 0000­8FFF FFFF 0184 8240 MAR144 MAR144 Controls EMIFA CE1 range 9000 0000­90FF FFFF 0184 8244 MAR145 MAR145 Controls EMIFA CE1 range 9100 0000­91FF FFFF 0184 8248 MAR146 MAR146 Controls EMIFA CE1 range 9200 0000­92FF FFFF 0184 824C MAR147 MAR147 Controls EMIFA CE1 range 9300 0000­93FF FFFF 0184 8250 MAR148 MAR148 Controls EMIFA CE1 range 9400 0000­94FF FFFF 0184 8254 MAR149 MAR149 Controls EMIFA CE1 range 9500 0000­95FF FFFF 0184 8258 MAR150 MAR150 Controls EMIFA CE1 range 9600 0000­96FF FFFF 0184 825C MAR151 MAR151 Controls EMIFA CE1 range 9700 0000­97FF FFFF 0184 8260 MAR152 MAR152 Controls EMIFA CE1 range 9800 0000­98FF FFFF 0184 8264 MAR153 MAR153 Controls EMIFA CE1 range 9900 0000­99FF FFFF 0184 8268 MAR154 MAR154 Controls EMIFA CE1 range 9A00 0000­9AFF FFFF 0184 826C MAR155 MAR155 Controls EMIFA CE1 range 9B00 0000­9BFF FFFF 0184 8270 MAR156 MAR156 Controls EMIFA CE1 range 9C00 0000­9CFF FFFF 0184 8274 MAR157 MAR157 Controls EMIFA CE1 range 9D00 0000­9DFF FFFF 0184 8278 MAR158 MAR158 Controls EMIFA CE1 range 9E00 0000­9EFF FFFF 0184 827C MAR159 MAR159 Controls EMIFA CE1 range 9F00 0000­9FFF FFFF 0184 8280 MAR160 MAR160 Controls EMIFA CE2 range A000 0000­A0FF FFFF 0184 8284 MAR161 MAR161 Controls EMIFA CE2 range A100 0000­A1FF FFFF 0184 8288 MAR162 MAR162 Controls EMIFA CE2 range A200 0000­A2FF FFFF 0184 828C MAR163 MAR163 Controls EMIFA CE2 range A300 0000­A3FF FFFF 0184 8290 MAR164 MAR164 Controls EMIFA CE2 range A400 0000­A4FF FFFF 0184 8294 MAR165 MAR165 Controls EMIFA CE2 range A500 0000­A5FF FFFF 0184 8298 MAR166 MAR166 Controls EMIFA CE2 range A600 0000­A6FF FFFF 0184 829C MAR167 MAR167 Controls EMIFA CE2 range A700 0000­A7FF FFFF 0184 82A0 MAR168 MAR168 Controls EMIFA CE2 range A800 0000­A8FF FFFF 0184 82A4 MAR169 MAR169 Controls EMIFA CE2 range A900 0000­A9FF FFFF 0184 82A8 MAR170 MAR170 Controls EMIFA CE2 range AA00 0000­AAFF FFFF 0184 82AC MAR171 MAR171 Controls EMIFA CE2 range AB00 0000­ABFF FFFF 0184 82B0 MAR172 MAR172 Controls EMIFA CE2 range AC00 0000­ACFF FFFF 0184 82B4 MAR173 MAR173 Controls EMIFA CE2 range AD00 0000­ADFF FFFF 0184 82B8 MAR174 MAR174 Controls EMIFA CE2 range AE00 0000­AEFF FFFF 0184 82BC MAR175 MAR175 Controls EMIFA CE2 range AF00 B000­AFFF FFFF 0184 82A0 MAR176 MAR176 Controls EMIFA CE3 range B000 0000­B0FF FFFF 0184 82C4 MAR177 MAR177 Controls EMIFA CE3 range B100 0000­B1FF FFFF 0184 82C8 MAR178 MAR178 Controls EMIFA CE3 range B200 0000­B2FF FFFF 0184 82CC MAR179 MAR179 Controls EMIFA CE3 range B300 0000­B3FF FFFF 0184 82D0 MAR180 MAR180 Controls EMIFA CE3 range B400 0000­B4FF FFFF 0184 82D4 MAR181 MAR181 Controls EMIFA CE3 range B500 0000­B5FF FFFF Submit Documentation Feedback Introduction 13 SM320C6414-EP SM320C6414-EP, SM320C6415-EP SM320C6415-EP, SM320C6416-EP SM320C6416-EP FIXED-POINT DIGITAL SIGNAL PROCESSORS SGUS043D SGUS043D ­ MAY 2003 ­ REVISED SEPTEMBER 2008 www.ti.com Table 1-6. L2 Cache Registers (continued) HEX ADDRESS ACRONYM 0184 82D8 MAR182 MAR182 Controls EMIFA CE3 range B600 0000­B6FF FFFF REGISTER NAME 0184 82DC MAR183 MAR183 Controls EMIFA CE3 range B700 B000­B7FF FFFF 0184 82E0 MAR184 MAR184 Controls EMIFA CE3 range B800 0000­B8FF FFFF 0184 82E4 MAR185 MAR185 Controls EMIFA CE3 range B900 0000­B9FF FFFF 0184 82E8 MAR186 MAR186 Controls EMIFA CE3 range BA00 0000­BAFF FFFF 0184 82EC MAR187 MAR187 Controls EMIFA CE3 range BB00 0000­BBFF FFFF 0184 82F0 MAR188 MAR188 Controls EMIFA CE3 range BC00 0000­BCFF FFFF 0184 82F4 MAR189 MAR189 Controls EMIFA CE3 range BD00 0000­BDFF FFFF 0184 82F8 MAR190 MAR190 Controls EMIFA CE3 range BE00 0000­BEFF FFFF Controls EMIFA CE3 range BF00 B000­BDFF FFFF 0184 82FC MAR191 MAR191 0184 8300­0184 83FC MAR192 MAR192 to MAR255 MAR255 Reserved 0184 8400­0187 FFFF ­ Reserved Table 1-7. EDMA Registers HEX ADDRESS ACRONYM 01A0 FF9C EPRH Event Polarity High Register REGISTER NAME 01A0 FFA4 CIPRH Channel Interrupt Pending High Register 01A0 FFA8 CIERH Channel Interrupt Enable High Register 01A0 FFAC CCERH Channel Chain Enable High Register 01A0 FFB0 ERH 01A0 FFB4 EERH Event High Register Event Enable High Register 01A0 FFB8 ECRH Event Clear High Register 01A0 FFBC ESRH Event Set High Register 01A0 FFC0 PQAR0 Priority Queue Allocation Register 0 01A0 FFC4 PQAR1 Priority Queue Allocation Register 1 01A0 FFC8 PQAR2 Priority Queue Allocation Register 2 01A0 FFCC PQAR3 Priority Queue Allocation Register 3 01A0 FFDC EPRL Event Polarity Low Register 01A0 FFE0 PQSR Priority Queue Status Register 01A0 FFE4 CIPRL Channel Interrupt Pending Low Register 01A0 FFE8 CIERL Channel Interrupt Enable Low Register 01A0 FFEC CCERL Channel Chain Enable Low Register 01A0 FFF0 ERL 01A0 FFF4 EERL Event Low Register Event Enable Low Register 01A0 FFF8 ECRL Event Clear Low Register 01A0 FFFC ESRL Event Set Low Register 01A1 0000­01A3 FFFF ­ Reserved Table 1-8. EDMA Parameter RAM (1) HEX ADDRESS REGISTER NAME 01A0 0000­01A0 0017 Parameters for Event 0 (6 words) 01A0 0018­01A0 002F Parameters for Event 1 (6 words) 01A0 0030­01A0 0047 Parameters for Event 2 (6 words) 01A0 0048­01A0 005F 14 Parameters for Event 4 (6 words) 01A0 0078­01A0 008F (1) Parameters for Event 3 (6 words) 01A0 0060-01A0 0060-01A0 0077 Parameters for Event 5 (6 words) The C64x device has 21 parameter sets (6 words each) that can be used to reload/link EDMA transfers. Introduction Submit Documentation Feedback SM320C6414-EP SM320C6414-EP, SM320C6415-EP SM320C6415-EP, SM320C6416-EP SM320C6416-EP FIXED-POINT DIGITAL SIGNAL PROCESSORS www.ti.com SGUS043D SGUS043D ­ MAY 2003 ­ REVISED SEPTEMBER 2008 Table 1-8. EDMA Parameter RAM (continued) HEX ADDRESS REGISTER NAME 01A0 0090­01A0 00A7 Parameters for Event 6 (6 words) 01A0 00A8­01A0 00BF Parameters for Event 7 (6 words) 01A0 00C0­01A0 00D7 Parameters for Event 8 (6 words) 01A0 00D8­01A0 00EF Parameters for Event 9 (6 words) 01A0 00F0­01A0 00107 Parameters for Event 10 (6 words) 01A0 0108­01A0 011F Parameters for Event 11 (6 words) 01A0 0120­01A0 0137 Parameters for Event 12 (6 words) 01A0 0138­01A0 014F Parameters for Event 13 (6 words) 01A0 0150­01A0 0167 Parameters for Event 14 (6 words) 01A0 0168­01A0 017F Parameters for Event 15 (6 words) 01A0 0150­01A0 0167 Parameters for Event 16 (6 words) 01A0 0168­01A0 017F Parameters for Event 17 (6 words) . . . . 01A0 05D0­01A0 05E7 Parameters for Event 62 (6 words) 01A0 05E8­01A0 05FF Parameters for Event 63 (6 words) 01A0 0600­01A0 0617 Reload/link parameters for Event M (6 words) 01A0 0618­01A0 062F Reload/link parameters for Event N (6 words) . . 01A0 07E0­01A0 07F7 Reload/link parameters for Event Z (6 words) 01A0 07F8­01A0 07FF Scratch pad area (2 words) Table 1-9. Quick DMA (QDMA) and Pseudo Registers HEX ADDRESS ACRONYM 0200 0000 QOPT QDMA Options Parameter REGISTER NAME 0200 0004 QSRC QDMA Source Address 0200 0008 QCNT QDMA Frame Count 0200 000C QDST QDMA Destination Address 0200 0010 QIDX QDMA Index 0200 0014­0200 001C Reserved 0200 0020 QSOPT QDMA Pseudo Options 0200 0024 QSSRC QDMA Pseudo Source Address 0200 0028 QSCNT QDMA Pseudo Frame Count 0200 002C QSDST QDMA Pseudo Destination Address 0200 0030 QSIDX QDMA Pseudo Index Submit Documentation Feedback Introduction 15 SM320C6414-EP SM320C6414-EP, SM320C6415-EP SM320C6415-EP, SM320C6416-EP SM320C6416-EP FIXED-POINT DIGITAL SIGNAL PROCESSORS SGUS043D SGUS043D ­ MAY 2003 ­ REVISED SEPTEMBER 2008 www.ti.com Table 1-10. Interrupt Selector Registers HEX ADDRESS ACRONYM REGISTER NAME COMMENTS 019C 0000 MUXH Interrupt Multiplexer High Selects which interrupts drive CPU interrupts 10­15 (INT10 INT10­INT15 INT15) 019C 0004 MUXL Interrupt Multiplexer Low Selects which interrupts drive CPU interrupts 4­9 (INT04 INT04­INT09 INT09) 019C 0008 EXTPOL External Interrupt Polarity Sets the polarity of the external interrupts (EXT_INT4­EXT_INT7) 019C 000C­019C 01FF ­ Reserved Table 1-11. Peripheral Power-Down Control Register HEX ADDRESS ACRONYM 019C 0200 PDCTL 019C 0204­019F FFFF REGISTER NAME Peripheral Power-Down Control Reserved Table 1-12. McBSP 0 Registers HEX ADDRESS ACRONYM REGISTER NAME 018C 0000 DRR0 McBSP0 Data Receive Register via configuration bus 0x3000 0000­0x33FF FFFF DRR0 McBSP0 Data Receive Register via peripheral bus 018C 0004 DXR0 McBSP0 Data Transmit Register via configuration bus 0x3000 0000­0x33FF FFFF DXR0 McBSP0 Data Transmit Register via peripheral bus 018C 0008 SPCR0 018C 000C RCR0 McBSP0 Receive Control Register 018C 0010 XCR0 McBSP0 Transmit Control Register 018C 0014 SRGR0 COMMENTS McBSP0 Sample Rate Generator Register McBSP0 Multichannel Control Register The CPU and EDMA controller can only read this register; they cannot write to it. McBSP0 Serial Port Control Register 018C 0018 MCR0 018C 001C RCERE00 RCERE00 McBSP0 Enhanced Receive Channel Enable Register 0 018C 0020 XCERE00 XCERE00 McBSP0 Enhanced Transmit Channel Enable Register 0 018C 0024 PCR0 018C 0028 RCERE10 RCERE10 McBSP0 Pin Control Register McBSP0 Enhanced Receive Channel Enable Register 1 018C 002C XCERE10 XCERE10 McBSP0 Enhanced Transmit Channel Enable Register 1 018C 0030 RCERE20 RCERE20 McBSP0 Enhanced Receive Channel Enable Register 2 018C 0034 XCERE20 XCERE20 McBSP0 Enhanced Transmit Channel Enable Register 2 018C 0038 RCERE30 RCERE30 McBSP0 Enhanced Receive Channel Enable Register 3 018C 003C XCERE30 XCERE30 McBSP0 Enhanced Transmit Channel Enable Register 3 018C 0040­018F FFFF ­ Reserved Table 1-13. McBSP 1 Registers HEX ADDRESS 018C 0000 DRR1 McBSP1 Data Receive Register via configuration bus 0x3400 0000­0x37FF FFFF DRR1 McBSP1 Data Receive Register via peripheral bus 019C 0004 16 ACRONYM DXR1 McBSP1 Data Transmit Register via configuration bus Introduction REGISTER NAME COMMENTS The CPU and EDMA controller can only read this register; they cannot write to it. Submit Documentation Feedback SM320C6414-EP SM320C6414-EP, SM320C6415-EP SM320C6415-EP, SM320C6416-EP SM320C6416-EP FIXED-POINT DIGITAL SIGNAL PROCESSORS www.ti.com SGUS043D SGUS043D ­ MAY 2003 ­ REVISED SEPTEMBER 2008 Table 1-13. McBSP 1 Registers (continued) HEX ADDRESS ACRONYM 0x3400 0000­0x37FF FFFF DXR1 REGISTER NAME COMMENTS McBSP1 Data Transmit Register via peripheral bus 019C 0008 SPCR1 019C 000C RCR1 McBSP1 Serial Port Control Register McBSP1 Receive Control Register 019C 0010 XCR1 McBSP1 Transmit Control Register 019C 0014 SRGR1 019C 0018 MCR1 019C 001C RCERE01 RCERE01 McBSP1 Enhanced Receive Channel Enable Register 0 019C 0020 XCERE01 XCERE01 McBSP1 Enhanced Transmit Channel Enable Register 0 019C 0024 PCR1 019C 0028 RCERE11 RCERE11 McBSP1 Enhanced Receive Channel Enable Register 1 019C 002C XCERE11 XCERE11 McBSP1 Enhanced Transmit Channel Enable Register 1 019C 0030 RCERE21 RCERE21 McBSP1 Enhanced Receive Channel Enable Register 2 019C 0034 XCERE21 XCERE21 McBSP1 Enhanced Transmit Channel Enable Register 2 019C 0038 RCERE31 RCERE31 McBSP1 Enhanced Receive Channel Enable Register 3 019C 003C XCERE31 XCERE31 McBSP1 Enhanced Transmit Channel Enable Register 3 019C 0040­0193 FFFF ­ McBSP1 Sample Rate Generator Register McBSP1 Multichannel Control Register McBSP1 Pin Control Register Reserved Table 1-14. McBSP 2 Registers HEX ADDRESS ACRONYM REGISTER NAME 01A4 0000 DRR2 McBSP2 Data Receive Register via configuration bus 0x3800 0000­0x3BFF FFFF DRR2 McBSP2 Data Receive Register via peripheral bus 01A4 0004 DXR2 McBSP2 Data Transmit Register via configuration bus 0x3800 0000­0x3BFF FFFF DXR2 COMMENTS The CPU and EDMA controller can only read this register; they cannot write to it. McBSP2 Data Transmit Register via peripheral bus 01A4 0008 SPCR2 01A4 000C RCR2 McBSP2 Serial Port Control Register McBSP2 Receive Control Register 01A4 0010 XCR2 McBSP2 Transmit Control Register 01A4 0014 SRGR2 01A4 0018 MCR2 01A4 001C RCERE02 RCERE02 McBSP2 Enhanced Receive Channel Enable Register 0 01A4 0020 XCERE02 XCERE02 McBSP2 Enhanced Transmit Channel Enable Register 0 McBSP2 Sample Rate Generator Register McBSP2 Multichannel Control Register 01A4 0024 PCR2 01A4 0028 RCERE12 RCERE12 McBSP2 Enhanced Receive Channel Enable Register 1 01A4 002C XCERE12 XCERE12 McBSP2 Enhanced Transmit Channel Enable Register 1 01A4 0030 RCERE22 RCERE22 McBSP2 Enhanced Receive Channel Enable Register 2 01A4 0034 XCERE22 XCERE22 McBSP2 Enhanced Transmit Channel Enable Register 2 01A4 0038 RCERE32 RCERE32 McBSP2 Enhanced Receive Channel Enable Register 3 01A4 003C XCERE32 XCERE32 McBSP2 Enhanced Transmit Channel Enable Register 3 01A4 0040­01A7 FFFF ­ Submit Documentation Feedback McBSP2 Pin Control Register Reserved Introduction 17 SM320C6414-EP SM320C6414-EP, SM320C6415-EP SM320C6415-EP, SM320C6416-EP SM320C6416-EP FIXED-POINT DIGITAL SIGNAL PROCESSORS SGUS043D SGUS043D ­ MAY 2003 ­ REVISED SEPTEMBER 2008 www.ti.com Table 1-15. Timer 0 Registers HEX ADDRESS ACRONYM REGISTER NAME COMMENTS 0194 0000 CTL0 Timer 0 Control Determines the operating mode of the timer, monitors the timer status, and controls the function of the TOUT pin 0194 0004 PRD0 Timer 0 Period Contains the number of timer input clock cycles to count. This number controls the TSTAT signal frequency. 0194 0008 CNT0 Timer 0 Counter Contains the current value of the incrementing counter 0194 000C­0197 FFFF ­ Reserved Table 1-16. Timer 1 Registers HEX ADDRESS ACRONYM REGISTER NAME COMMENTS Determines the operating mode of the timer, monitors the timer status, and controls the function of the TOUT pin 0198 0000 CTL1 Timer 1 Control 0198 0004 PRD1 Timer 1 Period Contains the number of timer input clock cycles to count. This number controls the TSTAT signal frequency. 0198 0008 CNT1 Timer 1 Counter Contains the current value of the incrementing counter 0198 000C­019B FFFF ­ Reserved Table 1-17. Timer 2 Registers HEX ADDRESS ACRONYM REGISTER NAME COMMENTS 01AC 0000 CTL2 Timer 2 Control Determines the operating mode of the timer, monitors the timer status, and controls the function of the TOUT pin 01AC 0004 PRD2 Timer 2 Period Contains the number of timer input clock cycles to count. This number controls the TSTAT signal frequency. 01AC 0008 CNT2 Timer 2 Counter Contains the current value of the incrementing counter 01AC 000C­01AF FFFF ­ Reserved Table 1-18. HPI Registers HEX ADDRESS ACRONYM ­ HPID HPI Data Host read/write access only 0188 0000 HPIC HPI Control HPIC has both host/CPU read/write access. 0188 0004 HPIA (HPIAW) (1) HPI Address (Write) 0188 0008 HPIA (HPIAR) (1) HPI Address (Read) 0188 000C­0189 FFFF ­ 018A 0000 TRCTL 018A 0004­018B FFFF ­ (1) REGISTER NAME COMMENTS HPIA has both host/CPU read/write access. Reserved HPI Transfer Request Control Reserved Host access to the HPIA register updates both the HPIAW and HPIAR registers. The CPU can access HPIAW and HPIAR independently. Table 1-19. GPIO Registers HEX ADDRESS ACRONYM REGISTER NAME 01B0 0000 GPEN GPIO Enable 01B0 0004 GPDIR GPIO Direction 01B0 0008 GPVAL GPIO Value 01B0 000C GPDH GPIO Delta High 01B0 0014 GPHM GPIO High Mask 01B0 0018 GPDL GPIO Delta Low 01B0 001C 18 ­ 01B0 0010 GPLM GPIO Low Mask Introduction Reserved Submit Documentation Feedback SM320C6414-EP SM320C6414-EP, SM320C6415-EP SM320C6415-EP, SM320C6416-EP SM320C6416-EP FIXED-POINT DIGITAL SIGNAL PROCESSORS www.ti.com SGUS043D SGUS043D ­ MAY 2003 ­ REVISED SEPTEMBER 2008 Table 1-19. GPIO Registers (continued) HEX ADDRESS ACRONYM 01B0 0020 GPGC GPIO Global Control REGISTER NAME 01B0 0024 GPPOL GPIO Interrupt Polarity 01B0 0028­01B0 01FF ­ 01B0 0200 DEVICE_REV 01B0 0204­01B3 FFFF ­ Reserved Silicon revision identification (For more details, see the device characteristics listed in Table 1-3.) Reserved Table 1-20. PCI Peripheral Registers (C6415 C6415 and C6416 C6416 Only) (1) HEX ADDRESS ACRONYM REGISTER NAME 01C0 0000 RSTSRC 01C0 0004 ­ 01C0 0008 PCIIS PCI Interrupt Source 01C0 000C PCIIEN PCI Interrupt Enable 01C0 0010 DSPMA DSP Master Address 01C0 0014 PCIMA PCI Master Address 01C0 0018 PCIMC PCI Master Control 01C0 001C CDSPA Current DSP Address 01C0 0020 CPCIA Current PCI Address 01C0 0024 CCNT Current Byte Count DSP Reset Source/Status Reserved 01C0 0028 Reserved ­ Reserved 0x01C1 FFF0 HSR 0x01C1 FFF4 HDCR Host-to-DSP Control Register 0x01C1 FFF8 DSPP DSP Page 0x01C1 FFFC ­ Reserved 01C2 0000 EEADD EEPROM Address 01C2 0004 EEDAT EEPROM Data 01C2 0008 EECTL EEPROM Control 01C2 000C­01C2 FFFF ­ 01C3 0000 TRCTL 01C3 0004­01C3 FFFF (1) ­ 01C0 02C­01C1 FFEF ­ Host Status Register Reserved PCI Transfer Request Control Reserved These PCI registers are not supported on the C6414 C6414 device. Table 1-21. UTOPIA Registers (C6415 C6415 and C6416 C6416 Only) (1) HEX ADDRESS ACRONYM REGISTER NAME 01B4 0000 UCR 01B4 0004 ­ Reserved 01B4 0008 ­ Reserved 01B4 000C UIER UTOPIA Interrupt Enable Register 01B4 0010 UIPR UTOPIA Interrupt Pending Register 01B4 0014 CDR Clock Detect Register UTOPIA Control Register 01B4 0018 Error Interrupt Enable Register EIPR Error Interrupt Pending Register 01B4 0020­01B7 FFFF (1) EIER 01B4 001C ­ Reserved These UTOPIA registers are not supported on the C6414 C6414 device. Submit Documentation Feedback Introduction 19 SM320C6414-EP SM320C6414-EP, SM320C6415-EP SM320C6415-EP, SM320C6416-EP SM320C6416-EP FIXED-POINT DIGITAL SIGNAL PROCESSORS SGUS043D SGUS043D ­ MAY 2003 ­ REVISED SEPTEMBER 2008 www.ti.com Table 1-22. UTOPIA Queue Registers (C6415 C6415 and C6416 C6416 Only) (1) HEX ADDRESS URQ UTOPIA Receive Queue 3D00 0000 UXQ UTOPIA Transmit Queue 3D00 0004­3FFF FFFF (1) ACRONYM 3C00 0000 REGISTER NAME ­ Reserved These UTOPIA registers are not supported on the C6414 C6414 device. Table 1-23. VCP Registers (C6414 C6414 Only) HEX ADDRESS ACRONYM REGISTER EDMA BUS PERIPHERAL BUS 5000 0000 01B8 0000 VCPIC0 VCP Input Configuration 0 5000 0004 01B8 0004 VCPIC1 VCP Input Configuration 1 5000 0008 01B8 0008 VCPIC2 VCP Input Configuration 2 5000 000C 01B8 000C VCPIC3 VCP Input Configuration 3 5000 0010 01B8 0010 VCPIC4 VCP Input Configuration 4 5000 0014 01B8 0014 VCPIC5 VCP Input Configuration 5 5000 0040 01B8 0024 VCPOUT0 VCP Output 0 5000 0044 01B8 0028 VCPOUT1 VCP Output 1 5000 0080 ­ VCPWBM VCP Write Branch Metrics 5000 0088 ­ VCPRDECS ­ 01B8 0018 VCPEXE VCP Execution ­ 01B8 0020 VCPEND VCP Endian ­ 01B8 0040 VCPSTAT0 VCP Status Register 0 ­ 01B8 0044 VCPSTAT1 VCP Status Register 1 ­ 01B8 0050 VCPERR VCP Read Decisions VCP Error Table 1-24. TCP Registers (C6414 C6414 Only) HEX ADDRESS ACRONYM REGISTER EDMA BUS PERIPHERAL BUS 5800 0000 01BA 0000 TCPIC0 TCP Input Configuration 0 5800 0004 01BA 0004 TCPIC1 TCP Input Configuration 1 5800 0008 01BA 0008 TCPIC2 TCP Input Configuration 2 5800 000C 01BA 000C TCPIC3 TCP Input Configuration 3 5800 0010 01BA 0010 TCPIC4 TCP Input Configuration 4 5800 0014 01BA 0014 TCPIC5 TCP Input Configuration 5 5800 0018 01BA 0018 TCPIC6 TCP Input Configuration 6 5800 001C 01BA 001C TCPIC7 TCP Input Configuration 7 5800 0020 01BA 0020 TCPIC8 TCP Input Configuration 8 5800 0024 01BA 0024 TCPIC9 TCP Input Configuration 9 5800 0028 01BA 0028 TCPIC10 TCPIC10 TCP Input Configuration 10 5800 002C 01BA 002C TCPIC11 TCPIC11 TCP Input Configuration11 5800 0030 01BA 0030 TCPOUT TCP Output Parameters 5802 0000 ­ TCPSP 5804 0000 ­ TCPEXT 5806 0000 ­ TCPAP 5808 0000 ­ TCPINTER TCP Systematics and Parities Memory TCP Extrinsic Memory TCP Apriori Memory TCP Interleaver Memory 580A 0000 20 ­ TCPHD TCP Hard Decisions Memory ­ 01BA 0038 TCPEXE TCP Execution Introduction Submit Documentation Feedback SM320C6414-EP SM320C6414-EP, SM320C6415-EP SM320C6415-EP, SM320C6416-EP SM320C6416-EP FIXED-POINT DIGITAL SIGNAL PROCESSORS www.ti.com SGUS043D SGUS043D ­ MAY 2003 ­ REVISED SEPTEMBER 2008 Table 1-24. TCP Registers (C6414 C6414 Only) (continued) HEX ADDRESS EDMA BUS PERIPHERAL BUS ­ 01BA 0040 ­ ­ ACRONYM REGISTER TCPEND TCP Endian 01BA 0050 TCPERR TCP Error 01BA 0058 TCPSTAT TCP Status 1.4.7 EDMA Channel Synchronization Events The C64x EDMA supports up to 64 EDMA channels that service peripheral devices and external memory. Table 1-25 lists the source of C64x EDMA synchronization events associated with each of the programmable EDMA channels. For the C64x device, the association of an event to a channel is fixed; each of the EDMA channels has one specific event associated with it. These specific events are captured in the EDMA event registers (ERL, ERH), even if the events are disabled by the EDMA event enable registers (EERL, EERH). The priority of each event can be specified independently in the transfer parameters stored in the EDMA parameter RAM. For more detailed information on the EDMA module and how EDMA events are enabled, captured, processed, linked, chained, and cleared, etc., see the EDMA Controller chapter of the TMS320C6000 TMS320C6000 Peripherals Reference Guide (literature number SPRU190 SPRU190). Table 1-25. SM320C64x EDMA Channel Synchronization Events (1) EDMA CHANNEL EVENT NAME 0 DSP_INT 1 TINT0 Timer 0 interrupt 2 TINT1 Timer 1 interrupt 3 SD_INTA 4 GPINT4/EXT_INT4 GPIO event 4/External interrupt pin 4 5 GPINT5/EXT_INT5 GPIO event 5/External interrupt pin 5 6 GPINT6/EXT_INT6 GPIO event 6/External interrupt pin 6 7 GPINT7/ EXT_INT7 GPIO event 7/External interrupt pin 7 8 GPINT0 GPIO event 0 9 GPINT1 GPIO event 1 10 GPINT2 GPIO event 2 11 GPINT3 GPIO event 3 12 XEVT0 McBSP0 transmit event 13 REVT0 McBSP0 receive event 14 XEVT1 McBSP1 transmit event 15 REVT1 McBSP1 receive event 16 ­ EVENT DESCRIPTION HPI/PCI-to-DSP interrupt (PCI peripheral supported on C6415 C6415 and C6416 C6416 only) (2) EMIFA SDRAM timer interrupt None 17 McBSP2 receive event TINT2 Timer 2 interrupt 20 SD_INTB EMIFB SDRAM timer interrupt 21 ­ Reserved, for future expansion 22­27 ­ None 28 (2) (3) McBSP2 transmit event REVT2 19 (1) XEVT2 18 VCPREVT VCP receive event (C6416 C6416 only) (3) In addition to the events shown in this table, each of the 64 channels can also be synchronized with the transfer completion or alternate transfer completion events. For more detailed information on EDMA event-transfer chaining, see the EDMA Controller chapter of the TMS320C6000 TMS320C6000 Peripherals Reference Guide (SPRU190 SPRU190). The PCI and UTOPIA peripherals are not supported on the C6414 C6414 device; therefore, these EDMA synchronization events are reserved. The VCP/TCP EDMA synchronization events are supported on the C6416 C6416 only. For the C6414 C6414 and C6415 C6415 devices, these events are reserved. Submit Documentation Feedback Introduction 21 SM320C6414-EP SM320C6414-EP, SM320C6415-EP SM320C6415-EP, SM320C6416-EP SM320C6416-EP FIXED-POINT DIGITAL SIGNAL PROCESSORS SGUS043D SGUS043D ­ MAY 2003 ­ REVISED SEPTEMBER 2008 www.ti.com Table 1-25. SM320C64x EDMA Channel Synchronization Events (continued) EDMA CHANNEL EVENT NAME 29 VCPXEVT VCP transmit event (C6416 C6416 only) (3) 30 TCPREVT TCP receive event (C6416 C6416 only) (3) 31 TCPXEVT TCP transmit event (C6416 C6416 only) (3) 32 UREVT 33­39 ­ 40 UXEVT EVENT DESCRIPTION UTOPIA receive event (C6415 C6415 and C6416 C6416 only) (2) None UTOPIA transmit event (C6415 C6415 and C6416 C6416 only) (2) 41­47 GPINT8 GPIO event 8 49 GPINT9 GPIO event 9 50 GPINT10 GPINT10 GPIO event 10 51 GPINT11 GPINT11 GPIO event 11 52 GPINT12 GPINT12 GPIO event 12 53 GPINT13 GPINT13 GPIO event 13 54 GPINT14 GPINT14 GPIO event 14 55 GPINT15 GPINT15 GPIO event 15 56­63 22 ­ 48 ­ Introduction None None Submit Documentation Feedback SM320C6414-EP SM320C6414-EP, SM320C6415-EP SM320C6415-EP, SM320C6416-EP SM320C6416-EP FIXED-POINT DIGITAL SIGNAL PROCESSORS www.ti.com SGUS043D SGUS043D ­ MAY 2003 ­ REVISED SEPTEMBER 2008 1.4.8 Interrupt Sources and Interrupt Selector The C64x DSP core supports 16 prioritized interrupts, which are listed in Table 1-26. The highest-priority interrupt is INT_00 (dedicated to RESET), while the lowest-priority interrupt is INT_15. The first four interrupts (INT_00­INT_03) are nonmaskable and fixed. The remaining interrupts (INT_04­INT_15) are maskable and default to the interrupt source specified in Table 1-26. The interrupt source for interrupts 4­15 can be programmed by modifying the selector value (binary value) in the corresponding fields of the interrupt selector control registers; MUXH (address 0x019C0000) and MUXL (address 0x019C0004). Table 1-26. C64x DSP Interrupts CPU INTERRUPT NUMBER INTERRUPT SELECTOR CONTROL REGISTER SELECTOR VALUE (BINARY) INTERRUPT EVENT INT_00 (1) ­ ­ RESET (1) ­ ­ NMI INT_02 (1) ­ ­ Reserved Reserved. Do not use. INT_03 (1) ­ Reserved GPIO interrupt 4/external interrupt 4 INT_01 INTERRUPT SOURCE (2) MUXL[4:0] 00100 GPINT4/EXT_INT4 GPIO interrupt 5/external interrupt 5 INT_05 (2) MUXL[9:5] 00101 GPINT5/EXT_INT5 TCP interrupt (C6416 C6416 only) INT_06 (2) MUXL[14:10] 00110 GPINT6/EXT_INT6 GPIO interrupt 6/external interrupt 6 INT_07 (2) MUXL[20:16] 00111 GPINT7/EXT_INT7 GPIO interrupt 7/external interrupt 7 (2) MUXL[25:21] 01000 EDMA_INT INT_09 (2) MUXL[30:26] 01001 EMU_DTDMA INT_10 (2) MUXH[4:0] 00011 SD_INTA INT_04 INT_08 INT_11 (2) EDMA channel (0­63) interrupt EMU DTDMA EMIFA SDRAM timer interrupt 01010 EMU_RTDXRX EMU real-time data exchange (RTDX) receive MUXH[14:10] 01011 EMU_RTDXTX EMU RTDX transmit INT_13 (2) MUXH[20:16] 00000 DSP_INT INT_14 (2) MUXH[25:21] 00001 TINT0 Timer 0 interrupt INT_15 (2) MUXH[30:26] 00010 TINT1 Timer 1 interrupt ­ ­ 01100 XINT0 McBSP0 transmit interrupt ­ ­ 01101 RINT0 McBSP0 receive interrupt ­ ­ 01110 XINT1 McBSP1 transmit interrupt ­ ­ 01111 RINT1 McBSP1 receive interrupt ­ ­ 10000 GPINT0 ­ ­ 10001 XINT2 McBSP2 transmit interrupt ­ ­ 10010 RINT2 McBSP2 receive interrupt ­ ­ 10011 TINT2 Timer 2 interrupt ­ ­ 10100 SD_INTB EMIFB SDRAM timer interrupt ­ ­ 10101 Reserved Reserved. Do not use. ­ ­ 10110 Reserved Reserved. Do not use. ­ ­ 10111 UINT ­ ­ 11000­11101 Reserved Reserved. Do not use. ­ ­ 11110 VCPINT VCP interrupt (C6416 C6416 only) ­ (1) (2) MUXH[9:5] INT_12 (2) ­ 11111 TCPINT TCP interrupt (C6416 C6416 only) HPI/PCI-to-DSP interrupt (PCI supported on C6415 C6415 and C6416 C6416 only) GPIO interrupt 0 UTOPIA interrupt (C6415/C6416 C6415/C6416 only) Interrupts INT_00­INT_03 are nonmaskable and fixed. Interrupts INT_04­INT_15 are programmable by modifying the binary selector values in the Interrupt Selector Control registers fields. Table 1-26 shows the default interrupt sources for interrupts INT_04­INT_15. For more detailed information on interrupt sources and selection, see the Interrupt Selector and External Interrupts chapter of the TMS320C6000 TMS320C6000 Peripherals Reference Guide (SPRU190 SPRU190). Submit Documentation Feedback Introduction 23 SM320C6414-EP SM320C6414-EP, SM320C6415-EP SM320C6415-EP, SM320C6416-EP SM320C6416-EP FIXED-POINT DIGITAL SIGNAL PROCESSORS SGUS043D SGUS043D ­ MAY 2003 ­ REVISED SEPTEMBER 2008 www.ti.com 1.4.9 Signal Groups Description CLKIN CLKOUT4/GP1 CLKOUT6/GP2 CLKMODE1 CLKMODE0 PLLV TMS TDO TDI TCK TRST EMU0 EMU1 EMU2 EMU3 EMU4 EMU5 EMU6 EMU7 EMU8 EMU9 EMU10 EMU10 EMU11 EMU11 Reset and Interrupts Clock/PLL Reserved IEEE Standard 1149.1 (JTAG) Emulation RESET NMI GP7/EXT_INT7 GP6/EXT_INT6 GP5/EXT_INT5 GP4/EXT_INT4 RSV RSV RSV RSV RSV RSV · · · RSV RSV RSV Peripheral Control/Status PCI_EN MCBSP2_EN Control/Status GP15/PRST GP15/PRST§ GP14/PCLK GP14/PCLK§ GP13/PINTA GP13/PINTA§ GP12/PGNT GP12/PGNT§ GP11/PREQ GP11/PREQ§ GP10/PCBE3 GP10/PCBE3§ GP9/PIDSEL§ CLKS2/GP8 GPIO GP7/EXT_INT7 GP6/EXT_INT6 GP5/EXT_INT5 GP4/EXT_INT4 GP3 CLKOUT6/GP2 CLKOUT4/GP1 GP0 General-Purpose Input/Output (GPIO) Port These pins are MUXed with the GPIO port pins and by default these signals function as clocks (CLKOUT4 or CLKOUT6) or McBSP2 clock source (CLKS2). To use these MUXed pins as GPIO signals, the appropriate GPIO register bits (GPxEN and GPxDIR) must be properly enabled and configured. For more details, see the Device Configurations section of this data sheet. These pins are GPIO pins that can also function as external interrupt sources (EXT_INT[7:4]). Default after reset is EXT_INTx or GPIO as input-only. § For the C6415 C6415 and C6416 C6416 devices, these GPIO pins are MUXed with the PCI peripheral pins. By default, these signals are set up to no function with both the GPIO and PCI pin functions disabled. For more details on these MUXed pins, see the Device Configurations section of this data sheet. For the C6414 C6414 device, the GPIO peripheral pins are not MUXed; the C6414 C6414 device does not support the PCI peripheral. Figure 1-2. CPU and Peripheral Signals 24 Introduction Submit Documentation Feedback SM320C6414-EP SM320C6414-EP, SM320C6415-EP SM320C6415-EP, SM320C6416-EP SM320C6416-EP FIXED-POINT DIGITAL SIGNAL PROCESSORS www.ti.com SGUS043D SGUS043D ­ MAY 2003 ­ REVISED SEPTEMBER 2008 64 Data AED[63:0] ACE3 ACE2 ACE1 ACE0 Memory Map Space Select 20 AEA[22:3] AECLKIN External Memory I/F Control Address ABE7 ABE6 ABE5 ABE4 Byte Enables ABE3 ABE2 ABE1 ABE0 Bus Arbitration AECLKOUT1 AECLKOUT2 ASDCKE AARE/ASDCAS/ASADS/ASRE AAOE/ASDRAS/ASOE AAWE/ASDWE/ASWE AARDY ASOE3 APDT AHOLD AHOLDA ABUSREQ EMIFA (64-bit) 16 Data BED[15:0] BCE3 BCE2 BCE1 BCE0 Memory Map Space Select BECLKIN External Memory I/F Control 20 BEA[20:1] BBE1 BBE0 BSOE3 BPDT Address Byte Enables Bus Arbitration EMIFB (16-bit) BECLKOUT1 BECLKOUT2 BARE/BSDCAS/BSADS/BSRE BAOE/BSDRAS/BSOE BAWE/BSDWE/BSWE BARDY BHOLD BHOLDA BBUSREQ These C64xTM devices have two EMIFs (64-bit EMIFA and 16-bit EMIFB). The prefix "A" in front of a signal name indicates it is an EMIFA signal whereas a prefix "B" in front of a signal name indicates it is an EMIFB signal. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix "A" or "B" may be omitted from the signal name. Figure 1-3. Peripheral Signals (1) Submit Documentation Feedback Introduction 25 SM320C6414-EP SM320C6414-EP, SM320C6415-EP SM320C6415-EP, SM320C6416-EP SM320C6416-EP FIXED-POINT DIGITAL SIGNAL PROCESSORS SGUS043D SGUS043D ­ MAY 2003 ­ REVISED SEPTEMBER 2008 32 www.ti.com Data HD[31:0]/AD[31:0] HCNTL0/PSTOP HCNTL1/PDEVSEL HPI (Host-Port Interface) Register Select Control Half-Word Select HHWIL/PTRDY (HPI16 HPI16 ONLY) HAS/PPAR HR/W/PCBE2 HCS/PPERR HDS1/PSERR HDS2/PCBE1 HRDY/PIRDY HINT/PFRAME 32 HD[31:0]/AD[31:0] GP10/PCBE3 GP10/PCBE3 HR/W/PCBE2 HDS2/PCBE1 PCBE0§ GP12/PGNT GP12/PGNT Data/Address Command Byte Enable Clock Control Arbitration Error GP11/PREQ GP11/PREQ Serial EEPROM PCI Interface (C6415 C6415 and C6416 C6416 Only) GP14/PCLK GP14/PCLK GP9/PIDSEL HCNTL1/PDEVSEL HINT/PFRAME GP13/PINTA GP13/PINTA HAS/PPAR GP15/PRST GP15/PRST HRDY/PIRDY HCNTL0/PSTOP HHWIL/PTRDY HDS1/PSERR HCS/PPERR DX2/XSP_DO XSP_CS§ CLKX2/XSP_CLK DR2/XSP_DI For the C6415 C6415 and C6416 C6416 devices, these HPI pins are MUXed with the PCI peripheral. By default, these signals function as HPI. For more details on these MUXed pins, see the Device Configurations section of this data sheet. For the C6414 C6414 device, these HPI pins are not MUXed; the C6414 C6414 device does not support the PCI peripheral. For the C6415 C6415 and C6416 C6416 devices, these PCI pins (excluding PCBE0 and XSP_CS) are MUXed with the HPI, McBSP2, or GPIO peripherals. By default, these signals function as HPI, McBSP2, and no function, respectively. For more details on these MUXed pins, see the Device Configurations section of this data sheet. For the C6414 C6414 device, the HPI, McBSP2, and GPIO peripheral pins are not MUXed; the C6414 C6414 device does not support the PCI peripheral. § For the C6414 C6414 device, these pins are "Reserved (leave unconnected, do not connect to power or ground)." Figure 1-4. Peripheral Signals (2) 26 Introduction Submit Documentation Feedback SM320C6414-EP SM320C6414-EP, SM320C6415-EP SM320C6415-EP, SM320C6416-EP SM320C6416-EP FIXED-POINT DIGITAL SIGNAL PROCESSORS www.ti.com SGUS043D SGUS043D ­ MAY 2003 ­ REVISED SEPTEMBER 2008 McBSP1 McBSP0 CLKX1/URADDR4 FSX1/UXADDR3 DX1/UXADDR4 Transmit Transmit CLKR1/URADDR2 FSR1/UXADDR2 DR1/UXADDR1 Receive Receive CLKS1/URADDR3 Clock CLKX0 FSX0 DX0 CLKR0 FSR0 DR0 Clock CLKS0 McBSP2 CLKX2/XSP_CLK FSX2 DX2/XSP_DO Transmit CLKR2 FSR2 DR2/XSP_DI Receive CLKS2/GP8 Clock McBSPs (Multichannel Buffered Serial Ports) For the C6415 C6415 and C6416 C6416 devices, these McBSP2 and McBSP1 pins are MUXed with the PCI and UTOPIA peripherals, respectively. By default, these signals function as McBSP2 and McBSP1, respectively. For more details on these MUXed pins, see the Device Configurations section of this data sheet. For the C6414 C6414 device, these McBSP2 and McBSP1 peripheral pins are not MUXed; the C6414 C6414 device does not support PCI and UTOPIA peripherals. The McBSP2 clock source pin (CLKS2, default) is MUXed with the GP8 pin. To use this MUXed pin as the GP8 signal, the appropriate GPIO register bits (GP8EN and GP8DIR) must be properly enabled and configured. For more details, see the Device Configurations section of this data sheet. Figure 1-5. Peripheral Signals (3) Submit Documentation Feedback Introduction 27 SM320C6414-EP SM320C6414-EP, SM320C6415-EP SM320C6415-EP, SM320C6416-EP SM320C6416-EP FIXED-POINT DIGITAL SIGNAL PROCESSORS SGUS043D SGUS043D ­ MAY 2003 ­ REVISED SEPTEMBER 2008 www.ti.com UTOPIA (SLAVE) [C6415 C6415 and C6416 C6416 Only] URDATA7 URDATA6 URDATA5 URDATA4 URDATA3 URDATA2 URDATA1 URDATA0 URENB CLKX1/URADDR4 CLKS1/URADDR3 CLKR1/URADDR2 URADDR1 URADDR0 URCLAV URSOC Receive Transmit Control/Status Clock Clock TOUT1 TINP1 Timer 1 TOUT2 TINP2 UXENB DX1/UXADDR4 FSX1/UXADDR3 FSR1/UXADDR2 DR1/UXADDR1 UXADDR0 UXCLAV UXSOC Control/Status URCLK UXDATA7 UXDATA6 UXDATA5 UXDATA4 UXDATA3 UXDATA2 UXDATA1 UXDATA0 Timer 2 UXCLK TOUT0 TINP0 Timer 0 Timers For the C6415 C6415 and C6416 C6416 devices, these UTOPIA pins are MUXed with the McBSP1 peripheral. By default, these signals function as McBSP1. For more details on these MUXed pins, see the Device Configurations section of this data sheet. For the C6414 C6414 device, these McBSP1 peripheral pins are not MUXed; the C6414 C6414 does not support the UTOPIA peripheral. Figure 1-6. Peripheral Signals (4) Contents 1 Introduction . 1 1.3 Description . 2 1.4 Ball-Grid Array (BGA) Package 1.4.1 1.4.2 1.4.3 1.4.4 1.4.5 28 . 3 Device Characteristics . 4 Device Compatiblity . 5 Functional Block and CPU (DSP Core) Diagram . 6 CPU (DSP Core) Description . 7 Memory Map Summary . 10 Contents . . 1.4.8 Interrupt Sources and Interrupt Selector. 1.4.9 Signal Groups Description . Device Configurations. 2.1 Peripherals Selection . 2.2 Other Device Configurations . 2.3 Multiplexed Pins . 2.4 Debugging Considerations . 2.5 Terminal Functions . 1.4.6 Peripheral Register Descriptions 2 11 1.4.7 EDMA Channel Synchronization Events Features . 1 SUPPORTS DEFENSE, AEROSPACE, AND MEDICAL APPLICATIONS . 2 1.1 1.2 21 23 24 30 30 31 33 33 35 Submit Documentation Feedback SM320C6414-EP SM320C6414-EP, SM320C6415-EP SM320C6415-EP, SM320C6416-EP SM320C6416-EP FIXED-POINT DIGITAL SIGNAL PROCESSORS www.ti.com 3 Development Support . 43 3.1 4 SGUS043D SGUS043D ­ MAY 2003 ­ REVISED SEPTEMBER 2008 Device and Development Support Tool Nomenclature . 43 Electrical Specifications . 50 4.1 RECOMMENDED OPERATING CONDITIONS 4.3 5 ABSOLUTE MAXIMUM RATINGS . 50 4.2 ELECTRICAL CHARACTERISTICS . 50 . . Signal Transition Levels . Signal Transition Rates . Timing Parameters and Board Routing Analysis. INPUT AND OUTPUT CLOCKS . 50 PARAMETER MEASUREMENT INFORMATION 52 5.1 52 5.2 5.3 5.1 5.1.1 52 52 53 Timing Requirements for CLKIN for ­50xEP Devices (see Figure 5-5) . 53 5.1.4 Timing Requirements ECLKIN for EMIFA and EMIFB (see Figure 5-8) . 55 5.2 ASYNCHRONOUS MEMORY TIMING . 5.2.1 Timing Requirements for Asynchronous Memory Cycles for EMIFA Module (see Figure 5-11 and Figure 5-12) . 5.2.3 Timing Requirements for Asynchronous Memory Cycles for EMIFB Module (see Figure 5-11 and Figure 5-12) . 5.3 PROGRAMMABLE SYNCHRONOUS INTERFACE TIMING . 5.3.1 Timing Requirements for Programmable Synchronous Interface Cycles for EMIFA Module (see Figure 5-13) . 5.3.3 Timing Requirements for Programmable Synchronous Interface Cycles for EMIFB Module (see Figure 5-13) . 56 56 56 58 58 5.5 HOLD/HOLDA TIMING . 70 5.5.1 Timing Requirements for the HOLD/HOLDA cycles for EMIFA and EMIFB Modules (see Figure 5-24) . 70 5.6 Switching Characteristics Over Recommended Operating Conditions for the HOLD/HOLDA Cycles for EMIFA and EMIFB Modules (see Figure 5-24) . 71 5.7 BUSREQ TIMING . 71 5.8 RESET TIMING 5.8.1 5.9 72 Timing Requirements for Reset (see Figure 5-26 ) 72 EXTERNAL INTERRUPT TIMING . 74 Submit Documentation Feedback 5.10 HOST-PORT INTERFACE (HPI). 74 5.10.1 Timing Requirements for Host-Port Interface Cycles (see Figure 5-28 through Figure 5-35) . 74 5.11 PERIPHERAL COMPONENT INTERCONNECT (PCI) TIMING (C6415 C6415 AND C6416 C6416 ONLY) . 78 5.11.1 5.11.2 Timing Requirements for PCLK (see Figure 5-36 Timing Requirements for PCI Reset (see Figure 5-37) . 5.11.3 Timing Requirements for PCI Inputs (see Figure 5-38) . 5.11.5 Timing Requirements for Serial EEPROM Interface (see Figure 5-39) . 5.12 MULTICHANNEL BUFFERED SERIAL PORT (McBSP) TIMING . 5.12.1 Timing Requirements for McBSP (see Figure 5-40 . 5.12.3 Timing Requirements for FSR When GSYNC = 1 (see Figure 5-41) . 5.12.4 Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 (see ) . 5.12.6 Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 (see Figure 5-43) . 5.13 UTOPIA SLAVE TIMING (C6415 C6415 AND C6416 C6416 ONLY) . 5.13.1 Timing Requirements for UXCLK (see Figure 5-44) . 5.13.2 Timing Requirements for URCLK (see Figure 5-45 79 79 79 80 80 81 82 82 84 84 85 . 59 5.4 SYNCHRONOUS DRAM TIMING. 62 5.4.1 Timing Requirements for Synchronous DRAM Cycles for EMIFA Module (see Figure 5-16 . 62 5.4.3 Timing Requirements for Synchronous DRAM Cycles for EMIFB Module(see Figure 5-16). 63 . 5.9.1 Timing Requirements for External Interrupts (see Figure 5-27) . 74 85 Timing Requirements for UTOPIA Slave Transmit (see Figure 5-46) . 85 5.13.5 Timing Requirements for UTOPIA Slave Receive (see Figure 5-47) . 86 5.13.3 5.14 TIMER TIMING . 5.14.1 Timing Requirements for Timer Inputs (see Figure 5-48) . 5.15 GENERAL-PURPOSE INPUT/OUTPUT (GPIO) PORT TIMING. 5.15.1 Timing Requirements for GPIO Inputs (see Figure 5-48) . 87 87 87 88 5.16 JTAG TEST PORT TIMING . 88 5.16.1 Timing Requirements for JTAG Test Port (see Figure 5-50) . 88 5.16.3 Thermal Resistance Characteristics (S-PBGA Package) . 88 Contents 29 SM320C6414-EP SM320C6414-EP, SM320C6415-EP SM320C6415-EP, SM320C6416-EP SM320C6416-EP FIXED-POINT DIGITAL SIGNAL PROCESSORS SGUS043D SGUS043D ­ MAY 2003 ­ REVISED SEPTEMBER 2008 www.ti.com 2 Device Configurations The C6414 C6414, C6415 C6415, and C6416 C6416 peripheral selections and other device configurations are determined by external pullup/pulldown resistors on the following pins (all of which are latched during device reset): · Peripherals selection (C6415 C6415 and C6416 C6416 devices) ­ BEA11 BEA11 (UTOPIA_EN) ­ PCI_EN (for C6415 C6415 or C6416 C6416, see Table 28 footnotes) ­ MCBSP2_EN (for C6414 C6414 or C6416 C6416, see Table 28 footnotes) The C6414 C6414 device does not support the PCI and UTOPIA peripherals; for proper operation of the C6414 C6414 device, do not oppose the internal pulldowns (IPDs) on the BEA11 BEA11, PCI_EN, and MCBSP2_EN pins. (For IPUs/IPDs on pins, see the Terminal Functions table of this data manual.) · Other device configurations (C64x) ­ BEA[20:13, 7] ­ HD5 2.1 Peripherals Selection Some C6415/C6416 C6415/C6416 peripherals share the same pins (internally multiplexed) and are mutually exclusive (i.e., HPI, GPIO pins GP[15:9], PCI and its internal EEPROM, McBSP1, McBSP2, and UTOPIA). The VCP/TCP coprocessors (C6416 C6416 only) and other C64x peripherals (i.e., the timers, McBSP0, and the GP[8:0] pins) are always available. · UTOPIA and McBSP1 peripherals The UTOPIA_EN pin (BEA11 BEA11) is latched at reset. For C6415 C6415 and C6416 C6416 devices, this pin selects whether the UTOPIA peripheral or McBSP1 peripheral is functionally enabled (see Table 2-1). The C6414 C6414 device does not support the UTOPIA peripheral; for proper device operation, do not oppose the internal pulldown (IPD) on the BEA11 BEA11 pin. Table 2-1. UTOPIA_EN Peripheral Selection (McBSP1 and UTOPIA) (C6415/C6416 C6415/C6416 Only) PERIPHERAL SELECTION UTOPIA_EN (BEA11 BEA11) PIN [D16] PERIPHERALS SELECTED UTOPIA 0 · McBSP1 is enabled and UTOPIA is disabled (default). This means all multiplexed McBSP1/UTOPIA pins function as McBSP1 and all other stand alone UTOPIA pins are tied off (Hi-Z). UTOPIA is enabled and McBSP1 is disabled. This means all multiplexed McBSP1/UTOPIA pins now function as UTOPIA and all other stand alone McBSP1 pins are tied off (Hi-Z). 1 DESCRIPTION McBSP1 HPI, GP[15:9], PCI, EEPROM (internal to PCI), and McBSP2 peripherals The PCI_EN and MCBSP2_EN pins are latched at reset. They determine specific peripheral selection for the C6415 C6415 and C6416 C6416 devices, summarized in Table 2-2. The C6414 C6414 device does not support the PCI peripheral; for proper device operation, do not oppose the internal pulldowns (IPDs) on the PCI_EN and MCBSP2_EN pins. Table 2-2. PCI_EN and MCBSP2_EN Peripheral Selection (HPI, GP[15:9], PCI, and McBSP2) PERIPHERAL SELECTION (1) PERIPHERALS SELECTED PCI_EN PIN [AA4] GP[15:9] 0 0 30 HPI 0 (1) MCBSP2_EN PIN [AF3] 1 PCI EEPROM (INTERNAL TO PCI) McBSP2 The PCI_EN pin must be driven valid at all times and the user must not switch values throughout device operation. The MCBSP2_EN pin must be driven valid at all times and the user can switch values throughout device operation. Device Configurations Submit Documentation Feedback SM320C6414-EP SM320C6414-EP, SM320C6415-EP SM320C6415-EP, SM320C6416-EP SM320C6416-EP FIXED-POINT DIGITAL SIGNAL PROCESSORS www.ti.com SGUS043D SGUS043D ­ MAY 2003 ­ REVISED SEPTEMBER 2008 Table 2-2. PCI_EN and MCBSP2_EN Peripheral Selection (HPI, GP[15:9], PCI, and McBSP2) (continued) PERIPHERAL SELECTION (1) PCI_EN PIN [AA4] MCBSP2_EN PIN [AF3] 1 (2) 1 (2) PERIPHERALS SELECTED PCI EEPROM (INTERNAL TO PCI) 0 1 HPI GP[15:9] McBSP2 The only time McBSP2 is disabled is when both PCI_EN = 1 and MCBSP2_EN = 0. This configuration enables, at reset, the auto-initialization of the PCI peripheral through the PCI internal EEPROM [provided the PCI EEPROM auto-initialization pin (BEA13 BEA13) is pulled up (EEAI = 1)]. The user then can enable the McBSP2 peripheral (disabling EEPROM) by dynamically changing MCBSP2_EN to a 1 after the device is initialized (out of reset). · · · If the PCI is disabled (PCI_EN = 0), the HPI peripheral is enabled and GP[15:9] pins can be programmed as GPIO, provided the GPxEN and GPxDIR bits are properly configured. This means all multiplexed HPI/PCI pins function as HPI and all stand-alone PCI pins (PCBE0 and XSP_CS) are tied off (Hi-Z). Also, the multiplexed GPIO/PCI pins can be used as GPIO with the proper software configuration of the GPIO Enable and Direction registers (for more details, see Table 2-4). If the PCI is enabled (PCI_EN = 1), the HPI peripheral is disabled. This means all multiplexed HPI/PCI pins function as PCI. Also, the multiplexed GPIO/PCI pins function as PCI pins (for more details, see Table 2-4). The MCBSP2_EN pin, in combination with the PCI_EN pin, controls the selection of the McBSP2 peripheral and the PCI internal EEPROM (for more details, see Table 2-2 and its footnotes). 2.2 Other Device Configurations Table 2-3 describes the C6414 C6414, C6415 C6415, and C6416 C6416 devices configuration pins, which are set up via external pullup/pulldown resistors through the specified EMIFB address bus pins (BEA[20:13, 11, 9:7]) and the HD5 pin. For more details on these device configuration pins, see the Terminal Functions table and the Debugging Considerations section. Submit Documentation Feedback Device Configurations 31 SM320C6414-EP SM320C6414-EP, SM320C6415-EP SM320C6415-EP, SM320C6416-EP SM320C6416-EP FIXED-POINT DIGITAL SIGNAL PROCESSORS SGUS043D SGUS043D ­ MAY 2003 ­ REVISED SEPTEMBER 2008 www.ti.com Table 2-3. Device Configuration Pins (BEA[20:13, 9:7], HD5, and BEA11 BEA11) CONFIGURATION PIN NO. BEA20 BEA20 FUNCTIONAL DESCRIPTION E16 Device endian mode (LEND) 0 ­ System operates in big endian mode. 1 ­ System operates in little endian mode (default). Bootmode [1:0] 00 ­ No boot BEA19 BEA19 BEA18 BEA18 D18 C18 01 ­ HPI boot 10 ­ EMIFB 8-bit ROM boot with default timings (default mode) 11 ­ Reserved EMIFA input clock select. Clock-mode select for EMIFA (AECLKIN_SEL[1:0]). 00 ­ AECLKIN (default mode) BEA17 BEA17 BEA16 BEA16 B18 A18 01 ­ CPU/4 clock rate 10 ­ CPU/6 clock rate 11 ­ Reserved EMIFA input clock select. Clock-mode select for EMIFB (BECLKIN_SEL[1:0]). 00 ­ BECLKIN (default mode) BEA15 BEA15 BEA14 BEA14 D17 C17 01 ­ CPU/4 clock rate 10 ­ CPU/6 clock rate 11 ­ Reserved PCI EEPROM auto-initialization (EEAI) (C6415 C6415 and C6416 C6416 devices only) [The C6414 C6414 device does not support the PCI peripheral; for proper device operation, do not oppose the internal pulldown (IPD) on the BEA13 BEA13 pin.] PCI auto-initialization via external EEPROM BEA13 BEA13 0 ­ PCI auto-initialization through EEPROM is disabled; the PCI peripheral uses the specified PCI default values (default). B17 1 ­ PCI auto-initialization through EEPROM is enabled; the PCI peripheral is configured through EEPROM provided the PCI peripheral pin is enabled (PCI_EN = 1) and the McBSP2 peripheral pin is disabled (MCBSP2_EN = 0). Note: If the PCI peripheral is disabled (PCI_EN pin = 0), this pin must not be pulled up. For more information on the PCI EEPROM default values, see the PCI chapter of the TMS320C6000 TMS320C6000 Peripherals Reference Guide (literature number SPRU190 SPRU190). UTOPIA enable (UTOPIA_EN) (C6415 C6415 and C6416 C6416 devices only) [The C6414 C6414 device does not support the UTOPIA peripheral. For proper device operation, do not oppose the internal pulldown (IPD) on the BEA11 BEA11 pin.] UTOPIA peripheral enable (functional) BEA11 BEA11 D16 0 ­ UTOPIA peripheral disabled (McBSP1 functions are enabled) (default). This means all multiplexed McBSP1/UTOPIA pins function as McBSP1 and all other standalone UTOPIA pins are tied off (Hi-Z). 1 ­ UTOPIA peripheral enabled (McBSP1 functions are disabled). This means all multiplexed McBSP1/UTOPIA pins now function as UTOPIA and all other stand-alone McBSP1 pins are tied off (Hi-Z). C6414 C6414 Devices D15 A16 B16 C6415 C6415 Devices C6416 C6416 Devices Do not oppose internal pulldown (IPD) Pullup Do not oppose IPD Do not oppose IPD Do not oppose IPD Pullup(1) Do not oppose IPD BEA7 BEA8 BEA9 Do not oppose IPD Pullup(1) (1) HPI peripheral bus width (HPI_WIDTH) HD5 Y1 0 ­ HPI operates as an HPI16 HPI16. (HPI bus is 16 bits wide. HD[15:0] pins are used and the remaining HD[31:16] pins are reserved pins in the Hi-Z state.) 1 ­ HPI operates as an HPI32 HPI32. (HPI bus is 32 bits wide. All HD[31:0] pins are used for host-port operations.) (1) 32 For proper device operation, this pin must be externally pulled up with a 1-k resistor. Device Configurations Submit Documentation Feedback SM320C6414-EP SM320C6414-EP, SM320C6415-EP SM320C6415-EP, SM320C6416-EP SM320C6416-EP FIXED-POINT DIGITAL SIGNAL PROCESSORS www.ti.com SGUS043D SGUS043D ­ MAY 2003 ­ REVISED SEPTEMBER 2008 2.3 Multiplexed Pins Multiplexed pins are pins that are shared by more than one peripheral and are internally multiplexed. Some of these pins are configured by software, and the others are configured by external pullup/pulldown resistors only at reset. The multiplexed pins that are configured by software can be programmed to switch functionalities at any time. The multiplexed pins that are configured by external pullup/pulldown resistors are mutually exclusive; only one peripheral has primary control of the function of these pins after reset. Table 2-4 identifies the multiplexed pins on the C6414 C6414, C6415 C6415, and C6416 C6416 devices, shows the default (primary) function and the default settings after reset, and describes the pins, registers, etc., necessary to configure specific multiplexed functions. 2.4 Debugging Considerations It is recommended that external connections be provided to device configuration pins, including CLKMODE[1:0], BEA[20:13, 11, 9:7], HD5/AD5, PCI_EN, and MCBSP2_EN. Although internal pullup/pulldown resistors exist on these pins (except for HD5/AD5), providing external connectivity adds convenience to the user in debugging and flexibility in switching operating modes. Internal pullup/pulldown resistors also exist on the nonconfiguration pins on the BEA bus (BEA[12, 10, 6:1]). Do not oppose the internal pullup/pulldown resistors on these nonconfiguration pins with external pullup/pulldown resistors. If an external controller provides signals to these nonconfiguration pins, these signals must be driven to the default state of the pins at reset or not be driven at all. For the internal pullup/pulldown resistors on the C6414 C6414, C6415 C6415, and C6416 C6416 device pins, see the Terminal Functions table. Table 2-4. C6414 C6414, C6415 C6415, and C6416 C6416 Device Multiplexed Pins (1) MULTIPLEXED PINS NAME DEFAULT FUNCTION DEFAULT SETTING DESCRIPTION These pins are software configurable. To use these pins as GPIO pins, the GPxEN bits in the GPIO Enable Register and the GPxDIR bits in the GPIO Direction Register must be properly configured. GPxEN = 1: GPx pin enabled GPxDIR = 0: GPx pin is an input. GPxDIR = 1: GPx pin is an output. NO. CLKOUT4/GP1 (2) AE6 CLKOUT4 GP1EN = 0 (disabled) CLKOUT6/GP2 (2) AD6 CLKOUT6 GP2EN = 0 (disabled) CLKS2/GP8 (2) AE4 CLKS2 GP8EN = 0 (disabled) GP9/PIDSEL M3 GP10/PCBE3 GP10/PCBE3 L2 GP11/PREQ GP11/PREQ F1 GP12/PGNT GP12/PGNT J3 GP14/PCLK GP14/PCLK G4 GP13/PINTA GP13/PINTA GPxEN = 0 (disabled) PCI_EN = 0 (disabled) (1) UTOPIA_EN (BEA11 BEA11) = 0 (disabled) (1) By default, McBSP1 is enabled upon reset (UTOPIA is disabled). To enable the UTOPIA peripheral, an external pullup resistor (1 k) must be provided on the BEA11 BEA11 pin (setting UTOPIA_EN = 1 at reset). F2 GP15/PRST GP15/PRST None To use GP[15:9] as GPIO pins, the PCI must be disabled (PCI_EN = 0), the GPxEN bits in the GPIO Enable Register and the GPxDIR bits in the GPIO Direction. Register must be properly configured. GPxEN = 1: GPx pin enabled GPxDIR = 0: GPx pin is an input. GPxDIR = 1: GPx pin is an output. G3 DX1/UXADDR4 AB11 DX1 FSX1/UXADDR3 AB13 FSX1 FSR1/UXADDR2 AC9 FSR1 DR1/UXADDR1 AF11 DR1 CLKX1/URADDR4 AB12 CLKX1 CLKS1/URADDR3 AC8 CLKS1 CLKR1/URADDR2 AC10 CLKR1 (1) (2) For the C6415 C6415 and C6416 C6416 devices, all other stand-alone UTOPIA and PCI pins are tied off internally (pins in Hi-Z) when the peripheral is disabled [UTOPIA_EN (BEA11 BEA11) = 0 or PCI_EN = 0]. The C6414 C6414 device does not support the PCI and UTOPIA peripherals. These are the only multiplexed pins on the C6414 C6414 device, all other pins are stand-alone peripheral functions and are not multiplexed. Submit Documentation Feedback Device Configurations 33 SM320C6414-EP SM320C6414-EP, SM320C6415-EP SM320C6415-EP, SM320C6416-EP SM320C6416-EP FIXED-POINT DIGITAL SIGNAL PROCESSORS SGUS043D SGUS043D ­ MAY 2003 ­ REVISED SEPTEMBER 2008 www.ti.com Table 2-4. C6414 C6414, C6415 C6415, and C6416 C6416 Device Multiplexed Pins (continued) MULTIPLEXED PINS NAME DEFAULT FUNCTION DEFAULT SETTING DESCRIPTION NO. CLKX2/XSP_CLK AC2 CLKX2 DR2/XSP_DI AB3 DR2 DX2/XSP_DO AA2 DX2 (3) HD[31:0]/AD[31:0] HD[31:0] HAS/PPAR T3 HAS HCNTL1/PDEVSEL R1 HCNTL1 HCNTL0/PSTOP T4 HCNTL0 HDS1/PSERR T1 HDS1 HDS2/PCBE1 T2 HDS2 HR/W/PCBE2 P1 HR/W HWWIL/PTRDY R3 HHWIL (HPI16 HPI16 only) HINT/PFRAME R4 HINT HCS/PPERR R2 HCS HRDY/PIRDY P4 HRDY (3) 34 PCI_EN = 0 (disabled) (1) By default, HPI is enabled upon reset (PCI is disabled). To enable the PCI peripheral an external pullup resistor (1 k) must be provided on the PCI_EN pin (setting PCI_EN = 1 at reset). For the pin numbers of the HD[31:0]/AD[31:0] multiplexed pins, see the Terminal Functions table. Device Configurations Submit Documentation Feedback SM320C6414-EP SM320C6414-EP, SM320C6415-EP SM320C6415-EP, SM320C6416-EP SM320C6416-EP FIXED-POINT DIGITAL SIGNAL PROCESSORS www.ti.com SGUS043D SGUS043D ­ MAY 2003 ­ REVISED SEPTEMBER 2008 2.5 Terminal Functions TERMINAL NAME NO. TYPE (1) IPD/IPU DESCRIPTION (2) CLOCK/PLL Configuration CLKIN H4 I IPD Clock input. This clock is the input to the on-chip PLL. (3) AE6 I/O/Z IPD Clock output at 1/4 of the device speed (O/Z) (default) or this pin can be programmed as a GPIO1 pin (I/O/Z). CLKOUT6/GP2 (3) AD6 I/O/Z IPD Clock output at 1/6 of the device speed (O/Z) (default) or this pin can be programmed as a GPIO2 pin (I/O/Z). CLKMODE1 G1 I IPD CLKMODE0 H2 I IPD PLLV (4) J6 A (5) CLKOUT4/GP1 Clock-mode select. Selects whether the CPU clock frequency = input clock frequency ×1 (bypass), ×6, or ×12. For more details on the CLKMODE pins and the PLL multiply factors, see the Clock PLL section of this data manual. PLL voltage supply JTAG Emulation TMS AB16 I IPU JTAG test-port mode select TDO AE19 O/Z IPU JTAG test-port data out TDI AF18 I IPU JTAG test-port data in TCK AF16 I IPU JTAG test-port clock TRST AB15 I IPD JTAG test-port reset. For IEEE Std 1149.1 JTAG compatibility, see the IEEE Std 1149.1 JTAG Compatibility Statement section of this data manual. EMU11 EMU11 AC18 EMU10 EMU10 AD18 I/O/Z IPU Emulation pin [11:2]. Reserved for future use, leave unconnected. EMU9 AE18 EMU8 AC17 EMU7 AF17 EMU6 AD17 EMU5 AE17 EMU4 AC16 EMU3 AD16 EMU2 AE16 Emulation pins [1:0] Select the device functional mode of operation: EMU[1:0] EMU1 EMU0 AC15 AF15 I/O/Z IPU Operation 00 01 10 11 Boundary Scan/Normal mode (see Note) Reserved Reserved Emulation/Normal mode (default) (see the IEEE 1149.1 JTAG Compatibility Statement section of this data manual) Normal mode refers to the DSPs normal operational mode, when the DSP is free running. The DSP can be placed in normal operational mode when the EMU[1:0] pins are configured for either Boundary Scan or Emulation. Note: When the EMU[1:0] pins are configured for Boundary Scan mode, the internal pulldown (IPD) on the TRST signal must not be opposed in order to operate in Normal mode. For the Boundary Scan mode pulldown EMU[1:0] pins with a dedicated 1-k resistor. Resets, Interrupts, and General-Purpose Input/Outputs (GPIOs) RESET NMI (1) (2) (3) (4) (5) AC7 I B4 I Device reset IPD Nonmaskable interrupt, edge-driven (rising edge) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-k IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-k resistor should be used.) These pins are multiplexed pins. For more details, see the Device Configurations section of this data manual. PLLV is not part of external voltage supply. See the Clock PLL section for information on how to connect this pin. A = Analog signal (PLL filter) Submit Documentation Feedback Device Configurations 35 SM320C6414-EP SM320C6414-EP, SM320C6415-EP SM320C6415-EP, SM320C6416-EP SM320C6416-EP FIXED-POINT DIGITAL SIGNAL PROCESSORS SGUS043D SGUS043D ­ MAY 2003 ­ REVISED SEPTEMBER 2008 TERMINAL NAME NO. TYPE (1) IPD/IPU www.ti.com (2) DESCRIPTION IPU GP7/EXT_INT7 AF4 GP6/EXT_INT6 AD5 GP5/EXT_INT5 AE5 GP4/EXT_INT4 AF5 General-purpose input/outputs (GPIO) (I/O/Z) or external interrupts (input only). The default after reset setting is GPIO enabled as input only. When these pins function as external interrupts [by selecting the corresponding interrupt enable register bit (IER.[7:4])], they are edge driven and the polarity can be independently selected via the External Interrupt Polarity Register bits (EXTPOL[3:0]). GP15/PRST GP15/PRST (6) G3 General-purpose input/output (GPIO) 15 (I/O/Z) or PCI reset (I). No function at default. F2 GPIO 14 (I/O/Z) or PCI clock (I). No function at default. GP14/PCLK GP14/PCLK (6) GP13/PINTA GP13/PINTA (6) G4 GP12/PGNT GP12/PGNT (6) J3 (6) I/O/Z GP11/PREQ GP11/PREQ GPIO 13 (I/O/Z) or PCI interrupt A (O/Z). No function at default. I/O/Z GPIO 12 (I/O/Z) or PCI bus grant (I). No function at default. F1 GPIO 11 (I/O/Z) or PCI bus request (O/Z). No function at default. GP10/PCBE3 GP10/PCBE3 (6) L2 GPIO 10 (I/O/Z) or PCI command/byte enable 3 (I/O/Z). No function at default. GP9/PIDSEL (6) M3 GP3 AC6 I/O/Z GP0 AF6 I/O/Z IPD GPIO 0 (I/O/Z). Can be programmed as GPIO 0 (input only) (default) or as GPIO 0 (output only) pin or output as a general-purpose interrupt (GP0INT) signal (output only). AE4 I/O/Z IPD McBSP2 external clock source (CLKS2) [input only] (default) or this pin can be programmed as a GPIO 8 pin (I/O/Z). AD6 I/O/Z IPD Clock output at 1/6 of the device speed (O/Z) (default) or this pin can be programmed as a GPIO 2 pin (I/O/Z). AE6 I/O/Z IPD Clock output at 1/4 of the device speed (O/Z) (default) or this pin can be programmed as a GPIO 1 pin (I/O/Z). CLKS2/GP8 (6) (7) CLKOUT6/GP2 (6) (7) CLKOUT4/GP1 (6) (7) GPIO 9 (I/O/Z) or PCI initialization device select (I). No function at default. GPIO 3 (I/O/Z). The default after reset setting is GPIO 3 enabled as input only. Host-Port Interface (HPI) (C64x) or Peripheral Component Interconnect (PCI) (C6415 C6415 or C6416 C6416 Devices Only) PCI_EN AA4 I HINT/PFRAME (6) R4 I/O/Z Host interrupt from DSP to host (O) (default) or PCI frame (I/O/Z) HCNTL1/PDEVS EL (6) R1 I/O/Z Host control 1. Selects between control, address, or data registers (I) (default) or PCI device select (I/O/Z). 6) T4 I/O/Z Host control 0. Selects between control, address, or data registers (I) (default) or PCI stop (I/O/Z). HHWIL/PTRDY (6) R3 I/O/Z Host half-word select-first or second half word (not necessarily high or low order) (For HPI16 HPI16 bus width selection only) (I) (default) or PCI target ready (I/O/Z). HR/W/PCBE2 (6) P1 I/O/Z Host read or write select (I) (default) or PCI command/byte enable 2 (I/O/Z) HAS/PPAR (6) T3 I/O/Z Host address strobe (I) (default) or PCI parity (I/O/Z) HCS/PPERR (6) R2 I/O/Z Host chip select (I) (default) or PCI parity error (I/O/Z) (6) T1 I/O/Z Host data strobe 1 (I) (default) or PCI system error (I/O/Z) HDS2/PCBE1 (6) T2 I/O/Z Host data strobe 2 (I) (default) or PCI command/byte enable 1 (I/O/Z) HRDY/PIRDY (6) P4 I/O/Z Host ready from DSP to host (O) (default) or PCI initiator ready (I/O/Z) HCNTL0/PSTOP ( HDS1/PSERR (6) (7) 36 IPD PCI enable. This pin controls the selection (enable/disable) of the HPI and GP[15:9], or PCI peripherals (for the C6415 C6415 and C6416 C6416 devices). This pin works in conjunction with the MCBSP2_EN pin to enable/disable other peripherals (for more details, see the Device Configurations section of this data manual). The C6414 C6414 device does not support the PCI peripheral; for proper device operation, do not oppose the internal pulldown (IPD) on this pin. For the C6415 C6415 and C6416 C6416 devices, these pins are multiplexed pins. For more details, see the Device Configurations section of this data manual. The C6414 C6414 device does not support the PCI or UTOPIA peripherals; therefore, these MUXed peripheral pins are stand alone peripheral functions for this device. For the C6414 C6414 device, only these pins are multiplexed pins. Device Configurations Submit Documentation Feedback SM320C6414-EP SM320C6414-EP, SM320C6415-EP SM320C6415-EP, SM320C6416-EP SM320C6416-EP FIXED-POINT DIGITAL SIGNAL PROCESSORS www.ti.com SGUS043D SGUS043D ­ MAY 2003 ­ REVISED SEPTEMBER 2008 TERMINAL NAME NO. HD31/AD31 HD31/AD31 (6) IPD/IPU (2) DESCRIPTION J2 HD30/AD30 HD30/AD30 (6) TYPE (1) K3 HD29/AD29 HD29/AD29 (6) J1 HD28/AD28 HD28/AD28 (6) K4 HD27/AD27 HD27/AD27 (6) K2 (6) L3 HD25/AD25 HD25/AD25 (6) K1 HD24/AD24 HD24/AD24 (6) L4 HD26/AD26 HD26/AD26 (6) L1 HD22/AD22 HD22/AD22 (6) M4 HD21/AD21 HD21/AD21 (6) M2 HD20/AD20 HD20/AD20 (6) N4 (6) M1 HD18/AD18 HD18/AD18 (6) N5 HD17/AD17 HD17/AD17 (6) N1 (6) U4 HD23/AD23 HD23/AD23 HD19/AD19 HD19/AD19 HD15/AD15 HD15/AD15 HD16/AD16 HD16/AD16 (6) P5 HD15/AD15 HD15/AD15 (6) U1 HD13/AD13 HD13/AD13 (6) U3 HD12/AD12 HD12/AD12 (6) U2 HD11/AD11 HD11/AD11 (6) V4 (6) PCI command/byte enable 0 (I/O/Z). When PCI is disabled (PCI_EN = 0), this pin is tied­off. For the C6414 C6414 device this pin is "Reserved (leave unconnected, do not connect to power or ground)." U4 HD14/AD14 HD14/AD14 (6) I/O/Z Host-port data (I/O/Z) (default) (C64x) or PCI data-address bus (I/O/Z) (C6415 C6415 and C6416 C6416) AS HPI data bus (PCIPEN pin = 0): Used for transfer of data, address, and control . Host-port bus width user configurable at device reset via a 10-k. resistor pullup/pulldown resistor on the HD5 pin: HD5 pin = 0: HPI operates as an HPI16 HPI16. (HPI bus is 16 bits wide. HD[15:0] pins are used and the remaining HD[31:16] pins are reserved pins in the high-impedance state.) HD5 pin = 1: HPI operates as an HPI32 HPI32. (HPI bus is 32 bits wide. All HD[31:0] pins are used for host-port operations.) As PCI data-address bus (PCI_EN pin = 1) (C6415 C6415 and C6416 C6416 devices only): Used for transfer of data and address The C6414 C6414 device does not support the PCI peripheral; therefore, the HPI peripheral pins are stand alone peripheral functions, not