SN65HVD05 SN65HVD06 SN65HVD07 SN75HVD05 SN75HVD06 SN75HVD07 SLLS533B RS-485

SN75HVD05, SN75HVD06, SN75HVD07 www.ti.com SLLS533B MAY 2002 REVISED MAY 2003 HIGH OUTPUT RS-485 TRANSCEIVERS

SN65HVD05 SN65HVD05, SN65HVD06 SN65HVD06, SN65HVD07 SN65HVD07 SN75HVD05 SN75HVD05, SN75HVD06 SN75HVD06, SN75HVD07 SN75HVD07 www.ti.com SLLS533B SLLS533B MAY 2002 REVISED MAY 2003 HIGH OUTPUT RS-485 RS-485 TRANSCEIVERS FEATURES D Minimum Differential Output Voltage of 2.5 V D D D D D D D D Into a 54- Load Open-Circuit, Short-Circuit, and Idle-Bus Failsafe Receiver 1/8th Unit-Load Option Available (Up to 256 Nodes on the Bus) Bus-Pin ESD Protection Exceeds 16 kV HBM Driver Output Slew Rate Control Options Electrically Compatible With ANSI TIA/EIA-485-A TIA/EIA-485-A Standard Low-Current Standby Mode . . . 1 µA Typical Glitch-Free Power-Up and Power-Down Protection for Hot-Plugging Applications Pin Compatible With Industry Standard SN75176 SN75176 APPLICATIONS D Data Transmission Over Long or Lossy Lines D D D D D D or Electrically Noisy Environments Profibus Line Interface Industrial Process Control Networks Point-of-Sale (POS) Networks Electric Utility Metering Building Automation Digital Motor Control DESCRIPTION The SN65HVD05 SN65HVD05, SN75HVD05 SN75HVD05, SN65HVD06 SN65HVD06, SN75HVD06 SN75HVD06, SN65HVD07 SN65HVD07, and SN75HVD07 SN75HVD07 combine a 3-state differential line driver and differential line receiver. They are designed for balanced data transmission and interoperate with ANSI TIA/EIA-485-A TIA/EIA-485-A and ISO 8482E 8482E standard-compliant devices. The driver is designed to provide a differential output voltage greater than that required by these standards for increased noise margin. The drivers and receivers have active-high and active-low enables respectively, which can be externally connected together to function as direction control. The driver differential outputs and receiver differential inputs connect internally to form a differential input/ output (I/O) bus port that is designed to offer minimum loading to the bus whenever the driver is disabled or not powered. These devices feature wide positive and negative common-mode voltage ranges, making them suitable for party-line applications. D OR P PACKAGE (TOP VIEW) R RE DE D DIFFERENTIAL OUTPUT VOLTAGE vs DIFFERENTIAL OUTPUT CURRENT V O Differential Output Voltage V 4 60 Load Line 3.5 TA = 25°C DE at VCC D at VCC VCC = 5 V R 30 Load Line 3 8 2 7 3 6 4 5 VCC B A GND LOGIC DIAGRAM (POSITIVE LOGIC) 5 4.5 1 RE 1 2 2.5 2 DE 1.5 3 6 4 1 D 0.5 7 A B 0 0 20 40 60 80 100 120 IOD Differential Output Current mA Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 20022003, Texas Instruments Incorporated SN65HVD05 SN65HVD05, SN65HVD06 SN65HVD06, SN65HVD07 SN65HVD07 SN75HVD05 SN75HVD05, SN75HVD06 SN75HVD06, SN75HVD07 SN75HVD07 www.ti.com SLLS533B SLLS533B MAY 2002 REVISED MAY 2003 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION(1) MARKED AS DRIVER OUTPUT SLOPE CONTROL PLASTIC DUAL-IN-LINE PACKAGE (PDIP) SMALL OUTLINE IC (SOIC) PACKAGE SIGNALING RATE UNIT LOAD 40 Mbps 1/2 No SN65HVD05D SN65HVD05D SN65HVD05P SN65HVD05P 65HVD05 65HVD05 VP05 10 Mbps 1/8 Yes SN65HVD06D SN65HVD06D SN65HVD06P SN65HVD06P 65HVD06 65HVD06 VP06 PART NUMBER(2) TA 40°C to 85°C 40 C 85 C 1 Mbps 1/8 Yes SN65HVD07D SN65HVD07D SN65HVD07P SN65HVD07P 65HVD07 65HVD07 VP07 40 Mbps 1/2 No SN75HVD05D SN75HVD05D SN75HVD05P SN75HVD05P 75HVD05 75HVD05 VN05 10 Mbps 1/8 Yes SN75HVD06D SN75HVD06D SN75HVD06P SN75HVD06P 75HVD06 75HVD06 VN06 1 Mbps 1/8 Yes SN75HVD07D SN75HVD07D SN75HVD07P SN75HVD07P 75HVD07 75HVD07 (1) For the most current specification and package information, refer to our web site at www.ti.com. (2) The D package is available taped and reeled. Add an R suffix to the device type (i.e., SN65HVD05DR SN65HVD05DR). VN07 0°C to 70°C 0 C 70 C PACKAGE DISSIPATION RATINGS (SEE FIGURE 12 AND FIGURE 13) TA 25°C POWER RATING D(2) D(3) 710 mW DERATING FACTOR(1) ABOVE TA = 25°C 5.7 mW/°C 1282 mW 10.3 mW/°C 821 mW 667 mW P 1000 mW 8.0 mW/°C 640 mW 520 mW PACKAGE TA = 70°C POWER RATING TA = 85°C POWER RATING 455 mW 369 mW (1) This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow. (2) Tested in accordance with the Low-K thermal metric definitions of EIA/JESD51-3 EIA/JESD51-3 (3) Tested in accordance with the High-K thermal metric definitions of EIA/JESD51-7 EIA/JESD51-7 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted(1) (2) SN65HVD05 SN65HVD05, SN65HVD06 SN65HVD06, SN65HVD07 SN65HVD07 SN75HVD05 SN75HVD05, SN75HVD06 SN75HVD06, SN75HVD07 SN75HVD07 Supply voltage range, VCC 0.3 V to 6 V Voltage range at A or B 9 V to 14 V Input voltage range at D, DE, R or RE 0.5 V to VCC + 0.5 V Voltage input range, transient pulse, A and B, through 100 (see Figure 11) Electrostatic discharge Human body model(3) Charged-device model(4) 50 V to 50 V A, B, and GND 16 kV All pins 4 kV All pins Continuous total power dissipation Storage temperature range, Tstg Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 1 kV See Dissipation Rating Table 65°C to 150°C 260°C (1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal. (3) Tested in accordance with JEDEC Standard 22, Test Method A114-A A114-A. (4) Tested in accordance with JEDEC Standard 22, Test Method C101. 2 SN65HVD05 SN65HVD05, SN65HVD06 SN65HVD06, SN65HVD07 SN65HVD07 SN75HVD05 SN75HVD05, SN75HVD06 SN75HVD06, SN75HVD07 SN75HVD07 www.ti.com SLLS533B SLLS533B MAY 2002 REVISED MAY 2003 RECOMMENDED OPERATING CONDITIONS MIN Supply voltage, VCC Voltage at any bus terminal (separately or common mode) VI or VIC High-level input voltage, VIH D, DE, RE Low-level input voltage, VIL NOM MAX UNIT 4.5 7(1) 5.5 12 D, DE, RE V 0.8 V 12 V 12 Driver 100 Receiver mA 8 Driver Low-level Low level output current IOL current, V 2 Differential input voltage, VID (see Figure 7) High-level High level output current IOH current, V 100 Receiver 8 mA SN65HVD05 SN65HVD05 40 40 85 °C C 0 SN65HVD06 SN65HVD06 70 °C C SN65HVD07 SN65HVD07 Operating free air temperature TA free-air temperature, SN75HVD05 SN75HVD05 SN75HVD06 SN75HVD06 SN75HVD07 SN75HVD07 (1) The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet. DRIVER ELECTRICAL CHARACTERISTICS over operating free-air temperature range unless otherwise noted(1) TEST CONDITIONS PARAMETER VIK |VOD| Input clamp voltage II = 18 mA No Load |VOD| Change in magnitude of differential output voltage VOC(SS) Steady-state common-mode output voltage VOC(SS) Change in steady-state common-mode output voltage VOC(PP) Peak-to-peak commonPeak to peakcommon mode output voltage IOZ See Figure 1 and Figure 2 0.2 0.2 V 2.2 3.3 V 0.1 0.1 V See Figure 3 600 500 See Figure 3 See receiver input currents D 100 IOS C(diff) Short-circuit output current 7 V VO 12 V Differential output capacitance VID = 0.4 sin (4E6t) + 0.5 V, DE at 0 V RE at VCC, Receiver disabled and D & DE at VCC, No load driver enabled Receiver disabled and RE at VCC, D at VCC driver disabled DE at 0 V, No load (standby) DE RE at 0 V, D & DE at VCC, No load 0 0 Input current Supply current mV 900 II ICC V 2.2 HVD07 HVD07 High-impedance output current UNIT V 2.5 HVD05 HVD05 HVD06 HVD06 MAX VCC RL = 54 , See Figure 1 Vtest = 7 V to 12 V, See Figure 2 Differential out ut voltage output MIN TYP(1) 1.5 100 250 Receiver enabled and driver enabled 250 16 µA mA pF 9 15 mA 1 5 µA 9 15 mA (1) All typical values are at 25°C and with a 5-V supply. 3 SN65HVD05 SN65HVD05, SN65HVD06 SN65HVD06, SN65HVD07 SN65HVD07 SN75HVD05 SN75HVD05, SN75HVD06 SN75HVD06, SN75HVD07 SN75HVD07 www.ti.com SLLS533B SLLS533B MAY 2002 REVISED MAY 2003 DRIVER SWITCHING CHARACTERISTICS NIL over operating free-air temperature range unless otherwise noted TEST CONDITIONS PARAMETER MIN TYP(1) MAX HVD05 HVD05 Pro agation Propagation delay time, low to high level out ut low-to-high-level output 6.5 11 HVD06 HVD06 27 40 HVD07 HVD07 tPLH 250 400 HVD05 HVD05 Pro agation Propagation delay time, high to low level out ut high-to-low-level output 6.5 27 40 250 400 HVD05 HVD05 tr Differential out ut signal rise time output HVD06 HVD06 HVD07 HVD07 RL = 54 , CL = 50 pF, F, See Figure 4 2.7 3.6 28 55 150 300 450 2.7 3.6 18 28 55 150 300 450 HVD05 HVD05 Pulse skew (|tPHL tPLH|) 2.5 10 HVD05 HVD05 tPZH1 Pro agation Propagation delay time, high im edance to high level out ut high-impedance-to-high-level output 14 100 HVD05 HVD05 Part to art Part-to-part skew 25 45 HVD06 HVD06 HVD07 HVD07 HVD05 HVD05 RE at 0 V, RL = 110 , See Figure 5 tPZL1 Pro agation Propagation delay time, high im edance to low level out ut high-impedance-to-low-level output HVD06 HVD06 60 250 15 HVD06 HVD06 HVD07 HVD07 HVD05 HVD05 45 RE at 0 V, RL = 110 , See Figure 6 Pro agation Propagation delay time, low level to high im edance out ut low-level-to-high-impedance output ns ns 200 14 HVD06 HVD06 90 HVD07 HVD07 tPLZ ns 25 HVD05 HVD05 Pro agation Propagation delay time, high level to high im edance out ut high-level-to-high-impedance output ns 250 HVD07 HVD07 tPHZ ns 3.5 HVD06 HVD06 HVD07 HVD07 tsk(pp)(2) sk( ) ns 2 HVD06 HVD06 HVD07 HVD07 tsk(p) sk( ) ns 6 HVD06 HVD06 HVD07 HVD07 Differential out ut signal fall time output ns 6 18 HVD05 HVD05 tf ns 11 HVD06 HVD06 HVD07 HVD07 tPHL UNIT 550 ns tPZH2 Propagation delay time, standby-to-high-level output RL = 110 , RE at 3 V, See Figure 5 6 µs tPZL2 Propagation delay time, standby-to-low-level output RL = 110 , RE at 3 V, See Figure 6 6 µs (1) All typical values are at 25°C and with a 5-V supply. (2) tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits. 4 SN65HVD05 SN65HVD05, SN65HVD06 SN65HVD06, SN65HVD07 SN65HVD07 SN75HVD05 SN75HVD05, SN75HVD06 SN75HVD06, SN75HVD07 SN75HVD07 www.ti.com SLLS533B SLLS533B MAY 2002 REVISED MAY 2003 RECEIVER ELECTRICAL CHARACTERISTICS over operating free-air temperature range unless otherwise noted PARAMETER MIN TYP(1) TEST CONDITIONS IO = 8 mA VIT Negative-going input threshold voltage IO = 8 mA MAX UNIT 0.01 VIT+ Positive-going input threshold voltage V 0.2 1.5 Vhys VIK Hysteresis voltage (VIT+ VIT) VOH VOL High-level output voltage II = 18 mA VID = 200 mV, Low-level output voltage VID = 200 mV, IOH = 8 mA, IOL = 8 mA, High-impedance-state output current VO = 0 or VCC RE at VCC IOZ Enable-input clamp voltage HVD05 HVD05 II 35 Other in ut input at 0 V Bus input current HVD06 HVD06, HVD07 HVD07 IIH IIL High-level input current, RE C(diff) Differential input capacitance Low-level input current, RE V Other in ut input at 0 V VA or VB = 12 V VA or VB = 12 V, See Figure 7 V 4 V See Figure 7 0.4 1 1 0.23 VCC = 0 V VA or VB = 12 V VA or VB = 12 V, VCC = 0 V 0.5 V µA 0.5 0.3 VCC = 0 V VA or VB = 7 V VA or VB = 7 V, VA or VB = 7 V VA or VB = 7 V, mV 0.4 0.13 0.4 mA 0.15 0.06 0.1 0.08 0.13 mA 0.1 0.03 26.4 µA 60 VI = 0.4 sin (4E6t) + 0.5 V, DE at 0 V RE at 0 V, D & DE at 0 V, Receiver enabled and driver disabled No load 0.05 60 VCC = 0 V VIH = 2 V VIL = 0.8 V 0.05 27.4 µA 16 pF 5 10 mA Supply current Receiver disabled and driver disabled (standby) 1 5 µA RE at 0 V, D & DE at VCC, No load ICC RE at VCC, DE at 0 V, D at VCC, No load Receiver enabled and driver enabled 9 15 mA (1) All typical values are at 25°C and with a 5-V supply. 5 SN65HVD05 SN65HVD05, SN65HVD06 SN65HVD06, SN65HVD07 SN65HVD07 SN75HVD05 SN75HVD05, SN75HVD06 SN75HVD06, SN75HVD07 SN75HVD07 www.ti.com SLLS533B SLLS533B MAY 2002 REVISED MAY 2003 RECEIVER SWITCHING CHARACTERISTICS over operating free-air temperature range unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT tPLH tPHL Propagation delay time, low-to-high-level output 1/2 UL HVD05 HVD05 14.6 25 ns Propagation delay time, high-to-low-level output 1/2 UL HVD05 HVD05 14.6 25 ns HVD06 HVD06 55 70 tPLH Propagation delay time low-to-high-level output 1/8 UL time, low to high level HVD07 HVD07 55 70 55 70 55 70 HVD06 HVD06 tPHL Propagation delay time high-to-low-level output 1/8 UL time, high to low level HVD07 HVD07 VID = 1.5 V to 1.5 V, CL = 15 pF, F, See Figure 8 HVD05 HVD05 HVD07 HVD07 Part to art Part-to-part skew tr tf Output signal rise time tPZH1 tPZL1 Output disable time from high level tPZH2 tPZL2 Propagation delay time, standby-to-high-level output HVD06 HVD06 14 14 Output enable time to high level tPHZ tPLZ 6.5 HVD07 HVD07 tsk( )(2) sk(pp)( ) Pulse skew (|tPHL tPLH|) 4.5 HVD05 HVD05 tsk(p) sk( ) 4.5 Output signal fall time Output enable time to low level CL = 15 pF, F, See Figure 8 2 3 ns 3 2 ns ns 10 CL = 15 pF, DE at 3 V V, See Figure 9 Output disable time from low level Propagation delay time, standby-to-low-level output ns 2 HVD06 HVD06 ns 10 15 ns 15 CL = 15 pF, DE at 0, F, See Figure 10 6 6 µs s (1) All typical values are at 25°C and with a 5-V supply. (2) tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits. 6 SN65HVD05 SN65HVD05, SN65HVD06 SN65HVD06, SN65HVD07 SN65HVD07 SN75HVD05 SN75HVD05, SN75HVD06 SN75HVD06, SN75HVD07 SN75HVD07 www.ti.com SLLS533B SLLS533B MAY 2002 REVISED MAY 2003 PARAMETER MEASUREMENT INFORMATION VCC DE II 375 ±1% VCC A IOA DE VOD 0 or 3 V B D 54 ±1% A VOD 0 or 3 V IOB 60 ±1% + 7 V < V(test) _ < 12 V B VI 375 ±1% VOB VOA Figure 2. Driver VOD With Common-Mode Loading Test Circuit Figure 1. Driver VOD Test Circuit and Voltage and Current Definitions A VCC DE Input D B 27 ± 1% A VA VB VOC(PP) 27 ± 1% B CL = 50 pF ±20% VOC VOC(SS) VOC CL Includes Fixture and Instrumentation Capacitance Input: PRR = 500 kHz, 50% Duty Cycle,tr