AM26LS32AC AM26LS33AC AM26LS32AM AM26LS33AM SLLS115C AM26LS32A EIA/TIA-422-B - Datasheet Archive

 

QUADRUPLE DIFFERENTIAL LINE RECEIVERS SLLS115C ­ OCTOBER 1980 ­ REVISED APRIL 2000 D D D D D D D D D AM26LS32AC,

 

AM26LS32AC AM26LS32AC, AM26LS33AC AM26LS33AC, AM26LS32AM AM26LS32AM, AM26LS33AM AM26LS33AM QUADRUPLE DIFFERENTIAL LINE RECEIVERS SLLS115C SLLS115C ­ OCTOBER 1980 ­ REVISED APRIL 2000 D D D D D D D D D AM26LS32AC AM26LS32AC, AM26LS33AC AM26LS33AC . . . D OR N PACKAGE AM26LS32AM AM26LS32AM, AM26LS33AM AM26LS33AM . . . J PACKAGE (TOP VIEW) AM26LS32A AM26LS32A Meets or Exceeds the Requirements of ANSI EIA/TIA-422-B EIA/TIA-422-B, EIA/TIA-423-B EIA/TIA-423-B, and ITU Recommendations V.10 and V.11 AM26LS32A AM26LS32A Has ±7-V Common-Mode Range With ±200-mV Sensitivity AM26LS33A AM26LS33A Has ±15-V Common-Mode Range With ±500-mV Sensitivity Input Hysteresis . . . 50 mV Typical Operates From a Single 5-V Supply Low-Power Schottky Circuitry 3-State Outputs Complementary Output-Enable Inputs Input Impedance . . . 12 k Min Designed to Be Interchangeable With Advanced Micro Devices AM26LS32TM AM26LS32TM and AM26LS33TM AM26LS33TM 1B 1A 1Y G 2Y 2A 2B GND 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC 4B 4A 4Y G 3Y 3A 3B AM26LS32AM AM26LS32AM, AM26LS33AM AM26LS33AM . . . FK PACKAGE (TOP VIEW) 1A 1B NC VCC 4B D 1Y G NC 2Y 2A description 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 4A 4Y NC G 3Y 2B GND NC 3B 3A The AM26LS32A AM26LS32A and AM26LS33A AM26LS33A devices are quadruple differential line receivers for balanced and unbalanced digital data transmission. The enable function is common to all four receivers and offers a choice of active-high or active-low input. The 3-state outputs permit connection directly to a bus-organized system. Fail-safe design ensures that, if the inputs are open, the outputs are always high. 4 NC ­ No internal connection Compared to the AM26LS32 AM26LS32 and the AM26LS33 AM26LS33, the AM26LS32A AM26LS32A and AM26LS33A AM26LS33A incorporate an additional stage of amplification to improve sensitivity. The input impedance has been increased, resulting in less loading of the bus line. The additional stage has increased propagation delay; however, this does not affect interchangeability in most applications. The AM26LS32AC AM26LS32AC and AM26LS33AC AM26LS33AC are characterized for operation from 0°C to 70°C. The AM26LS32AM AM26LS32AM and AM26LS33AM AM26LS33AM are characterized for operation over the full military temperature range of ­55°C to 125°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. AM26LS32 AM26LS32 and AM26LS33 AM26LS33 are trademarks of Advanced Micro Devices, Inc. Copyright © 2000, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 1 AM26LS32AC AM26LS32AC, AM26LS33AC AM26LS33AC, AM26LS32AM AM26LS32AM, AM26LS33AM AM26LS33AM QUADRUPLE DIFFERENTIAL LINE RECEIVERS SLLS115C SLLS115C ­ OCTOBER 1980 ­ REVISED APRIL 2000 FUNCTION TABLE (each receiver) DIFFERENTIAL A­B ENABLES X H L H H X ? X L ? H VID VIT­ IT OUTPUT Y X VIT VID VIT IT­ IT+ G H VID VIT+ IT G X L X L H Z H X H X Open L L X L H H = high level, L = low level, ? = indeterminate, X = irrelevant, Z = high impedance (off) logic symbol G 4 1 EN 12 G 1A 1B 2A 2B 3A 3B 4A 4B 2 3 1 6 5 7 10 11 9 14 13 15 This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for D, J, and N packages. logic diagram (positive logic) G G 1A 1B 2A 2B 3A 3B 4A 4B 2 4 12 2 1 6 7 10 9 14 15 POST OFFICE BOX 655303 3 5 11 13 1Y 2Y 3Y 4Y · DALLAS, TEXAS 75265 1Y 2Y 3Y 4Y AM26LS32AC AM26LS32AC, AM26LS33AC AM26LS33AC, AM26LS32AM AM26LS32AM, AM26LS33AM AM26LS33AM QUADRUPLE DIFFERENTIAL LINE RECEIVERS SLLS115C SLLS115C ­ OCTOBER 1980 ­ REVISED APRIL 2000 schematics of inputs and outputs EQUIVALENT OF EACH DIFFERENTIAL INPUT EQUIVALENT OF EACH ENABLE INPUT VCC TYPICAL OF ALL OUTPUTS VCC 85 NOM VCC 8.3 k NOM 100 k A Input Only 960 NOM 20 k NOM Enable Output Input 960 NOM 100 k B Input Only absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage, VI: Any differential input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 V Other inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Differential input voltage, VID (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 V Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Package thermal impedance, JA (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D or N package . . . . . . . . . . . . . . . . 260°C Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: J package . . . . . . . . . . . . . . . . . . . . . 300°C Case temperature for 60 seconds, TC: FK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ­65°C to 150°C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values, except differential voltages, are with respect to the network ground terminal. 2. Differential voltage values are at the noninverting (A) input terminals with respect to the inverting (B) input terminals. 3. The package thermal impedance is calculated in accordance with JESD 51. DISSIPATION RATING TABLE PACKAGE TA 25°C POWER RATING DERATING FACTOR ABOVE TA = 25°C TA = 70°C POWER RATING TA = 125°C POWER RATING FK 1375 mW 11.0 mW/°C 880 mW 275 mW J 1375 mW 11.0 mW/°C 880 mW 275 mW POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 3 AM26LS32AC AM26LS32AC, AM26LS33AC AM26LS33AC, AM26LS32AM AM26LS32AM, AM26LS33AM AM26LS33AM QUADRUPLE DIFFERENTIAL LINE RECEIVERS SLLS115C SLLS115C ­ OCTOBER 1980 ­ REVISED APRIL 2000 recommended operating conditions MIN MAX 4.75 5 5.25 AM26LS32AM AM26LS32AM, AM26LS33AM AM26LS33AM Supply voltage VCC voltage, NOM AM26LS32AC AM26LS32AC, AM26LS33AC AM26LS33AC 4.5 5 5.5 High-level input voltage, VIH 2 V V Low-level input voltage, VIL 0.8 AM26LS32AC AM26LS32AC, AM26LS32AM AM26LS32AM ±7 AM26LS33AC AM26LS33AC, AM26LS33AM AM26LS33AM Common-mode Common mode input voltage, VIC voltage UNIT ±15 V V ­440 Low-level output current, IOL µA 8 High-level output current, IOH mA AM26LS32AC AM26LS32AC, AM26LS33AC AM26LS33AC 0 70 AM26LS32AM AM26LS32AM, AM26LS33AM AM26LS33AM Operating free-air temperature, TA free air temperature ­55 125 °C electrical characteristics over recommended ranges of VCC, VIC, and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VIT IT+ Positive-going g g input threshhold voltage VO = VOHmin IOH = ­440 µA min, 440 VIT IT­ Negative-going g g g input threshhold voltage VO = 0 45 V IOL = 8 mA 0.45 V, Vhys Enable input clamp voltage VCC = MIN, VOH High level output voltage High-level VCC =MIN, VID = 1 V, , , VI(G) = 0.8 V, IOH = ­440 µA MAX 0.2 AM26LS33A AM26LS33A 0.5 AM26LS32A AM26LS32A AM26LS33A AM26LS33A ­0.2 ­0.5 Low-level Low level output voltage VCC = MIN, VID = ­1 V, , , VI(G) = 0.8 V IOZ Off-state (high-impedance (high impedance state) output current VCC = MAX II Line input current VI = 15 V, VI = ­15 V, II(EN) IIH Enable input current IIL rI Low-level enable current Input resistance VI = 0.4 V VIC = ­15 V to 15 V, IOS Short-circuit output current§ II = ­18 mA AM26LS32AC AM26LS32AC AM26LS33AC AM26LS33AC AM26LS32AM AM26LS32AM AM26LS33AM AM26LS33AM UNIT V V 50 VOL mV ­1.5 V 2.7 V 2.5 IOL = 4 mA IOL = 8 mA 0.45 VO = 2.4 V 20 VO = 0.4 V ­20 VCC = MAX High-level enable current TYP AM26LS32A AM26LS32A Hysteresis voltage (VIT+ ­ VIT­) VIK MIN 0.4 Other input at ­10 V to 15 V 1.2 Other input at ­15 V to 10 V ­1.7 VI = 5.5 V VI = 2.7 V 100 V µA mA µA 20 One input to ac ground 12 ­15 µA ­0.36 mA ­85 mA 15 k ICC Supply current VCC = MAX, All outputs disabled 52 70 mA All typical values are at VCC = 5 V, TA = 25°C, and VIC = 0. The algebraic convention, in which the less positive (more negative) limit is designated as minimum, is used in this data sheet for threshold levels only. § Not more than one output should be shorted to ground at a time, and duration of the short circuit should not exceed one second. 4 POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 AM26LS32AC AM26LS32AC, AM26LS33AC AM26LS33AC, AM26LS32AM AM26LS32AM, AM26LS33AM AM26LS33AM QUADRUPLE DIFFERENTIAL LINE RECEIVERS SLLS115C SLLS115C ­ OCTOBER 1980 ­ REVISED APRIL 2000 switching characteristics, VCC = 5 V, TA = 25°C PARAMETER TEST CONDITIONS tPLH tPHL Propagation delay time, low-to-high-level output tPZH tPZL Output enable time to high level tPHZ tPLZ Output disable time from high level CL = 15 pF pF, Propagation delay time, high-to-low-level output CL = 5 pF pF, Output disable time from low level 35 ns 35 ns 17 22 ns 20 25 ns 21 30 ns 30 See Figure 1 MAX 22 See Figure 1 TYP 20 See Figure 1 CL = 15 pF pF, Output enable time to low level MIN UNIT 40 ns PARAMETER MEASUREMENT INFORMATION VCC Test Point RL = 2 k 2.5 V S1 From Output Under Test CL (see Note A) Input 0 0 ­2.5 V 5 k tPLH See Note B tPHL VOH Output S2 1.3 V 1.3 V VOL S1 and S2 Closed TEST CIRCUIT VOLTAGE WAVEFORMS FOR tPLH, tPHL 5 ns 90% Enable G 1.3 V 5 ns 3V 90% 10% See Note C 90% 90% 10% Output S1 Open S2 Closed 0 See Note C 3V 90% 90% 10% S1 Closed S2 Closed tPZL VOH 1.4 V S1 Closed S2 Closed 1.3 V Output VOLTAGE WAVEFORMS FOR tPHZ, tPZH S1 Closed S2 Open 3V 1.3 V 1.3 V 10% 1.3 V tPHZ 1.3 V 10% 0 0.5 V 3V 90% 1.3 V Enable G 10% tPZH 5 ns 10% 0 1.3 V 1.3 V 90% Enable G 1.3 V 10% Enable G 5 ns tPLZ 0 1.4 V VOL 0.5 V VOLTAGE WAVEFORMS FOR tPLZ, tPZL NOTES: A. CL includes probe and jig capacitance. B. All diodes are 1N3064 1N3064 or equivalent. C. Enable G is tested with G high; G is tested with G low. Figure 1 POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 5 AM26LS32AC AM26LS32AC, AM26LS33AC AM26LS33AC, AM26LS32AM AM26LS32AM, AM26LS33AM AM26LS33AM QUADRUPLE DIFFERENTIAL LINE RECEIVERS SLLS115C SLLS115C ­ OCTOBER 1980 ­ REVISED APRIL 2000 TYPICAL CHARACTERISTICS HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT HIGH-LEVEL OUTPUT VOLTAGE vs FREE-AIR TEMPERATURE 5 VID = 0.2 V TA = 25°C 4 3 VOH ­ High-Level Output Voltage ­ V VOH ­ High-Level Output Voltage ­ V 5 VCC = 5.25 V VCC = 5 V 2 VCC = 5.5 V VCC = 4.75 V 1 VCC = 4.5 V VCC = 5 V VID = 0.2 mV IOH = ­ 440 µA 4 3 2 1 0 0 ­10 ­20 ­30 ­40 ­50 0 IOH ­ High-Level Output Current ­ mA 0 10 VCC = 5.5 V and VCC = 4.5 V applies to M-suffix devices only. 20 30 40 50 60 TA ­ Free-Air Temperature ­ °C LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT LOW-LEVEL OUTPUT VOLTAGE vs FREE-AIR TEMPERATURE 0.5 0.6 VCC = 5 V TA = 25°C VID = ­ 0.2 mV 0.5 VOL ­ Low-Level Output Voltage ­ V VOL ­ Low-Level Output Voltage ­ V 80 Figure 3 Figure 2 0.4 0.3 0.2 0.1 0 VCC = 5 V VID = ­0.2 V IOL = 8 mA 0.4 0.3 0.2 0.1 0 0 15 20 25 10 IOL ­ Low-Level Output Current ­ mA 5 30 0 10 Figure 4 6 70 20 30 40 50 60 TA ­ Free-Air Temperature ­ °C Figure 5 POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 70 80 AM26LS32AC AM26LS32AC, AM26LS33AC AM26LS33AC, AM26LS32AM AM26LS32AM, AM26LS33AM AM26LS33AM QUADRUPLE DIFFERENTIAL LINE RECEIVERS SLLS115C SLLS115C ­ OCTOBER 1980 ­ REVISED APRIL 2000 TYPICAL CHARACTERISTICS OUTPUT VOLTAGE vs ENABLE G VOLTAGE OUTPUT VOLTAGE vs ENABLE G VOLTAGE 5 5 VID = 0.2 V TA = 25°C Load = 8 k to GND 4.5 VCC = 5.5 V 4 4 VCC = 5 V 3.5 VO ­ Output Voltage ­ V VO ­ Output Voltage ­ V VCC = 5 V VID = 0.2 V Load = 8 k to GND 4.5 VCC = 4.5 V 3 2.5 2 1.5 TA = 70°C TA = 25°C TA = 0°C 3.5 3 2.5 2 1.5 1 1 0.5 0.5 0 0 0 0.5 1 1.5 2 2.5 0 3 0.5 1 1.5 2 2.5 3 Enable G Voltage ­ V Enable G Voltage ­ V Figure 6 Figure 7 OUTPUT VOLTAGE vs ENABLE G VOLTAGE OUTPUT VOLTAGE vs ENABLE G VOLTAGE 6 6 VCC = 5.5 V VCC = 5 V 5 5 VO ­ Output Voltage ­ V VO ­ Output Voltage ­ V VCC = 4.5 V 4 3 2 1 0 0.5 1 TA = 70°C 3 2 1 VID = ­0.2 V Load = 1 k to VCC TA = 25°C 0 TA = 0°C TA = 25°C 4 1.5 2 2.5 3 VCC = 5 V VID = ­0.2 V Load = 1 k to VCC 0 0 0.5 Enable G Voltage ­ V 1 1.5 2 2.5 3 Enable G Voltage ­ V Figure 8 Figure 9 POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 7 AM26LS32AC AM26LS32AC, AM26LS33AC AM26LS33AC, AM26LS32AM AM26LS32AM, AM26LS33AM AM26LS33AM QUADRUPLE DIFFERENTIAL LINE RECEIVERS SLLS115C SLLS115C ­ OCTOBER 1980 ­ REVISED APRIL 2000 TYPICAL CHARACTERISTICS AM26LS32A AM26LS32A AM26LS33A AM26LS33A OUTPUT VOLTAGE vs DIFFERENTIAL INPUT VOLTAGE OUTPUT VOLTAGE vs DIFFERENTIAL INPUT VOLTAGE 5 5 VO ­ Output Voltage ­ V 4 VCC = 5 V, IO = 0, TA = 25°C 4.5 4 VIC = ­7 V 3.5 VIC = 0 VO ­ Output Voltage ­ V 4.5 VCC = 5 V IO = 0 TA = 25°C VIC = 7V 3 2.5 2 VIT­ VIT+ 1.5 VIT­ VIT+ VIT­ VIT+ VIC = ­15 V 3.5 VIC = 0 VIC = 15 V 3 2.5 2 VIT­ VIT+ 1.5 1 VIT­ VIT+ VIT+ 1 0.5 VIT­ 0.5 0 ­200 ­150 ­100 ­50 50 0 100 0 ­200 ­150 ­100 ­50 150 200 VID ­ Differential Input Voltage ­ mV 0 50 100 150 200 VID ­ Differential Input Voltage ­ mV Figure 11 Figure 10 INPUT CURRENT vs INPUT VOLTAGE 4 3 I I ­ Input Current ­ mA 2 1 0 VCC = 0 ­1 ­2 VCC = 5 V The Unshaded Area Shows Requirements of Paragraph 4.2.1 of ANSI Standards EIA/TIA-422-B EIA/TIA-422-B and EIA/TIA-423-B EIA/TIA-423-B. ­3 ­4 ­25 ­20 ­15 ­10 ­5 0 5 10 15 VI ­ Input Voltage ­ V Figure 12 8 POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 20 25 AM26LS32AC AM26LS32AC, AM26LS33AC AM26LS33AC, AM26LS32AM AM26LS32AM, AM26LS33AM AM26LS33AM QUADRUPLE DIFFERENTIAL LINE RECEIVERS SLLS115C SLLS115C ­ OCTOBER 1980 ­ REVISED APRIL 2000 APPLICATION INFORMATION 1/4 AM26LS31AC AM26LS31AC 1/4 AM26LS32AC AM26LS32AC Data In RT 1/4 AM26LS32AC AM26LS32AC Data Out 1/4 AM26LS33AC AM26LS33AC Data Out Data Out RT equals the characteristic impedance of the line. Figure 13. Circuit With Multiple Receivers POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 9 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof. Copyright © 2000, Texas Instruments Incorporated