SLLA076 HFS9003 TIA/EIA-644 4PR24 6236B P6247 E3516A P6243 - Datasheet Archive

 

SLLA076 - March 2000 Logic Input Thresholds and the Effects on Output Jitter Steve Corrigan and Mark Morgan Advanced Analog

 

Application Report SLLA076 SLLA076 - March 2000 Logic Input Thresholds and the Effects on Output Jitter Steve Corrigan and Mark Morgan Advanced Analog Products ABSTRACT Differential drivers are subject to a severe jitter increase when the upper and lower input voltage levels are not kept symmetrical about the input voltage trigger threshold. After a brief description of this common condition, bench characterization of the resulting jitter is presented for varied upper and lower voltage levels. Contents Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Unsymmetrical Input Voltage Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Jitter Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Test Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Test Equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2 3 6 6 7 8 8 List of Figures 1 Symmetrical Input Voltage Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Unsymmetrical Input Voltage Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Output Duty Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Altered Driver Output Duty Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Symmetrical Driver Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Driver Output From an Unbalanced High-Input Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Driver Output From an Unbalanced Low-Level Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Altered Duty Cycle With Undistorted Triggering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Typical Eye Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 The Test Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2 2 3 4 4 5 6 7 8 1 SLLA076 SLLA076 Introduction An extremely high jitter condition occurs in any type of differential connection when the logic levels applied to a differential driver are not symmetrical about the the driver's input voltage trigger threshold. If this occurs, jitter is distributed completely through the transmission system and is present at a receiver's output. This paper addresses the excessive jitter that results from varying the upper and lower input voltage levels around the trigger threshold of a differential driver. Unsymmetrical Input Voltage Levels Figure 1 displays an input voltage level that is symmetrical about the input voltage trigger level of a differential driver. Ideally, the time elapsed as the input voltage traverses the logic input signal from (1) to (2) is equal to the time elapsed during the excursion between trigger levels from (2) to (3). This equal time between triggers is the ideal unit interval (UI), and becomes corrupted when input logic levels are unsymmetrical about the driver input voltage threshold as displayed in Figure 2. Since the voltage level above the trigger threshold is greater in magnitude than the voltage below the threshold, the time it takes to complete the voltage excursion in Figure 2 from (4) to (5) is no longer equal to the time excursion from (5) to (6). The opposite is true when the voltage level below the voltage threshold is greater in magnitude than the voltage above the threshold. When the balance above or below a trigger threshold is changed, the duty cycle of the driver output signal changes as well. This condition leads to an alteration of the UI by causing the driver outputs to trigger both ahead of and behind the ideal UI as presented in Figure 3 where the voltage imbalance is above the trigger threshold. 1 2 High Input Level 3 Driver Trigger Level Low Input Level t(1­2) t(2­3) t(1­2) = t(2­3) Figure 1. Symmetrical Input Voltage Levels High Input Level 4 6 5 Driver Trigger Level Low Input Level t(4­5) t(5­6) t(4­5) t(5­6) Figure 2. Unsymmetrical Input Voltage Levels High Input Level Driver Trigger Level Low Input Level Trigger Points Driver output Figure 3. Output Duty Cycle 2 Logic Input Thresholds and the Effects on Output Jitter SLLA076 SLLA076 This duty cycle alteration can be observed at the output of a differential driver with a 50% duty cycle pulse input. Figure 4 displays the pulse width modulation that results from unsymmetrical voltage level inputs. When applying a pseudo-random binary sequence (PRBS) data pattern as the input signal, this modulation is reflected in the eye pattern of the differential output as a shift in the transition crossing points. The amount of distortion is also effected by an input signal's transition time, since a driver with a slow rise time amplifies the effect of an unsymmetrical switching point. Driver Output with 50% Duty Cycle Pulse Input Figure 4. Altered Driver Output Duty Cycle Results Figures 5 presents an LVDS driver output with an input high level of 2 V and a input low level of 800 mV that is balanced around the 1.4 V trigger threshold of the driver (600 mV above and 600 mV below). The high level is then increased to 3.3 V while maintaining the 800 mV low level for Figure 6. Next in Figure 7, the high level is returned to 2 V, but the low level is reduced to 0 V. Notice that for a signaling rate of 200 Mbps with 800 ns rise/fall times, jitter has increased from 360 ps in Figure 5, to 610 ps in Figures 6 and 560 ps in Figure 7, representing increases of 69% and 56% respectively. Logic Input Thresholds and the Effects on Output Jitter 3 SLLA076 SLLA076 Driver Output With Balanced NRZ PRBS Input Figure 5. Symmetrical Driver Output Driver Output With UnBalanced NRZ PRBS Input Figure 6. Driver Output From an Unbalanced High-Input Level 4 Logic Input Thresholds and the Effects on Output Jitter SLLA076 SLLA076 Driver Output With UnBalanced NRZ PRBS Input Figure 7. Driver Output From an Unbalanced Low-Level Input Note that the common mode voltage of the driver output is not affected. Figure 8 shows that even though the duty cycle has been distorted, the crossover points are still in the center of the waveform. The figure displays both channels of the driver output while being driven with the 50% duty cycle pulse input and monitored with individual (not differential) probes. The most important effect of duty cycle modulation is output jitter and its impact on the highest signaling rate possible. As the input frequency is increased, the pulse width decreases and the distortion becomes a larger percentage of the output unit interval. A frequency is ultimately reached where the distortion is severe enough that noise margins and setup times are violated. Therefore, centering the input waveform about an input trigger level ensures a balanced output and maximized signaling rate. Logic Input Thresholds and the Effects on Output Jitter 5 SLLA076 SLLA076 Driver Output with 50% Duty Cycle Pulse Input Figure 8. Altered Duty Cycle With Undistorted Triggering Measurements A control measurement is first taken with the input voltage levels adjusted in the Tektronix HFS9003 HFS9003 signal generator to a symmetrical 2 V high level and 800 mV low level. At these settings, each level is 600 mV above and below the 1.4 V trigger threshold of the LVDS driver, and the resulting balanced output is displayed in Figure 5. Next, the high level is adjusted to 3.3 V for Figure 6, then returned back to 2 V and the low level lowered from 800 mV to 0 V for Figure 7. For Figures 4 and 8, the high level input of a 50% duty cycle pulse is adjusted to 2 V and the low level to 0 V. Jitter Measurement The eye pattern is a useful tool for measuring the overall signal quality. It includes all of the effects of systemic and random distortion, and shows the time during which the signal may be considered valid. A typical eye pattern is illustrated in Figure 9 with the significant attributes identified. 6 Logic Input Thresholds and the Effects on Output Jitter SLLA076 SLLA076 Height abs. jitter Width Unit Interval Figure 9. Typical Eye Pattern Several characteristics of the eye pattern indicate the quality of a differential signal. The height of the eye above or below the receiver threshold level at the sampling instant is the noise margin of the system, and the spread of the transitions across the receiver thresholds measures the absolute jitter of the data signal. The signal rise and fall times can be measured relative to the 0% and 100% levels provided by the long series of low and high levels. Jitter is the time frame during which the logic state transition of a signal occurs. The jitter may be given either as an absolute number or as a percentage with reference to the unit interval (UI). The UI or bit length equals the reciprocal value of the signaling rate, and the time during which a logic state is valid is just the UI minus the jitter. Percent jitter (the jitter time divided by the UI times100) is more commonly used and represents the portion of UI during which a logic state should be considered indeterminate. Test Setup The TIA/EIA-644 TIA/EIA-644 LVDS standard specifies the use of 90 to 132 transmission lines (although other values may also be used in nonstandard applications), and the one meter cable used for this set up is Belden-M DataTwistTM (stock number 1583A CM 4PR24 4PR24) 100 UTP CAT5. Figure 10 displays the circuit under consideration with the transmission line being probed at the output of both the LVDS driver and receiver. Logic Input Thresholds and the Effects on Output Jitter 7 SLLA076 SLLA076 TEKTRONIX HFS­9003 Pattern Generator Trigger Input TEKTRONIX 784D Oscilloscope HP 6236B 6236B Power Supply TEKTRONIX P6247 P6247 Differential Probes 100 HP E3516A E3516A Power Supply One Meter UTP CAT5 LVDS Driver BELDEN ­ M Data Twist LVDS Receiver Figure 10. The Test Setup Test Equipment HP E3516A E3516A and HP 6236B 6236B dc power supplies provide the required supply voltage of 3.3 V for the `LVDS driver and receiver in the circuit. For the eye pattern distortion examples, a Tektronix HFS9003 HFS9003 signal generator is employed as a nonreturn-to-zero (NRZ), pseudo-random binary sequence (PRBS) signal source for the driver and is adjusted as follows for the balanced input: · Pattern: NRZ, PRBS · Input high level: 2V · Input low level: 0.8 V · Transition time: 800 ps For the duty cycle alteration examples, the HFS9003 HFS9003 is adjusted to a 50% duty cycle pulse, then the input voltage levels are adjusted out of symmetry as previously mentioned. At high signaling rates, the influence of equipment used to measure a signal of concern should be minimized. For differential tests, a Tektronix 784D oscilloscope and Tektronix P6247 P6247 differential probes are used. Each has a bandwidth of 1 GHz and the probe capacitance is less than 1 pF. For the pulse input test of Figures 4 and 8, individual Tektronix P6243 P6243 1 GHz probes are used to monitor each side of the differential output. Conclusions Balanced high and low input voltage levels create a 50% duty cycle at the output of a differential driver that is unaffected by signaling rate. However, any variation of an equal voltage magnitude on either side of a triggering threshold changes the balance of the duty cycle and generates noise. This unbalanced duty cycle also reduces bus data setup times and limits top speed operation. If necessary, a simple resistor divider network can accomplish any voltage level adjustment required to achieve the threshold balance. 8 Logic Input Thresholds and the Effects on Output Jitter IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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