TPIC6B596 SLIS095A TPIC6B596DWG4 TPIC6B596DWR TPIC6B596DWRG4 TPIC6B596N - Datasheet Archive

 

POWER LOGIC 8BIT SHIFT REGISTER SLIS095A - MARCH 2000 - REVISED MAY 2005 D Low rDS(on) . . . 5 D Avalanche Energy . . . 30 mJ D

 

TPIC6B596 TPIC6B596 POWER LOGIC 8BIT SHIFT REGISTER SLIS095A SLIS095A - MARCH 2000 - REVISED MAY 2005 D Low rDS(on) . . . 5 D Avalanche Energy . . . 30 mJ D Eight Power DMOS-Transistor Outputs of D D D D D DW OR N PACKAGE (TOP VIEW) NC VCC SER IN DRAIN0 DRAIN1 DRAIN2 DRAIN3 SRCLR G GND 150-mA Continuous Current 500-mA Typical Current-Limiting Capability Output Clamp Voltage . . . 50 V Enhanced Cascading for Multiple Stages All Registers Cleared With Single Input Low Power Consumption description The TPIC6B596 TPIC6B596 is a monolithic, high-voltage, medium-current power 8-bit shift register designed for use in systems that require relatively high load power. The device contains a built-in voltage clamp on the outputs for inductive transient protection. Power driver applications include relays, solenoids, and other mediumcurrent or high-voltage loads. 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 NC GND SER OUT DRAIN7 DRAIN6 DRAIN5 DRAIN4 SRCK RCK GND NC - No internal connection logic symbol G RCK SRCLR SRCK 9 EN3 12 8 13 C2 R SRG8 C1 This device contains an 8-bit serial-in, parallel-out 4 3 DRAIN0 2 1D SER IN shift register that feeds an 8-bit D-type storage 5 DRAIN1 register. Data transfers through both the shift and 6 storage registers on the rising edge of the DRAIN2 7 shift-register clock (SRCK) and the register clock DRAIN3 (RCK), respectively. The storage register 14 DRAIN4 transfers data to the output buffer when shift15 DRAIN5 register clear (SRCLR) is high. When SRCLR is 16 DRAIN6 low, all registers in the device are cleared. When 17 output enable (G) is held high, all data in the DRAIN7 2 18 output buffers is held low and all drain outputs are SER OUT off. When G is held low, data from the storage This symbol is in accordance with ANSI/IEEE Std 91-1984 register is transparent to the output buffers. When and IEC Publication 617-12. data in the output buffers is low, the DMOStransistor outputs are off. When data is high, the DMOS-transistor outputs have sink-current capability. The serial output (SER OUT) is clocked out of the device on the falling edge of SRCK to provide additional hold time for cascaded applications. This will provide improved performance for applications where clock signals may be skewed, devices are not located near one another, or the system must tolerate electromagnetic interference. Outputs are low-side, open-drain DMOS transistors with output ratings of 50 V and 150-mA continuous sinkcurrent capability. Each output provides a 500-mA typical current limit at TC = 25°C. The current limit decreases as the junction temperature increases for additional device protection. The TPIC6B596 TPIC6B596 is characterized for operation over the operating case temperature range of -40°C to 125°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2000 - 2005, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 1 TPIC6B596 TPIC6B596 POWER LOGIC 8BIT SHIFT REGISTER SLIS095A SLIS095A - MARCH 2000 - REVISED MAY 2005 logic diagram (positive logic) G RCK SRCLR 9 12 4 8 D D C2 CLR D C1 D C2 CLR CLR D C1 D C2 CLR CLR D C1 D C2 CLR CLR D C1 D C2 CLR CLR D SER IN 13 C1 CLR SRCK 5 3 C1 C1 C1 CLR DRAIN3 DRAIN4 DRAIN5 D C2 CLR 15 CLR D 14 DRAIN2 D C2 CLR 7 CLR D 6 DRAIN1 D C2 CLR 16 17 10, 11, 19 D C1 18 CLR 2 DRAIN0 POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 SER OUT DRAIN6 DRAIN7 GND TPIC6B596 TPIC6B596 POWER LOGIC 8BIT SHIFT REGISTER SLIS095A SLIS095A - MARCH 2000 - REVISED MAY 2005 schematic of inputs and outputs EQUIVALENT OF EACH INPUT TYPICAL OF ALL DRAIN OUTPUTS VCC DRAIN 50 V Input 25 V 20 V 12 V GND GND absolute maximum ratings over recommended operating case temperature range (unless otherwise noted) Logic supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Logic input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 7 V Power DMOS drain-to-source voltage, VDS (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 V Continuous source-to-drain diode anode current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 mA Pulsed source-to-drain diode anode current (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 A Pulsed drain current, each output, all outputs on, ID, TC = 25°C (see Note 3) . . . . . . . . . . . . . . . . . . . 500 mA Continuous drain current, each output, all outputs on, ID, TC = 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 mA Peak drain current single output, IDM,TC = 25°C (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 mA Single-pulse avalanche energy, EAS (see Figure 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mJ Avalanche current, IAS (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 mA Continuous total dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to 150°C Operating case temperature range, TC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to 125°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values are with respect to GND. 2. Each power DMOS source is internally connected to GND. 3. Pulse duration 100 µs and duty cycle 2%. 4. DRAIN supply voltage = 15 V, starting junction temperature (TJS) = 25°C, L = 200 mH, IAS = 0.5 A (see Figure 4). DISSIPATION RATING TABLE PACKAGE TC 25°C POWER RATING DW N DERATING FACTOR ABOVE TC = 25°C TC = 125°C POWER RATING 1389 mW 11.1 mW/°C 278 mW 1050 mW 10.5 mW/°C 263 mW POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 3 TPIC6B596 TPIC6B596 POWER LOGIC 8BIT SHIFT REGISTER SLIS095A SLIS095A - MARCH 2000 - REVISED MAY 2005 recommended operating conditions MIN 4.5 Logic supply voltage, VCC High-level input voltage, VIH MAX UNIT 5.5 V 0.85 VCC Low-level input voltage, VIL V 0.15 VCC Pulsed drain output current, TC = 25°C, VCC = 5 V (see Notes 3 and 5) V 500 mA -500 Setup time, SER IN high before SRCK, tsu (see Figure 2) 15 ns Hold time, SER IN high after SRCK, th (see Figure 2) 15 ns Pulse duration, tw (see Figure 2) 40 Operating case temperature, TC -40 ns °C 125 NOTES: 3. Pulse duration 100 µs and duty cycle 2%. 5. Technique should limit TJ - TC to 10°C maximum. electrical characteristics, VCC = 5 V, TC = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS V(BR)DSX Drain-to-source breakdown voltage ID = 1 mA VSD Source-to-drain diode forward voltage IF = 100 mA VOH High-level output voltage, SER OUT VOL Low-level output voltage, SER OUT MIN IIH IIL TYP MAX 50 V 0.85 IOH = - 20 µA, VCC = 4.5 V IOH = - 4 mA, VCC = 4.5 V IOL = 20 µA, VCC = 4.5 V High-level input current IOL = 4 mA, VCC = 5.5 V, Low-level input current VCC = 5.5 V, 4.4 1 4.2 V 0.005 0.1 0.3 0.5 VI = 0 V 1 µA -1 µA All outputs off 20 100 All outputs on 150 300 0.4 5 ICC Logic supply current VCC = 5.5 V ICC(FRQ) Logic supply current at frequency fSRCK = 5 MHz, CL = 30 pF, All outputs off, See Figures 2 and 6 IN Nominal current IDSX Off-state drain current rDS(on) Static drain-source on-state resistance VDS(on) = 0.5 V, IN = ID, TC = 85°C VDS = 40 V, VCC = 5.5 V V 4.49 4 VCC = 4.5 V VI = VCC UNIT See Notes 5, 6, and 7 90 VCC = 5.5 V, TC = 125°C VCC = 4.5 V ID = 100 mA, VCC = 4.5 V ID = 350 mA, TC = 125°C, See Notes 5 and 6 and Figures 7 and 8 mA mA 0.1 VDS = 40 V, ID = 100 mA, A µA 5 0.15 8 4.2 5.7 6.8 9.5 µA A VCC = 4.5 V 5.5 8 NOTES: 5. Technique should limit TJ - TC to 10°C maximum. 6. These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts. 7. Nominal current is defined for a consistent comparison between devices from different sources. It is the current that produces a voltage drop of 0.5 V at TC = 85°C. 4 POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 TPIC6B596 TPIC6B596 POWER LOGIC 8BIT SHIFT REGISTER SLIS095A SLIS095A - MARCH 2000 - REVISED MAY 2005 switching characteristics, VCC = 5 V, TC = 25°C PARAMETER TEST CONDITIONS tPLH tPHL Rise time, drain output TYP Propagation delay time, low-to-high-level output from G tr tf MIN MAX UNIT 150 tpd Propagation delay time, SRCK to SEROUT CL = 30 pF, See Figure 2 f(SRCK) Serial clock frequency CL = 30 pF, See Note 8 ta trr Reverse-recovery-current rise time ns ns ID = 100 mA, ID = 100 mA, 10 MHz 100 IF = 100 mA, di/dt = 20 A/µs, See Notes 5 and 6 and Figure 3 Reverse-recovery time ns 15 Fall time, drain output ns 200 CL = 30 pF, ID = 100 mA, See Figures 1, 2, and 9 ns 90 200 Propagation delay time, high-to-low-level output from G ns 300 NOTES: 5. Technique should limit TJ - TC to 10°C maximum. 6. These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts. 8. This is the maximum serial clock frequency assuming cascaded operation where serial data is passed from one stage to a second stage. The clock period allows for SRCK SEROUT propagation delay and setup time plus some timing margin. thermal resistance PARAMETER RJA TEST CONDITIONS DW package Thermal resistance, junction-to-ambient MIN 90 All 8 outputs with equal power N package MAX 95 UNIT °C/W PARAMETER MEASUREMENT INFORMATION 5V 24 V 7 2 8 13 Word Generator (see Note A) 3 12 9 SRCLR SRCK 5 4 3 2 1 0 DRAIN 4 -7, 14 -17 Output G 0V 5V SER IN CL = 30 pF (see Note B) RCK 5V G RL = 235 DUT 5V 0V ID VCC SER IN 6 SRCK 0V 5V RCK 0V 5V SRCLR 0V GND 10, 11, 19 24 V DRAIN1 0.5 V VOLTAGE WAVEFORMS TEST CIRCUIT NOTES: A. The word generator has the following characteristics: tr 10 ns, tf 10 ns, tw = 300 ns, pulsed repetition rate (PRR) = 5 kHz, ZO = 50 . B. CL includes probe and jig capacitance. Figure 1. Resistive-Load Test Circuit and Voltage Waveforms POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 5 TPIC6B596 TPIC6B596 POWER LOGIC 8BIT SHIFT REGISTER SLIS095A SLIS095A - MARCH 2000 - REVISED MAY 2005 PARAMETER MEASUREMENT INFORMATION 5V G 50% 50% 0V 5V tPLH 24 V Output 2 8 13 Word Generator (see Note A) 3 12 9 V SRCLR CC SRCK ID 4 -7, 14 -17 DUT 90% 24 V 90% 10% 10% tr RL = 235 SWITCHING TIMES Output 5V 50% SRCK 0V CL = 30 pF (see Note B) RCK 0.5 V tf DRAIN SER IN G tPHL tsu th GND 5V 10, 11, 19 SER IN 50% 50% 0V TEST CIRCUIT tw INPUT SETUP AND HOLD WAVEFORMS SRCK 50% 50% tpd SER OUT 50% tpd 50% SER OUT PROPAGATION DELAY WAVEFORM NOTES: A. The word generator has the following characteristics: tr 10 ns, tf 10 ns, tw = 300 ns, pulsed repetition rate (PRR) = 5 kHz, ZO = 50 . B. CL includes probe and jig capacitance. Figure 2. Test Circuit, Switching Times, and Voltage Waveforms 6 POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 TPIC6B596 TPIC6B596 POWER LOGIC 8BIT SHIFT REGISTER SLIS095A SLIS095A - MARCH 2000 - REVISED MAY 2005 PARAMETER MEASUREMENT INFORMATION TP K DRAIN Circuit Under Test 0.1 A 2500 µF 250 V di/dt = 20 A/µs + 25 V L = 1 mH IF (see Note A) IF - 0 TP A 25% of IRM t2 t1 t3 Driver IRM RG VGG (see Note B) ta 50 trr TEST CIRCUIT CURRENT WAVEFORM NOTES: A. The DRAIN terminal under test is connected to the TP K test point. All other terminals are connected together and connected to the TP A test point. B. The VGG amplitude and RG are adjusted for di/dt = 20 A/µs. A VGG double-pulse train is used to set IF = 0.1 A, where t1 = 10 µs, t2 = 7 µs, and t3 = 3 µs. Figure 3. Reverse-Recovery-Current Test Circuit and Waveforms of Source-to-Drain Diode 5V 15 V tw 2 8 V SRCLR CC 10.5 Word Generator (see Note A) 3 12 9 DUT 4 -7, 14 -17 DRAIN RCK See Note B 200 mH SER IN G 5V Input ID 13 SRCK tav 0V IAS = 0.5 A ID VDS GND V(BR)DSX = 50 V MIN VDS 10, 11, 19 SINGLE-PULSE AVALANCHE ENERGY TEST CIRCUIT VOLTAGE AND CURRENT WAVEFORMS NOTES: A. The word generator has the following characteristics: tr 10 ns, tf 10 ns, ZO = 50 . B. Input pulse duration, tw, is increased until peak current IAS = 0.5 A. Energy test level is defined as EAS = IAS × V(BR)DSX × tav/2 = 30 mJ. Figure 4. Single-Pulse Avalanche Energy Test Circuit and Waveforms POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 7 TPIC6B596 TPIC6B596 POWER LOGIC 8BIT SHIFT REGISTER SLIS095A SLIS095A - MARCH 2000 - REVISED MAY 2005 TYPICAL CHARACTERISTICS PEAK AVALANCHE CURRENT vs TIME DURATION OF AVALANCHE SUPPLY CURRENT vs FREQUENCY 10 2.5 VCC = 5 V TC = - 40°C to 125°C 4 I CC - Supply Current - mA IAS - Peak Avalanche Current - A TC = 25°C 2 1 0.4 2 1.5 1 0.5 0.2 0.1 0.1 0.2 0.4 1 2 4 0 0.1 10 1 tav - Time Duration of Avalanche - ms Figure 5 14 TC = 125°C 12 10 8 6 TC = 25°C 4 TC = - 40°C 2 0 0 100 200 300 400 500 ID - Drain Current - mA 600 700 STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE vs LOGIC SUPPLY VOLTAGE r DS(on) - Static Drain-to-Source On-State Resistance - r DS(on) - Drain-to-Source On-State Resistance - VCC = 5 V See Note A 16 8 ID = 100 mA See Note A 7 TC = 125°C 6 5 TC = 25°C 4 3 TC = - 40°C 2 1 0 4 4.5 5 5.5 Figure 8 POST OFFICE BOX 655303 6 6.5 VCC - Logic Supply Voltage - V Figure 7 8 100 Figure 6 DRAIN-TO-SOURCE ON-STATE RESISTANCE vs DRAIN CURRENT 18 10 f - Frequency - MHz · DALLAS, TEXAS 75265 7 TPIC6B596 TPIC6B596 POWER LOGIC 8BIT SHIFT REGISTER SLIS095A SLIS095A - MARCH 2000 - REVISED MAY 2005 TYPICAL CHARACTERISTICS SWITCHING TIME vs CASE TEMPERATURE 300 ID = 100 mA See Note A tf Switching Time - ns 250 tr 200 tPLH 150 tPHL 100 50 -50 -25 0 25 50 75 100 TC - Case Temperature - °C 125 Figure 9 NOTE A: Technique should limit TJ - TC to 10°C maximum. POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 9 TPIC6B596 TPIC6B596 POWER LOGIC 8BIT SHIFT REGISTER SLIS095A SLIS095A - MARCH 2000 - REVISED MAY 2005 THERMAL INFORMATION I D - Maximum Continuous Drain Current of Each Output - A 0.45 VCC = 5 V 0.4 0.35 0.3 0.25 TC = 25°C 0.2 0.15 TC = 100°C 0.1 TC = 125°C 0.05 0 1 2 3 4 5 6 7 8 I D - Maximum Peak Drain Current of Each Output - A MAXIMUM PEAK DRAIN CURRENT OF EACH OUTPUT vs NUMBER OF OUTPUTS CONDUCTING SIMULTANEOUSLY MAXIMUM CONTINUOUS DRAIN CURRENT OF EACH OUTPUT vs NUMBER OF OUTPUTS CONDUCTING SIMULTANEOUSLY 0.5 d = 10% 0.45 d = 20% 0.4 0.35 d = 50% 0.3 0.25 d = 80% 0.2 0.15 VCC = 5 V TC = 25°C d = tw/tperiod = 1 ms/tperiod 0.1 0.05 0 1 2 3 4 N - Number of Outputs Conducting Simultaneously Figure 11 Figure 10 Revision History DATE REV PAGE 5/18/05 A 5 3/2000 * SECTION Figure 1 DESCRIPTION Changed SRCLR timing diagram Original reversion NOTE: Page numbers for previous revisions may differ from page numbers in the current version. 10 POST OFFICE BOX 655303 5 6 7 8 N - Number of Outputs Conducting Simultaneously · DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 28-May-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TPIC6B596DWG4 TPIC6B596DWG4 ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TBD CU NIPDAU Level-1-220C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU N / A for Pkg Type TPIC6B596DWR TPIC6B596DWR ACTIVE SOIC DW 20 2000 TPIC6B596DWRG4 TPIC6B596DWRG4 ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) TPIC6B596N TPIC6B596N ACTIVE PDIP N 20 20 Pb-Free (RoHS) Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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