TPIC6B273 SLIS031 TPIC6B273DW TPIC6B273DWG4 TPIC6B273DWR TPIC6B273DWRG4 - Datasheet Archive

 

POWER LOGIC OCTAL D-TYPE LATCH SLIS031 ­ APRIL 1994 ­ REVISED JULY 1995 D D D D D D Low rDS(on) . . . 5 Typical Avalanche

 

TPIC6B273 TPIC6B273 POWER LOGIC OCTAL D-TYPE LATCH SLIS031 SLIS031 ­ APRIL 1994 ­ REVISED JULY 1995 D D D D D D Low rDS(on) . . . 5 Typical Avalanche Energy . . . 30 mJ Eight Power DMOS-Transistor Outputs of 150-mA Continuous Current 500-mA Typical Current-Limiting Capability Output Clamp Voltage . . . 50 V Low Power Consumption DW OR N PACKAGE (TOP VIEW) CLR D1 D2 DRAIN1 DRAIN2 DRAIN3 DRAIN4 D3 D4 GND description The TPIC6B273 TPIC6B273 is a monolithic, high-voltage, medium-current, power logic octal D-type latch with DMOS-transistor outputs designed for use in systems that require relatively high load power. The device contains a built-in voltage clamp on the outputs for inductive transient protection. Power driver applications include relays, solenoids, and other medium-current or high-voltage loads. The TPIC6B273 TPIC6B273 contains eight positive-edgetriggered D-type flip-flops with a direct clear input. Each flip-flop features an open-drain power DMOS-transistor output. Outputs are low-side, open-drain DMOS transistors with output ratings of 50 V and 150-mA continuous sink-current capability. Each output provides a 500-mA typical current limit at TC = 25°C. The current limit decreases as the junction temperature increases for additional device protection. 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 VCC D8 D7 DRAIN8 DRAIN7 DRAIN6 DRAIN5 D6 D5 CLK logic symbol CLR CLK D1 D2 D3 D4 When clear (CLR) is high, information at the D inputs meeting the setup time requirements is transferred to the DRAIN outputs on the positivegoing edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock input (CLK) is at either the high or low level, the D input signal has no effect at the output. An asynchronous CLR is provided to turn all eight DMOS-transistor outputs off. When data is low for a given output, the DMOS-transistor output is off. When data is high, the DMOS-transistor output has sink-current capability. 1 D5 D6 D7 D8 1 R 11 C1 2 4 1D 3 5 8 6 9 7 12 14 13 15 18 16 19 17 DRAIN1 DRAIN2 DRAIN3 DRAIN4 DRAIN5 DRAIN6 DRAIN7 DRAIN8 This symbol is in accordance with ANSI/IEEE Standard 91-1984 and IEC Publication 617-12. FUNCTION TABLE (each channel) INPUTS CLR CLK D OUTPUT DRAIN L H H H X L X H L X H L H Latched H = high level, L = low level, X = irrelevant The TPIC6B273 TPIC6B273 is characterized for operation over the operating case temperature range of ­ 40°C to 125°C. Copyright © 1997, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 1 TPIC6B273 TPIC6B273 POWER LOGIC OCTAL D-TYPE LATCH SLIS031 SLIS031 ­ APRIL 1994 ­ REVISED JULY 1995 logic diagram (positive logic) 4 CLR D1 CLK 1 2 11 DRAIN1 CLR 1D C1 5 DRAIN2 CLR D2 3 1D C1 6 DRAIN3 CLR D3 8 1D C1 7 DRAIN4 CLR D4 9 1D C1 14 DRAIN5 CLR D5 12 1D C1 15 DRAIN6 CLR D6 13 1D C1 16 DRAIN7 CLR D7 18 1D C1 17 DRAIN8 CLR D8 19 1D 10 C1 2 POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 GND TPIC6B273 TPIC6B273 POWER LOGIC OCTAL D-TYPE LATCH SLIS031 SLIS031 ­ APRIL 1994 ­ REVISED JULY 1995 schematic of inputs and outputs EQUIVALENT OF EACH INPUT TYPICAL OF ALL DRAIN OUTPUTS VCC DRAIN 50 V Input 25 V 20 V 12 V GND GND absolute maximum ratings over recommended operating case temperature range (unless otherwise noted) Logic supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Logic input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ­ 0.3 V to 7 V Power DMOS drain-to-source voltage, VDS (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 V Continuous source-to-drain diode anode current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 mA Pulsed source-to-drain diode anode current (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 A Pulsed drain current, each output, all outputs on, ID, TC = 25°C (see Note 3) . . . . . . . . . . . . . . . . . . . 500 mA Continuous drain current, each output, all outputs on, ID, TC = 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 mA Peak drain current single output, IDM,TC = 25°C (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 mA Single-pulse avalanche energy, EAS (see Figure 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mJ Avalanche current, IAS (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 mA Continuous total dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ­ 40°C to 150°C Operating case temperature range, TC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ­ 40°C to 125°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ­ 65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values are with respect to GND. 2. Each power DMOS source is internally connected to GND. 3. Pulse duration 100 µs and duty cycle 2%. 4. DRAIN supply voltage = 15 V, starting junction temperature (TJS) = 25°C, L = 200 mH, IAS = 0.5 A (see Figure 4). DISSIPATION RATING TABLE PACKAGE TC 25°C POWER RATING DW N DERATING FACTOR ABOVE TC = 25°C TC = 125°C POWER RATING 1389 mW 11.1 mW/°C 278 mW 1050 mW 10.5 mW/°C 263 mW POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 3 TPIC6B273 TPIC6B273 POWER LOGIC OCTAL D-TYPE LATCH SLIS031 SLIS031 ­ APRIL 1994 ­ REVISED JULY 1995 recommended operating conditions MIN High-level input voltage, VIH MAX 4.5 Logic supply voltage, VCC 5.5 UNIT V 0.85 VCC Low-level input voltage, VIL V 0.15 VCC Pulsed drain output current, TC = 25°C, VCC = 5 V (see Notes 3 and 5) V 500 mA ­ 500 Setup time, D high before CLK, tsu (see Figure 2) 20 ns Hold time, D high after CLK, th (see Figure 2) 20 ns Pulse duration, tw (see Figure 2) 40 Operating case temperature, TC ­ 40 ns °C 125 electrical characteristics, VCC = 5 V, TC = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS V(BR)DSX Drain-to-source breakdown voltage ID = 1 mA VSD Source-to-drain diode forward voltage MIN IF = 100 mA TYP MAX 50 V 0.85 IIH IIL High-level input current Low-level input current VCC = 5.5 V, VCC = 5.5 V, ICC Logic supply current VCC = 5 5 V 5.5 IN Nominal current VDS(on) = 0.5 V, IN = ID, See Notes 5, 6, and 7 IDSX Off state drain current Off-state VDS = 40 V, VDS = 40 V, VCC = 5.5 V VCC = 5.5 V, rDS(on) Static drain-to-source on-state resistance ID = 100 mA, ID = 100 mA, TC = 125°C VCC = 4.5 V VCC = 4.5 V, ID = 350 mA, UNIT 1 VCC = 4.5 V V µA ­1 VI = VCC VI = 0 1 µA All outputs off 20 100 All outputs on 150 300 TC = 85°C, 90 mA 0.1 8 4.2 5.7 6.8 9.5 5.5 See Notes 5 and 6 and Figures 6 and 7 5 0.15 TC = 125°C µA 8 TYP MAX µA switching characteristics, VCC = 5 V, TC = 25°C PARAMETER TEST CONDITIONS MIN UNIT tPLH tPHL Propagation delay time, low-to-high-level output from CLK 150 ns Propagation delay time, high-to-low-level output from CLK 90 ns tr tf Rise time, drain output 200 ns 200 ns ta trr Reverse-recovery-current rise time Fall time, drain output Reverse-recovery time NOTES: 3. 5. 6. 7. 4 CL = 30 pF, , ID = 100 mA, , See Figures 1, 2, and 8 IF = 100 mA, di/dt = 20 A/µs, µ See Notes 5 and 6 and Figure 3 100 300 ns Pulse duration 100 µs and duty cycle 2%. Technique should limit TJ ­ TC to 10°C maximum. These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts. Nominal current is defined for a consistent comparison between devices from different sources. It is the current that produces a voltage drop of 0.5 V at TC = 85°C. POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 TPIC6B273 TPIC6B273 POWER LOGIC OCTAL D-TYPE LATCH SLIS031 SLIS031 ­ APRIL 1994 ­ REVISED JULY 1995 thermal resistance PARAMETER RJA TEST CONDITIONS DW package Thermal resistance, junction-to-ambient resistance junction to ambient MIN MAX 90 All 8 outputs with equal power N package 95 UNIT °C/W PARAMETER MEASUREMENT INFORMATION 24 V 5V 20 VCC 11 Word Generator (see Note A) 5V ID CLK 0V 235 DUT CLK DRAIN 4 ­7, 14 ­17 5V D Output 0V D 1 5V CL = 30 pF (see Note B) CLR CLR 0V GND 24 V 10 Output 0.5 V TEST CIRCUIT VOLTAGE WAVEFORMS Figure 1. Resistive-Load Test Circuit and Voltage Waveforms 5V D 5V VCC Word Generator (see Note A) Word Generator (see Note A) CLK 24 V 1 20 0V 5V 50% 0V CLR tPLH ID D 11 CLK 235 DUT DRAIN GND 50% Output 4 ­7, 14 ­17 Output tPHL 90% 24 V 90% 10% 10% tr 0.5 V tf SWITCHING TIMES CL = 30 pF (see Note B) 10 5V 50% CLK 0V tsu TEST CIRCUIT D th 5V 50% 50% 0V tw INPUT SETUP AND HOLD WAVEFORMS Figure 2. Test Circuit, Switching Times, and Voltage Waveforms NOTES: A. The word generator has the following characteristics: tr 10 ns, tf 10 ns, tw = 300 ns, pulsed repetition rate (PRR) = 5 KHz, ZO = 50 . B. CL includes probe and jig capacitance. POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 5 TPIC6B273 TPIC6B273 POWER LOGIC OCTAL D-TYPE LATCH SLIS031 SLIS031 ­ APRIL 1994 ­ REVISED JULY 1995 PARAMETER MEASUREMENT INFORMATION TP K DRAIN 0.1 A 2500 µF 250 V Circuit Under Test di/dt = 20 A/µs + 25 V L = 1 mH IF (see Note A) IF ­ 0 TP A 25% of IRM t2 t1 t3 Driver IRM RG VGG (see Note B) ta 50 trr CURRENT WAVEFORM TEST CIRCUIT NOTES: A. The DRAIN terminal under test is connected to the TP K test point. All other terminals are connected together and connected to the TP A test point. B. The VGG amplitude and RG are adjusted for di/dt = 20 A/µs. A VGG double-pulse train is used to set IF = 0.1 A, where t1 = 10 µs, t2 = 7 µs, and t3 = 3 µs. Figure 3. Reverse-Recovery-Current Test Circuit and Waveforms of Source-to-Drain Diode 5V 15 V tw 20 1 Word Generator (see Note A) 11 VCC 10.5 CLR CLK 5V Input See Note B ID 200 mH DUT DRAIN D 4 ­7, 14 ­17 GND ID VDS V(BR)DSX = 50 V MIN VOLTAGE AND CURRENT WAVEFORMS TEST CIRCUIT NOTES: A. The word generator has the following characteristics: tr 10 ns, tf 10 ns, ZO = 50 . B. Input pulse duration, tw, is increased until peak current IAS = 0.5 A. Energy test is defined as EAS = IAS x V(BR)DSX x tav/2 = 30 mJ. Figure 4. Single-Pulse Avalanche Energy Test Circuit and Waveforms 6 0V IAS = 0.5 A VDS 10 tav POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 TPIC6B273 TPIC6B273 POWER LOGIC OCTAL D-TYPE LATCH SLIS031 SLIS031 ­ APRIL 1994 ­ REVISED JULY 1995 TYPICAL CHARACTERISTICS PEAK AVALANCHE CURRENT vs TIME DURATION OF AVALANCHE DRAIN-TO-SOURCE ON-STATE RESISTANCE vs DRAIN CURRENT r DS(on) ­Drain-to-Source On-State Resistance ­ 10 IAS ­ Peak Avalanche Current ­ A TC = 25°C 4 2 1 0.4 0.2 0.1 0.1 0.2 0.4 1 2 4 18 VCC = 5 V See Note A 16 14 TC = 125°C 12 10 8 6 TC = 25°C 4 TC = ­ 40°C 2 0 0 10 100 tav ­ Time Duration of Avalanche ­ ms 200 300 400 500 ID ­ Drain Current ­ mA 600 700 0 25 50 75 100 TC ­ Case Temperature ­ °C 125 Figure 5 Figure 6 8 SWITCHING TIME vs CASE TEMPERATURE 300 ID = 100 mA See Note A 7 ID = 100 mA See Note A tf TC = 125°C 250 6 Switching Time ­ ns r DS(on) ­ Static Drain-to-Source On-State Resistance ­ STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE vs LOGIC SUPPLY VOLTAGE 5 TC = 25°C 4 3 TC = ­ 40°C 2 tr 200 tPLH 150 tPHL 100 1 0 4 4.5 5 5.5 6 6.5 7 50 ­ 50 ­ 25 VCC ­ Logic Supply Voltage ­ V Figure 7 Figure 8 NOTE C: Technique should limit TJ ­ TC to 10°C maximum. POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 7 TPIC6B273 TPIC6B273 POWER LOGIC OCTAL D-TYPE LATCH SLIS031 SLIS031 ­ APRIL 1994 ­ REVISED JULY 1995 THERMAL INFORMATION MAXIMUM PEAK DRAIN CURRENT OF EACH OUTPUT vs NUMBER OF OUTPUTS CONDUCTING SIMULTANEOUSLY I D ­ Maximum Continuous Drain Current of Each Output ­ A 0.45 VCC = 5 V 0.4 0.35 0.3 0.25 TC = 25°C 0.2 0.15 TC = 100°C 0.1 TC = 125°C 0.05 0 1 2 3 4 5 6 7 8 N ­ Number of Outputs Conducting Simultaneously I D ­ Maximum Peak Drain Current of Each Output ­ A MAXIMUM CONTINUOUS DRAIN CURRENT OF EACH OUTPUT vs NUMBER OF OUTPUTS CONDUCTING SIMULTANEOUSLY 0.5 d = 10% 0.45 d = 20% 0.4 0.35 d = 50% 0.3 0.25 d = 80% 0.2 0.15 VCC = 5 V TC = 25°C d = tw/tperiod = 1 ms/tperiod 0.1 0.05 0 1 Figure 9 8 2 3 4 5 Figure 10 POST OFFICE BOX 655303 6 7 8 N ­ Number of Outputs Conducting Simultaneously · DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 18-Apr-2008 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty Lead/Ball Finish MSL Peak Temp (3) TPIC6B273DW TPIC6B273DW ACTIVE SOIC DW 20 25 TBD CU NIPDAU Level-1-220C-UNLIM TPIC6B273DWG4 TPIC6B273DWG4 ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TBD CU NIPDAU Level-1-220C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU N / A for Pkg Type TPIC6B273DWR TPIC6B273DWR ACTIVE SOIC DW 20 2000 TPIC6B273DWRG4 TPIC6B273DWRG4 ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) TPIC6B273N TPIC6B273N ACTIVE PDIP N 20 20 Pb-Free (RoHS) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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