SLG74120 CK410B DB1200 1E-12 SLG74120T SLG74120TTR - Datasheet Archive

 

Twelve Output PCI Express Gen 2 Buffer Features Output Summary · Optimized to meet Next Generation PCI-Express Gen 2 &

 

SLG74120 SLG74120 Twelve Output PCI Express Gen 2 Buffer Features Output Summary · Optimized to meet Next Generation PCI-Express Gen 2 & Gen 3 Phase Jitter · SRC or FSB Frequency Selectable · OE pin Control of All Outputs · 3.3 V Supply Voltage Operation · Output is HCSL Compatible · PLL Bypass Configurable · Programmable Bandwidth · Glitchfree Transition Between Frequency States · 3 Address Selection · DIFF SRC Clock Support 12 differential clock output pairs @ 0.7 V 50 ps O-O skew 50 ps Cyc_Cyc Jitter (PLL mode) 3.0 ps RMS phase jitter (PCIE Gen 2 Phase Jitter Compliant) SMBus Programmable Configurations · · · · · · 64 pin TSSOP package VDD FS_0 0 0 0 0 1 1 1 1 FS_1 0 0 1 1 0 0 1 1 FS_2 0 1 0 1 0 1 0 1 64 VDDA 2 63 VSSA SRC_IN# 3 62 IREF VSS 4 61 FS_0 OE_0# 5 60 OE_11# DIF_0 6 59 DIF_11 DIF_0# Optimized Freq(MHz) 266 333 200.0 400 133 100 166 Hi-z 1 SRC_IN Table 1. Frequency Select Table (FS_0, FS_1, FS_2) 7 58 DIF_11# 8 1 9 57 VDD 56 VSS OE_10# VDD VSS 54 DIF_10 12 53 DIF_10# 13 DIF_2 14 DIF_2# 15 VSS 16 SLG74120 SLG74120 55 11 OE_2# 12 10 DIF_1 DIF_1# OE OE_1# 52 OE_9# 51 DIF_9 50 DIF_9# 49 VSS VDD 17 48 VDD OE_3# 18 47 OE_8# DIF_3 CONTROL LOGIC 21 44 OE_7# DIF_4 22 43 DIF_7 DIF_4# 23 24 25 42 41 DIF_7# VDD 40 VSS OE_5# DIF(11:0) DIF_8# VSS FS (2:0) PLL BYPASS PD SDATA SCLK SA 12 DIF_8 45 VDD M U X STOP LOGIC 46 20 OE_4# SRC_IN# 19 DIF_3# PLL SRC_IN 26 39 OE_6# DIF_5 27 38 DIF_6 DIF_5# 28 37 *SA 29 36 DIF_6# PWRGD#/ PWRD- HIGH_BW# 30 35 BYPASS#/ PLL FS_2 31 34 FS_1 SCL 32 33 SDA 64-pin TSSOP Note: * = contains internal pull-down resistor Other brands and names may be claimed as the property of others Silego Technology, Inc. 000-0074120-092 Rev 0.92 Revised June 23, 2010 SLG74120 SLG74120 Pin Description Pin # Name Type Description 1 VDD PWR 3.3 V power supply for outputs 2 SRC_IN I, DIF 0.7 V Differential input (eg. from CK410B CK410B clock synthesizer) 3 SRC_IN# I, DIF 0.7 V Differential input (eg. from CK410B CK410B clock synthesizer) 4 VSS GND Ground for outputs 5 OE_0# I, SE 3.3 V LVTTL active low input for enabling differential outputs(default). Controls each output pair. OE can be disabled by SMBus registers. 6 DIF_0 O, DIF 0.7 V Differential clock outputs, that can be geared to the a ratio of the input clock. Default is 1:1. 7 DIFF_0# O, DIF 0.7 V Differential clock outputs, that can be geared to the a ratio of the input clock. Default is 1:1. 8 VDD PWR 3.3 V power supply for outputs 9 VSS GND Ground for outputs 10 OE_1# I, SE 3.3 V LVTTL active low input for enabling differential outputs(default). Controls each output pair. OE can be disabled by SMBus registers. 11 DIF_1 O, DIF 0.7 V Differential clock outputs, that can be geared to the a ratio of the input clock. Default is 1:1. 12 DIF_1# O, DIF 0.7 V Differential clock outputs, that can be geared to the a ratio of the input clock. Default is 1:1. 13 OE_2# I, SE 3.3 V LVTTL active low input for enabling differential outputs(default). Controls each output pair. OE can be disabled by SMBus registers. 14 DIF_2 O, DIF 0.7 V Differential clock outputs, that can be geared to the a ratio of the input clock. Default is 1:1. 15 DIF_2# O, DIF 0.7 V Differential clock outputs, that can be geared to the a ratio of the input clock. Default is 1:1. 16 VSS GND Ground for outputs 17 VDD PWR 3.3 V power supply for outputs 18 OE_3# I, SE 3.3 V LVTTL active low input for enabling differential outputs(default). Controls each output pair. OE can be disabled by SMBus registers. 19 DIF_3 O, DIF 0.7 V Differential clock outputs, that can be geared to the a ratio of the input clock. Default is 1:1. 20 DIF_3# O, DIF 0.7 V Differential clock outputs, that can be geared to the a ratio of the input clock. Default is 1:1. 21 OE_4# I, SE 3.3 V LVTTL active low input for enabling differential outputs(default). Controls each output pair. OE can be disabled by SMBus registers. 22 DIF_4 O, DIF 0.7 V Differential clock outputs, that can be geared to the a ratio of the input clock. Default is 1:1. 23 DIF_4# O, DIF 0.7 V Differential clock outputs, that can be geared to the a ratio of the input clock. Default is 1:1. 24 VDD PWR 3.3 V power supply for outputs 25 VSS GND Ground for outputs 26 OE_5# I, SE 3.3 V LVTTL active low input for enabling differential outputs(default). Controls each output pair. OE can be disabled by SMBus registers. 000-0074120-092 Page 2 of 16 SLG74120 SLG74120 Pin Description (continued) Pin # Name Type Description 27 DIF_5 O, DIF 0.7 V Differential clock outputs, that can be geared to the a ratio of the input clock. Default is 1:1. 28 DIF_5# O, DIF 0.7 V Differential clock outputs, that can be geared to the a ratio of the input clock. Default is 1:1. 29 SA I 3.3V tolerance input. Contains internal pull-down resistor. 3.3 V LVTTL input for selecting the address. Tri-level input. Refer to the Address Selection table for Vil_SA and Vih_SA thresholds for selecting the address. 30 HIGH_BW# I, SE 3.3 V LVTTL input for selecting the PLL bandwidth (high = low BW) 31 FS_2 I, SE 3.3 V tolerant inputs for input/output frequency selection. This can also be a GTL level, low-voltage threshold input. Refer to Table 3 2 for Vil_FS & Vih_FS thresholds.for selecting the SRC or FSB frequency. 32 SCL I, SE SMBus slave clock input 33 SDA I/O, OC 34 FS_1 I, SE 35 BYPASS#/PLL 36 PWRGD#/PWRDOWN 37 DIF_6# O, DIF 0.7 V Differential clock outputs, that can be geared to the a ratio of the input clock. Default is 1:1. 38 DIF_6 O, DIF 0.7 V Differential clock outputs, that can be geared to the a ratio of the input clock. Default is 1:1. 39 OE_6# I, SE 3.3 V LVTTL active low input for enabling differential outputs(default). Controls each output pair. OE can be disabled by SMBus registers. 40 VSS GND Ground for outputs 41 VDD PWR 3.3 V power supply for outputs 42 DIF_7# O, DIF 0.7 V Differential clock outputs, that can be geared to the a ratio of the input clock. Default is 1:1. 43 DIF_7 O, DIF 0.7 V Differential clock outputs, that can be geared to the a ratio of the input clock. Default is 1:1. 44 OE_7# I, SE 3.3 V LVTTL active low input for enabling differential outputs(default). Controls each output pair. OE can be disabled by SMBus registers. 45 DIF_8# O, DIF 0.7 V Differential clock outputs, that can be geared to the a ratio of the input clock. Default is 1:1. 46 DIF_8 O, DIF 0.7 V Differential clock outputs, that can be geared to the a ratio of the input clock. Default is 1:1. 47 OE_8# I, SE 3.3 V LVTTL active low input for enabling differential outputs(default). Controls each output pair. OE can be disabled by SMBus registers. 48 VDD PWR 3.3 V power supply for outputs 49 VSS GND Ground for outputs 50 DIF_9# 000-0074120-092 I Open collector SMBus data 3.3 V tolerant inputs for input/output frequency selection. This can also be a GTL level, low-voltage threshold input. Refer to Table 3 2 for Vil_FS & Vih_FS thresholds.for selecting the SRC or FSB frequency. 3.3 V LVTTL input for selecting PLL or bypass mode 3.3 V LVTTL input to power up or power down the device O, DIF 0.7 V Differential clock outputs, that can be geared to the a ratio of the input clock. Default is 1:1. Page 3 of 16 SLG74120 SLG74120 Pin Description (continued) Pin # Name Type Description 51 DIF_9 O, DIF 0.7 V Differential clock outputs, that can be geared to the a ratio of the input clock. Default is 1:1. 52 OE_9# I, SE 3.3 V LVTTL active low input for enabling differential outputs(default). Controls each output pair. OE can be disabled by SMBus registers. 53 DIF_10# O, DIF 0.7 V Differential clock outputs, that can be geared to the a ratio of the input clock. Default is 1:1. 54 DIF_10 O, DIF 0.7 V Differential clock outputs, that can be geared to the a ratio of the input clock. Default is 1:1. 55 OE_10# I, SE 3.3 V LVTTL active low input for enabling differential outputs(default). Controls each output pair. OE can be disabled by SMBus registers. 56 VSS GND Ground for outputs 57 VDD PWR 3.3 V power supply for outputs 58 DIF_11# O, DIF 0.7 V Differential clock outputs, that can be geared to the a ratio of the input clock. Default is 1:1. 59 DIF_11 O, DIF 0.7 V Differential clock outputs, that can be geared to the a ratio of the input clock. Default is 1:1. 60 OE_11# I, SE 3.3 V LVTTL active low input for enabling differential outputs(default). Controls each output pair. OE can be disabled by SMBus registers. 61 FS_0 I, SE 3.3 V tolerant inputs for input/output frequency selection. This can also be a GTL level, low-voltage threshold input.Refer to Table 3 2 for Vil_FS & Vih_FS thresholds.for selecting the SRC or FSB frequency. 62 IREF I 63 VSSA GND Ground for PLL 64 VDDA PWR 3.3V Power Supply for PLL A precision resistor is attached to this pin to set the differential output current Frequency Select Pins (FS_A, FS_B, FS_C) FS_A, FS_B, and FS_C are hardware pins, which program the appropriate output frequency of the DIF pairs. Note that the the CLK_IN frequency is equal to CLK_OUT frequency, this means that the SLG74120 SLG74120 is operated in the 1:1 mode only. The frequency seletction can be enabled by either FS_[2:0] hardware pins or by programing the SMBUS. The functionality is summarized in tahle below. OE Functionality OE# (Pin) OE (SMBus bit) DIFF DIFF# 0 1 Normal Normal 1 0 Tristate Tristate 1 1 Tristate Tristate 0 0 Tristate Notes Tristate SA ­ Address Selection SA is a hardware pin, which programs the appropriate address for the DB1200 DB1200. This is a tri-level input pin that can configure the DB1200 DB1200 to three different addresses (see table 3-2 for SA tri-level signal). This pin has an internal pull-down resistor, which will be a low level default at power on. The resistor values range over PVT is from 60K to 170K Following are the addresses for the DB1200 DB1200: LOW = DC/DD (default using internal pull-down resistor) MID = D6/D7 HIGH = D4/D5 000-0074120-092 Page 4 of 16 SLG74120 SLG74120 Serial Bus Interface A two-wire serial interface is provided as the programming interface for the clock synthesizer. The serial interface is fully compliance to the SMBus 2.0 specification. The registers associated with the two-wire interface initializes to their default setting upon power-up, and therefore use of this interface is optional. The serial interface supports block write and block read operation from any SMBus master devices. For block write and block read operations, the bytes must be accessed in sequential order from lowest to highest byte (most significant bit first) with the ability to stop after any complete byte has been transferred. The block write and block read protocol is outlined in Table 2. The slave receiver address is 11010010 (D2h). Table 2. Block Read and Block Write protocol Block Write Protocol Block Read Protocol Bit Description Bit Description 1 Start 1 Start 2:8 Slave address - 7 bits 2:8 Slave address - 7 bits 9 Write 9 Write 10 Acknowledge from slave 10 Acknowledge from slave 11:18 Command Code - 8 Bit '00000000' stands for block operation 11:18 Command Code - 8 Bit '00000000' stands for block operation 19 Acknowledge from slave 19 Acknowledge from slave 20:27 Byte Count - 8 bits 20 Repeat start 28 Acknowledge from slave 21:27 Slave address - 7 bits 29:36 Data byte 0 - 8 bits 28 Read 37 Acknowledge from slave 29 Acknowledge from slave 38:45 Data byte 1 - 8 bits 30:37 Byte count from slave - 8 bits 46 Acknowledge from slave 38 Acknowledge . Data Byte N/Slave Acknowledge. 39:46 Data byte from slave - 8 bits . Data Byte N - 8 bits 47 Acknowledge . Acknowledge from slave 48:55 Data byte from slave - 8 bits . Stop 56 Acknowledge . Data bytes from slave/Acknowledge . Data byte N from slave - 8 bits . Not Acknowledge . Stop 000-0074120-092 Page 5 of 16 SLG74120 SLG74120 Table 3. Byte Read and Byte Write protocol Byte Write Protocol Byte Read Protocol Bit Description Bit Description 1 Start 1 Start 2:8 Slave address - 7 bits 2:8 Slave address - 7 bits 9 Write 9 Write 10 Acknowledge from slave 10 Acknowledge from slave 11:18 Command Code - 8 bits '1xxxxxxx' stands for byte operation bit[6:0] of the command code represents the offset of the byte to be accessed 11:18 Command Code - 8 bits '1xxxxxxx' stands for byte operation bit[6:0] of the command code represents the offset of the byte to be accessed 19 Acknowledge from slave 19 Acknowledge from slave 20:27 Data byte - 8 bits 20 Repeat start 28 Acknowledge from slave 21:27 Slave address - 7 bits 29 Stop 28 Read 29 Acknowledge from slave 30:37 Data byte from slave - 8 bits 38 Not Acknowledge 39 Stop 000-0074120-092 Page 6 of 16 SLG74120 SLG74120 Control Registers (SMBus Address = DC/DD) Byte 0: Control Registers Bit Description Type Default Output(s) Affected 0 Frequency Select FS_A If Bit = 0 If Bit = 1 RW Latched at power up DIF[11:0] 1 Frequency Select FS_B RW Latched at power up DIF[11:0] 2 Frequency Select FS_C RW Latched at power up DIF[11:0] 3 Reserved 0 4 Reserved 0 5 Reserved 0 6 BYPASS# / PLL Bypass mode PLL mode RW Latched at power up DIF[11:0] 7 HIGH_BW# High BW Low BW RW Latched at power up DIF[11:0] Byte 1: Output Enable Control Registers Bit Description If Bit = 0 If Bit = 1 Type Default Output(s) Affected 0 Output Enable DIF 0 Hi-Z Enabled RW 1 DIF 0, DIF 0# 1 Output Enable DIF 1 Hi-Z Enabled RW 1 DIF 1, DIF 1# 2 Output Enable DIF 2 Hi-Z Enabled RW 1 DIF 2, DIF 2# 3 Output Enable DIF 3 Hi-Z Enabled RW 1 DIF 3, DIF 3# 4 Output Enable DIF 4 Hi-Z Enabled RW 1 DIF 4, DIF 4# 5 Output Enable DIF 5 Hi-Z Enabled RW 1 DIF 5, DIF 5# 6 Output Enable DIF 6 Hi-Z Enabled RW 1 DIF 6, DIF 6# 7 Output Enable DIF 7 Hi-Z Enabled RW 1 DIF 7, DIF 7# Byte 2: Output Enable Control Registers Bit Description If Bit = 0 If Bit = 1 Type Default Output(s) Affected 0 Output Enable DIF 8 Hi-Z Enabled RW 1 DIF 8, DIF 8# 1 Output Enable DIF 9 Hi-Z Enabled RW 1 DIF 9, DIF 9# 2 Output Enable DIF 10 Hi-Z Enabled RW 1 DIF 10, DIF 10# 3 Output Enable DIF 11 Hi-Z Enabled RW 1 DIF 11, DIF 11# 4 Reserved 0 5 Reserved 0 6 Reserved 0 7 Reserved 0 Byte 3: OE# Pin Readback Register Bit Description If Bit = 0 If Bit = 1 Type Default Output(s) Affected 0 OE# Input DIF 0 Enabled Hi-Z R Readback of the pin state DIF 0, DIF 0# 1 OE# Input DIF 1 Enabled Hi-Z R Readback of the pin state DIF 1, DIF 1# 000-0074120-092 Page 7 of 16 SLG74120 SLG74120 Bit Description If Bit = 0 If Bit = 1 Type Default Output(s) Affected 2 OE# Input DIF 2 Enabled Hi-Z R Readback of the pin state DIF 2, DIF 2# 3 OE# Input DIF 3 Enabled Hi-Z R Readback of the pin state DIF 3, DIF 3# 4 OE# Input DIF 4 Enabled Hi-Z R Readback of the pin state DIF 4, DIF 4# 5 OE# Input DIF 5 Enabled Hi-Z R Readback of the pin state DIF 5, DIF 5# 6 OE# Input DIF6 Enabled Hi-Z R Readback of the pin state DIF 6, DIF 6# 7 OE# Input DIF 7 Enabled Hi-Z R Readback of the pin state DIF 7, DIF 7# Byte 4: OE# Pin Readback Register Bit Description If Bit = 0 If Bit = 1 Type Default Output(s) Affected 0 OE# Input DIF 8 Enabled Hi-Z R Readback of the pin state DIF 8, DIF 8# 1 OE# Input DIF 9 Enabled Hi-Z R Readback of the pin state DIF 9, DIF 9# 2 OE# Input DIF 10 Enabled Hi-Z R Readback of the pin state DIF 10, DIF 10# 3 OE# Input DIF 11 Enabled Hi-Z R Readback of the pin state DIF 11, DIF 11# 4 Reserved 0 5 Reserved 0 6 Reserved 0 7 Reserved 0 Byte 5:Vendor/Revision Identification Registers Bit Description If Bit = 0 If Bit = 1 Type Default Output(s) Affected 0 Vendor ID Bit 0 - - R 0 - 1 Vendor ID Bit 1 - - R 1 - 2 Vendor ID Bit 2 - - R 1 - 3 Vendor ID Bit 3 - - R 0 - 4 Revision Code Bit 0 - - R 0 - 5 Revision Code Bit 1 - - R 0 - 6 Revision Code Bit 2 - - R 0 - 7 Revision Code Bit 3 - - R 0 - Byte 6: Device ID Bit Description If Bit = 0 If Bit = 1 Type Default Output(s) Affected 0 Device ID 0 - - R 0 - 1 Device ID 1 - - R 0 - 2 Device ID 2 - - R 1 - 3 Device ID 3 - - R 1 - 4 Device ID 4 - - R 0 - 000-0074120-092 Page 8 of 16 SLG74120 SLG74120 Bit Description If Bit = 0 If Bit = 1 Type Default Output(s) Affected 5 Device ID 5 - - R 0 - 6 Device ID 6 - - R 0 - 7 Device ID 7 (MSB) - - R 0 - Byte 7: Byte Count Registers Bit Description If Bit = 0 If Bit = 1 Type Default Output(s) Affected 0 BC0 - Writing to this register configure how many byte will be read back - - RW 1 - 1 BC1 - Writing to this register configure how many byte will be read back - - RW 1 - 2 BC2 - Writing to this register configure how many byte will be read back - - RW 1 - 3 BC3 - Writing to this register configure how many byte will be read back - - RW 0 - 4 BC4 - Writing to this register configure how many byte will be read back - - RW 0 - 5 BC5 - Writing to this register configure how many byte will be read back - - RW 0 - 6 BC6 - Writing to this register configure how many byte will be read back - - RW 0 - 7 BC7 - Writing to this register configure how many byte will be read back - - RW 0 - 000-0074120-092 Page 9 of 16 SLG74120 SLG74120 Electrical Characteristics Absolute Maximum Ratings The table below lists the SLG74120 SLG74120's maximum environmental stress ratings. Functional operation at the absolute maximum and minimum is neither implied nor guaranteed. Functional operating parameters are listed in the AC and DC tables. Extended exposure to the maximum ratings may affect device reliability. Table 3-1. Absolute Maximum Ratings Symbol Parameter Min Max Units Notes VDD_A 3.3 VCore Supply Voltage - 4.6 V 3 VDD 3.3V I/O Supply Voltage - 4.6 V 3 VIH 3.3 V Input High Voltage - 4.6 V 1,3 VIL 3.3 V Input Low Voltage -0.5 - ts Storage Temperature -65 150 ESD prot. Input ESD protection 2000 o C 3 V 3 V 2 Notes: 1 Maximum VIH is not to exceed maximum VDD 2 Human body model 3 Consult technical support regarding extended operation in excess of normal DC operating parameters. Electrical Characteristics - Clock Input Parameters TA = 0 to 70°C, Supply Voltage VDD = 3.3 V ± 5% Symbol Parameter Condition Min Typ Max Units VIHDIF Input High Voltage-DIF_IN Differential Inputs (single-ended measurement) 660 700 850 mV VILDIF Input High Voltage-DIF_IN Differential Inputs (single-ended measurement) -150 0.0 150 mV VCOM Input Common Mode Voltage-DIF_IN Common Mode Input Voltage 0 V mV VSWING Input Amplitude-DIF_IN Peak-to-Peak Value 510 1000 mV dv/dt Input Slew Rate-DIF_IN Rise and Fall Trigger Level (175mV to 525mV) 0.5 2.0 V/ns IIN Input Leakage Current VIN = VDD =, VIN = GND -0.5 +0.5 uA DTIN Input Duty Cycle Measurement from differential waveform 45 JDIFIN_SRC Input Jitter - Cycle to Cycle JDIFIN_CPU 000-0074120-092 55 % SRC 100MHz Output. Refer to CK410B CK410B+ Output Cycle to Cycle Jitter Spec 125 ps CPU Diff Output. Refer to CK410B CK410B+ Output Cycle to Cycle Jitter Spec 50 ps Page 10 of 16 SLG74120 SLG74120 DC Electrical Characteristics DC parameters must be sustainable under steady state (DC) conditions. Table 3-2 DC Operating Characteristics VDD_A = 3.3 V ± 5%, VDD = 3.3 V ± 5% Symbol Parameter Condition Min Max Units VDD_A 3.3V Core Supply Voltage VDD 3.3V I/O Supply Voltage 3.3V ±5% VIH 3.3V Input High Voltage VDD VIL 3.3V Input Low Voltage IIL Input Leakage Current 0 < VIN < VDD VIH_FS 3.3V Input High Voltage VDD Notes 3.3V ±5% 3.135 3.465 V 3.135 3.465 V 2.0 VDD+0.3 V VSS-0.3 0.8 V -5 +5 A 0.7 VDD-0.3 V 3 3 VIL_FS 3.3 Input Low Voltage VSS-0.3 0.35 V VIL_SA 3.3 Input Low Voltage 0 0.9 V VIM_SA 3.3V Input Medium Voltage 1.3 2.0 V VIH_SA 3.3V Input High Voltage 2.4 VDD V VOH 3.3V Output High Voltage IOH = -1mA V 1 VOL 3.3V Output Low Voltage IOL = 1mA 0.4 V 1 2.4 CIN Input Capacitance 2.5 4.5 pF 4 COUT Output Capacitance 2.5 4.5 pF 4 7 nH 0 70 oC LPIN Pin Inductance ta Ambient Temperature No Airflow 1 Signal edge is required to be monotonic when transitioning through this region Input Leakage Current does not include inputs with pull-up or pull-down resistors. Inputs with resistors should state current requirements. 3 Internal voltage reference is to be used to guarantee Vih_FS and Vil_FS thresholds levels over devices full operating range 2 4 Ccomp capacitance based on pad metallization and silicon device capacitance. Not including pin capacitance Power Management The values below are estimates for the power specifications. Table 3-3. Maximum Allowed Current Max 3.3V Supply Consumption Max Discrete Cap Loads VDD = 3.465 V All Static Inputs - VDD or VSS Condition Powerdown Mode (VTT_PWRGD# / PWRDWN = 1) All Pairs Tristated = 24mA Full Active 375 mA Skew and Jitter Characteristics Skew and jitter characteristics are critical output timing parameters affecting downstream receivers of the clocking signals. Table 3-4. Output Relational Timing Parameters Electrical Characteristics - Skew and Differential Jitter Parameters TA = 0 - 70oC Group Description min max units notes CLK_IN, DIFF[x:0] Input-to-Output Delay in PLL mode (1:1 only), nominal value -250 250 ps 1,2,3,4,5 000-0074120-092 Page 11 of 16 SLG74120 SLG74120 Electrical Characteristics - Skew and Differential Jitter Parameters TA = 0 - 70oC CLK_IN, DIF[x:0] Input-to-Output Delay in Bypass mode (1:1 only), nominal vlaue 2.5 4.5 ns 2,3,4 DIF[11:0] Output-to-Output Skew across all 12 outputs (Common to Bypass and PLL mode - all outpus at same gear 0 50 ps 1,2,3 DIF[11:0] Differential Phase Jitter (RMS Value) 10 ps 1,4,6 DIF[11:0] Differential Spread Spectrum Tracking Error (peak to peak) 100 ps 1,4,7 1 Measured into fixed 2 pF load cap. Input to output skew is measured at the first output edge following the corresponding input. 2 Measured from differential cross-point to differential cross-point 3 All Bypass Mode Input-to-Output specs refer to the timing between an input edge and the specific output edge created by it. 4 This parameter is deterministic for a given device 5 Measured with scope averaging on to find mean value. 6 This parameter is measured at the outputs of two separate SLG74120 SLG74120 devices driven by a single CK410B CK410B. The SLG74120 SLG74120's must be set to high bandwidth. Differential phase jitter is the accumulation of the phase jitter not shared by the outputs (e.g. not including the affects of spread spectrum). Target ranges of consideration are agents with BW of 1-22 MHz and 11-33 MHz. 7 Differential spread spectrum tracking error is the difference in spread spectrum tracking between two SLG74120 SLG74120 devices This parameter is measured at the outputs of two separate SLG74120 SLG74120 devices driven by a single CK410B CK410B in Spread Spectrum mode. The SLG74120 SLG74120's must be set to high bandwidth. The spread spectrum characteristics are: maximum of 0.5%, 30-33 kHz modulation frequency, linear profile. Table 3-5. PLL Bandwidth, Peaking and Phase Jitter Impact Group Parameter Target Min Max Notes DIF PLL Jitter Peaking (HIGH_BW# = 0)