500 MILLION PARTS FROM 12000 MANUFACTURERS

DATASHEET SEARCH ENGINE

Top Results

Part Manufacturer Description Datasheet BUY
80610840664 3M Interconnect END CAP SKE-15/40-0.59-1.26 visit Digikey Buy
SKE-45/100 3M Interconnect END CAP SKE-45/100-1.77-3.15 visit Digikey Buy
80610840680 3M Interconnect END CAP SKE-45/100-1.77-3.15 visit Digikey Buy
SKE-15/40 3M Interconnect END CAP SKE-15/40-0.59-1.26 visit Digikey Buy
SKE-30/76 3M Interconnect END CAP SKE-30/76-1.18-2.36 visit Digikey Buy
80610840672 3M Interconnect END CAP SKE-30/76-1.18-2.36 visit Digikey Buy

SKE 4f 1/08 Datasheet

Part Manufacturer Description PDF Type
SKE4F1/08 N/A Shortform Semicon, Diode, and SCR Datasheets Scan

SKE 4f 1/08

Catalog Datasheet MFG & Type PDF Document Tags

42TU

Abstract: AN-228 SE LE CT SKE W SE LE CT 3 3 3 1Q 1 3 1Q 1 1F 0:1 1F 0:1 2Q 0 2Q 0 SK E W , DS 0:1 3 P LL 2F 0:1 2F 0:1 FB 3 FS 3Q 0 3 3Q 0 SK E W SE LE CT SKE , 4Q 0 SK E W SE LE CT 3 4Q 1 4F 0:1 3 3 4Q 1 4F 0:1 1 c /- 2001 , and Frequency Multiply by six with 4F[1:0] = MM and DS[1:0] = MH. Figure 5. Wiring Diagram and , Figure 8. Wiring Diagram and Frequency Multiply by six with 4F[1:0] = MM and DS[1:0] = MH. Figure 9
Integrated Device Technology
Original
AN-228 IDT5V995 IDT5V9950 42TU IDT5T995 IDT5T9950 IDT5T995/A IDT5T9950/A

42TU

Abstract: IDT5 SE LE CT SKE W SE LE CT 3 3 3 1Q 1 3 1Q 1 1F 0:1 1F 0:1 2Q 0 2Q 0 SK E W , DS 0:1 3 P LL 2F 0:1 2F 0:1 FB 3 FS 3Q 0 3 3Q 0 SK E W SE LE CT SKE , 4Q 0 SK E W SE LE CT 3 4Q 1 4F 0:1 3 3 4Q 1 4F 0:1 1 c /- 2001 , and Frequency Multiply by six with 4F[1:0] = MM and DS[1:0] = MH. Figure 5. Wiring Diagram and , Figure 8. Wiring Diagram and Frequency Multiply by six with 4F[1:0] = MM and DS[1:0] = MH. Figure 9
Integrated Device Technology
Original
IDT5

SKE 4F

Abstract: 42TU SE LE CT SKE W SE LE CT 3 3 3 1Q 1 3 1Q 1 1F 0:1 1F 0:1 2Q 0 2Q 0 SK E W , DS 0:1 3 P LL 2F 0:1 2F 0:1 FB 3 FS 3Q 0 3 3Q 0 SK E W SE LE CT SKE , 4Q 0 SK E W SE LE CT 3 4Q 1 4F 0:1 3 3 4Q 1 4F 0:1 1 c /- 2001 , and Frequency Multiply by six with 4F[1:0] = MM and DS[1:0] = MH. Figure 5. Wiring Diagram and , . Wiring Diagram and Frequency Multiply by six with 4F[1:0] = MM and DS[1:0] = MH. Figure 9. Wiring
Integrated Device Technology
Original
SKE 4F

CY7B991

Abstract: IDT5991A Voltage to Ground VI 30 3F 1 5 29 2F 0 4F 0 6 28 G ND/sO E 4F 1 7 27 , - V - 0.8 V VCC- 1 - V VIL Input LOW Voltage Guaranteed Logic LOW , EW 0, 1 t SKE W PR t SKEW 0, 1 OTH ER Q t SKE W 2 t SKE W 2 INV ER TED Q t SK EW 3 , Output frequency: 3.75MHz to 100MHz · 2x, 4x, 1/2, and 1/4 outputs · 5V with TTL outputs · 3 skew , . FUNCTIONAL BLOCK DIAGRAM G ND/sOE 1Q 0 Skew Select 1Q 1 3 3 1F1:0 V CCQ /PE 2Q 0
Integrated Device Technology
Original
IDT5991A CY7B991 100MH IDT5991A-2 IDT5991A-5 IDT5991A-7

5T9950A

Abstract: 5T9950 0 2 23 4F 1 3 22 sOE PE 4 21 V D DQ V D DQ 5 20 1Q 0 4Q , t CCJ H, M, L Q t S KEW P R t SKEW 0, 1 t SKE W PR t SKEW 0, 1 OTH ER Q t SKE W 2 , : 6MHz to 200MHz Output frequency: ­ Std: 6MHz to 160MHz ­ A: 6MHz to 200MHz 2x, 4x, 1/2, and 1/4 , E 1Q 0 Skew Select 3 1Q 1 3 1F1:0 PE TEST 3 3 REF 2Q 0 Skew Select 2Q 1 3 PLL 2F1:0 FB 3 3Q 0 Skew Select 3 3Q 1 3 FS 3F1:0 4Q 0 Skew
Integrated Device Technology
Original
5T9950 5T9950A 160MH 200MH
Abstract: 23 4F 1 3 22 sOE PE 4 21 V D DQ V D DQ 5 20 1Q 0 4Q 1 6 , () t O DC V t O DC V FB t CCJ H, M, L Q t S KEW P R t SKEW 0, 1 t SKE W PR t SKEW 0, 1 OTH ER Q t SKE W 2 t SKE W 2 INVER TE D Q t SK EW 3, 4 t SK EW 3, 4 t SKEW 3, 4 , Std: 6MHz to 160MHz ­ A: 6MHz to 200MHz 2x, 4x, 1/2, and 1/4 outputs 3-level inputs for skew and , Select 3 1Q 1 3 1F1:0 PE TEST 3 3 REF 2Q 0 Skew Select 2Q 1 3 PLL Integrated Device Technology
Original

5T9950A

Abstract: 5T9950 0 2 23 4F 1 3 22 sOE PE 4 21 V D DQ V D DQ 5 20 1Q 0 4Q , Q t S KEW P R t SKEW 0, 1 t SKE W PR t SKEW 0, 1 OTH ER Q t SKE W 2 t SKE W 2 , : 6MHz to 200MHz Output frequency: ­ Std: 6MHz to 160MHz ­ A: 6MHz to 200MHz 2x, 4x, 1/2, and 1/4 , E 1Q 0 Skew Select 3 1Q 1 3 1F1:0 PE TEST 3 3 REF 2Q 0 Skew Select 2Q 1 3 PLL 2F1:0 FB 3 3Q 0 Skew Select 3 3Q 1 3 FS 3F1:0 4Q 0 Skew
Integrated Device Technology
Original
Abstract: Voltage 4F 0 2 23 4F 1 3 22 sOE PE 4 21 V D DQ V D DQ 5 20 1Q , P R t SKEW 0, 1 t SKE W PR t SKEW 0, 1 OTH ER Q t SKE W 2 t SKE W 2 INVER TE D Q , : â'" Std: 6MHz to 160MHz â'" A: 6MHz to 200MHz 2x, 4x, 1/2, and 1/4 outputs 3-level inputs for , sO E 1Q 0 Skew Select 3 1Q 1 3 1F1:0 PE TEST 3 3 REF 2Q 0 Skew Select 2Q 1 3 PLL 2F1:0 FB 3 3Q 0 Skew Select 3 3Q 1 3 FS 3F1:0 4Q 0 Integrated Device Technology
Original

5T9950

Abstract: 5T9950A 23 4F 1 3 22 sOE PE 4 21 V D DQ V D DQ 5 20 1Q 0 4Q 1 6 , () t O DC V t O DC V FB t CCJ H, M, L Q t S KEW P R t SKEW 0, 1 t SKE W PR t SKEW 0, 1 OTH ER Q t SKE W 2 t SKE W 2 INVER TE D Q t SK EW 3, 4 t SK EW 3, 4 t SKEW 3, 4 , Std: 6MHz to 160MHz ­ A: 6MHz to 200MHz 2x, 4x, 1/2, and 1/4 outputs 3-level inputs for skew and , Select 3 1Q 1 3 1F1:0 PE TEST 3 3 REF 2Q 0 Skew Select 2Q 1 3 PLL
Integrated Device Technology
Original
Abstract: Temperature Range Max. ­0.5 to +7 ­0.5 to +7 150 (1) Unit V V °C °C 4 3F 1 4F 0 4F 1 V CC Q /PE VCCN 4Q , - - Max. - 0.8 - VCC/2+0.5 1 ±5 ±200 ±50 ±200 ±100 ±100 - - 0.45 - 250 Unit V V V V V µA , tJR Q tS KEW P R tSKEW 0, 1 OTH ER Q t SKE WP R t SKEW 0, 1 t SKE W 2 INV ER TED Q t , , 4x, 1/2, and 1/4 outputs 5V with TTL outputs 3 skew grades: IDT5991A -2: tSKEW0 , negative edge of REF. · · · · · · · · FUNCTIONAL BLOCK DIAGRAM GND/sO E 1Q 0 1Q 1 1F1:0 V CCQ /PE Integrated Device Technology
Original
J32-1
Abstract: 3F 1 4F 0 4F 1 V CC Q /P E V CCN 4Q 1 4Q 0 G ND G ND 5 6 7 8 9 10 11 12 13 14 3 2 1 32 , (2) Min. 2 - VCC-1 VCC/2-0.5 - - Max. - 0.8 - VCC/2+0.5 1 ±5 ±200 ±50 ±200 ±100 ±100 - - , tJR Q t SKE W PR t SKEW 0, 1 OTH ER Q t S KEW PR t SK EW 0, 1 tS KEW 2 INVER TED Q t SKE W 2 tSK EW 3, 4 tSK EW 3, REF D IVIDE D BY 2 4 t SK EW 3, 4 t SK EW 1, 3, 4 , , 4x, 1/2, and 1/4 outputs 5V with TTL outputs 3 skew grades: IDT5991A -2: tSKEW0 Integrated Device Technology
Original

0C062

Abstract: OC062 * OOOD OOOE OOQF 0010 1C1B1 1C1BC 100 3 1 0903F POW ER.DELAY: CALL CALL ADD SKE BR W A IT -2 M S MS_H_1 , fo r any errors w h ic h m ay appear in CONTENTS CHAPTER 1 O U T L I N E . 1 CHAPTER 2 2.1 2.2 2 .3 F U N C T IO N S O F M IC R O C O M P U T E R -C O N T R O L L E , . 4 .5 .1 0 Random Pattern C o u n t , . 4 .5 .1 2 M o tor C o n t r o l
-
OCR Scan
0C062 OC062 0C032 SKE 502 SKE 1/17 triac MAC 97 AB PD17104 EA-1261 EA-677 1990P PD171

CYB991V

Abstract: 42TU 4Q 0 4Q 1 4Q 1 SKEW SELECT 3 3 4F 0:1 * = FS PIN DO ES NO T A PPLY TO IDT5V994 1 , 100 M Hz 1F1 TES T Figure 4. Wiring Diagram and Frequency Multiply by two with 4F[1:0] = LL , Frequency Multiply by two with 4F[1:0] = LL. Figure 7 illustrates the IDT5V991A configured for getting max , Figure 10. Wiring Diagram and Frequency Multiply by two with 4F[1:0] = LL. Figure 10 illustrates the , OUTPUT CONFIGURATIONS WITH DIFFERENT 4F(1:0)(1) FB Output at 4F(1:0) 1F(1:0) LL LM LH
Integrated Device Technology
Original
IDT5992A IDT5993A IDT5V993A CYB991V CY7B992 AN-226

SKE 4F

Abstract: 5T9950 4F 0 2 23 4F 1 3 22 sOE PE 4 21 V DD Q V D DQ 5 20 1Q 0 , DCV FB t CCJ H, M, L Q t S KEW P R t SK EW 0, 1 t SKE W PR t SKEW 0, 1 OTH ER Q , 160MHz ­ A: 6MHz to 200MHz Output frequency: ­ Std: 6MHz to 160MHz ­ A: 6MHz to 200MHz 2x, 4x, 1/2, and 1/4 outputs 3-level inputs for skew and PLL range control PLL bypass for DC testing External , BLOCK DIAGRAM sOE 1Q 0 Skew Select 3 1Q 1 3 1F1:0 PE TEST 3 3 REF 2Q 0
Integrated Device Technology
Original

5T995

Abstract: IDT5T995 41 40 39 38 37 36 35 34 4F 1 1 33 1F 0 sOE 2 32 D S1 , 2F 1 GN D TEST R EF VDD FS 3F 0 3F 1 PIN CONFIGURATION 4F 0 INDUSTRIAL , t CCJH, HA, M, L, LA Q t SKE W PR t SKEW 0, 1 tSKE W PR tSK EW 0, 1 OTH ER Q t SKE W , divide-by-functionality from 1 to 12 through the use of the DS[1:0] inputs. This provides the user with frequency multiplication from 1 to 12 without using divided outputs for feedback. When the sOE pin is held low, all the
Integrated Device Technology
Original
5T995 5T995A

CYB991V

Abstract: 42TU 4Q 0 4Q 0 4Q 1 4Q 1 SKEW SELECT 3 3 4F 0:1 * = FS PIN DO ES NO T A PP LY TO , . Wiring Diagram and Frequency Multiply by two with 4F[1:0] = LL. Figure 4 illustrates the IDT5991A and , 3F1 2F0 2F1 1F0 1F1 TES T Figure 7. Wiring Diagram and Frequency Multiply by two with 4F[1:0 , Figure 10. Wiring Diagram and Frequency Multiply by two with 4F[1:0] = LL. Figure 10 illustrates the , OUTPUT CONFIGURATIONS WITH DIFFERENT 4F(1:0)(1) FB Output at 4F(1:0) 1F(1:0) LL LM LH
Integrated Device Technology
Original
FS50M sk 4f1 Wiring Diagram logo
Abstract: CONFIGURATION VDD TEST GN D R EF 4F 0 3F 1 3F 0 2F 1 2F 0 1F 1 FS ABSOLUTE MAXIMUM RATINGS Symbol Rating , VCC+0.5 ­0.5 to +4.6 TA = 85°C TA = 55°C 0.7 1.1 ­65 to +150 44 4F 1 sOE PD PE V DD Q V DD Q 4Q 1 , O DC V t CCJH, HA, M, L, LA Q t SKE W PR t SKEW 0, 1 OTH ER Q tSKE W PR tSK EW 0, 1 t , input allows divide-by-functionality from 1 to 12 through the use of the DS[1:0] inputs. This provides the user with frequency multiplication from 1 to 12 without using divided outputs for feedback. When Integrated Device Technology
Original
Abstract: Symbol 32 31 30 29 28 27 26 25 4F 0 2 23 4F 1 3 22 sOE PE , t S KEW PR t SK EW 0, 1 OTHER Q t SKE W 2 t SKE W 2 INV ER TED Q t SK EW 3, 4 , : â'" Std: 6MHz to 160MHz â'" A: 6MHz to 200MHz 2x, 4x, 1/2, and 1/4 outputs 3-level inputs for , 1Q 1 3 1F1:0 PE TEST 3 3 REF 2Q 0 Skew Select 2Q 1 3 PLL 2F1:0 FB 3 3Q 0 Skew Select 3 3Q 1 3 FS 3F1:0 4Q 0 Skew Select 3 4Q 1 3 4F1 Integrated Device Technology
Original
87952AYI-147LF CQ-13-02

854S296I-33

Abstract: 31 30 29 28 27 26 25 4F 0 2 23 4F 1 3 22 sOE PE 4 21 , t S KEW PR t SK EW 0, 1 OTHER Q t SKE W 2 t SKE W 2 INV ER TED Q t SK EW 3, 4 , : â'" Std: 6MHz to 160MHz â'" A: 6MHz to 200MHz 2x, 4x, 1/2, and 1/4 outputs 3-level inputs for , drive outputs. FUNCTIONAL BLOCK DIAGRAM sO E 1Q 0 Skew Select 3 1Q 1 3 1F1:0 PE TEST 3 3 REF 2Q 0 Skew Select 2Q 1 3 PLL 2F1:0 FB 3 3Q 0 Skew
Integrated Device Technology
Original
854S296I-33 87952AYI-147 854S295I-25 CQ-14-01

15-LCDLCD

Abstract: MAX17126 15× 32× 53.3s75 kHz BEEP 1.5 kHz3 kHz LCD 15 1/41 , LCD7 P0D3/FMIFC/AMIFC 42 P0D2/AMIFC 1 P0C1 P1C0 µPD17071 AMIFC IF P0C0 , PD17071PD17072, 17073.164 .165 9 µPD17071 . 1 P1C0 1C CMOS 2 , b10 b7 b6 b5 b4 b3 b2 b1 b0 1 CALL addr addr 0 addr BR @AR , 1 0 BANK1 Write R/W 54H ASR 0 0 ASR0 0 1 ASR1 1 0 ASR2
NEC
Original
15-LCDLCD MAX17126 14BEE CE061 12-FFPLL LCD10 CPU17K PROMPD17P073PD17071 K3072 PD17071GB- 56QFP10 U11868JJ1V0DS00
Showing first 20 results.