SIII51001-1 SIII51002-1 SIII51003-1 SIII51004-1 SIII51005-1 SIII51006-1 - Datasheet Archive

 

101 Innovation Drive San Jose, CA 95134 www.altera.com SIII5V1-1.1 Copyright © 2007 Altera Corporation. All rights reserved.

 

Stratix III Device Handbook, Volume 1 101 Innovation Drive San Jose, CA 95134 www.altera.com SIII5V1-1.1 Copyright © 2007 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. ii Altera Corporation Contents Chapter Revision Dates . xiii About this Handbook . xv How to Contact Altera . xv Typographic Conventions . xv Section I. Device Core Chapter 1. Stratix III Device Family Overview Introduction . 1­1 Features . 1­2 Architecture Features . 1­5 Logic Array Blocks and Adaptive Logic Modules . 1­5 MultiTrack Interconnect . 1­6 TriMatrix Embedded Memory Blocks . 1­6 DSP Blocks . 1­7 Clock Networks and PLLs . 1­8 I/O Banks and I/O Structure . 1­8 External Memory Interfaces . 1­9 High Speed Differential I/O Interfaces with DPA . 1­10 Hot Socketing and Power-On Reset . 1­10 Configuration . 1­11 Remote System Upgrades . 1­11 IEEE 1149.1 (JTAG) Boundary Scan Testing . 1­12 Design Security . 1­12 SEU Mitigation . 1­12 Programmable Power . 1­13 Signal Integrity . 1­13 Reference and Ordering Information . 1­14 Software . 1­14 Ordering Information . 1­15 Document Revision History . 1­16 Chapter 2. Logic Array Blocks and Adaptive Logic Modules in Stratix III Devices Introduction . Logic Array Blocks . LAB Interconnects . LAB Control Signals . Altera Corporation 2­1 2­1 2­3 2­4 iii Contents Stratix III Device Handbook, Volume 2 Adaptive Logic Modules . 2­5 ALM Operating Modes . 2­8 Register Chain . 2­20 ALM Interconnects . 2­22 Clear and Preset Logic Control . 2­23 LAB Power Management Techniques . 2­23 Conclusion . 2­24 Document Revision History . 2­24 Chapter 3. MultiTrack Interconnect in Stratix III Devices Introduction . 3­1 Row Interconnects . 3­1 Column Interconnects . 3­3 Memory Block Interface . 3­8 DSP Block Interface . 3­10 I/O Block Connections to Interconnect . 3­13 Conclusion . 3­14 Document Revision History . 3­15 Chapter 4. TriMatrix Embedded Memory Blocks in Stratix III Devices Introduction . 4­1 Overview . 4­1 TriMatrix Memory Block Types . 4­3 Parity Bit Support . 4­3 Byte Enable Support . 4­3 Packed Mode Support . 4­5 Address Clock Enable Support . 4­5 Mixed Width Support . 4­7 Asynchronous Clear . 4­7 Error Correction Code (ECC) Support . 4­8 Memory Modes . 4­9 Single Port RAM . 4­10 Simple Dual-Port Mode . 4­12 True Dual-Port Mode . 4­15 Shift-Register Mode . 4­17 ROM Mode . 4­18 FIFO Mode . 4­19 Clocking Modes . 4­19 Independent Clock Mode . 4­19 Input/Output Clock Mode . 4­20 Read/Write Clock Mode . 4­20 Single Clock Mode . 4­20 Design Considerations . 4­20 Selecting TriMatrix Memory Blocks . 4­20 Conflict Resolution . 4­21 Read During Write . 4­21 Power-Up Conditions and Memory Initialization . 4­24 iv Altera Corporation Contents Contents Power Management . 4­24 Conclusion . 4­24 Document Revision History . 4­25 Chapter 5. DSP Blocks in Stratix III Devices Introduction . 5­1 DSP Block Overview . 5­1 Simplified DSP Operation . 5­3 Operational Modes Overview . 5­9 DSP Block Resource Descriptions . 5­10 Input Registers . 5­11 Multiplier and First-Stage Adder . 5­15 Pipeline Register Stage . 5­16 Second-Stage Adder . 5­16 Round and Saturation Stage . 5­17 Second Adder and Output Registers . 5­17 Operational Mode Descriptions . 5­18 Independent Multiplier Modes . 5­18 9-, 12- and 18-Bit Multiplier . 5­18 36-Bit Multiplier . 5­22 Double Multiplier . 5­23 Two-Multiplier Adder Sum Mode . 5­25 18 × 18 Complex Multiply . 5­29 Four-Multiplier Adder . 5­31 Multiply Accumulate Mode . 5­33 Shift Modes . 5­34 Rounding and Saturation Mode . 5­36 DSP Block Control Signals . 5­39 Application Examples . 5­41 FIR Example . 5­41 FFT Example . 5­48 Software Support . 5­49 Conclusion . 5­49 Document Revision History . 5­50 Chapter 6. Clock Networks and PLLs in Stratix III Devices Introduction . 6­1 Clock Networks in Stratix III Devices . 6­1 Clock Input Connections to PLLs . 6­12 Clock Output Connections . 6­13 Clock Source Control for PLLs . 6­14 Clock Control Block . 6­16 Clock Enable Signals . 6­19 PLLs in Stratix III Devices . 6­21 Stratix III PLL Hardware Overview . 6­23 Stratix III PLL Software Overview . 6­27 Clock Feedback Modes . 6­30 Altera Corporation v Contents Stratix III Device Handbook, Volume 2 Clock Multiplication and Division . Post-Scale Counter Cascading . Programmable Duty Cycle . PLL Control Signals . Clock Switchover . Programmable Bandwidth . Phase-Shift Implementation . PLL Reconfiguration . Spread-Spectrum Tracking . PLL Specifications . Conclusion . Document Revision History . 6­36 6­37 6­38 6­38 6­39 6­45 6­48 6­50 6­62 6­62 6­62 6­62 Section II. I/O Interfaces Chapter 7. Stratix III Device I/O Features Introduction . 7­1 Stratix III I/O Standards Support . 7­1 I/O Standards and Voltage Levels . 7­3 Stratix III I/O Banks . 7­5 Modular I/O Banks . 7­7 Stratix III I/O Structure . 7­13 3.3-V I/O Interface . 7­15 External Memory Interfaces . 7­16 High-Speed Differential I/O with DPA Support . 7­16 Programmable Current Strength . 7­17 Programmable Slew Rate Control . 7­18 Programmable Delay . 7­19 Open-Drain Output . 7­19 Bus Hold . 7­19 Programmable Pull-Up Resistor . 7­20 MultiVolt I/O Interface . 7­20 OCT Support . 7­21 LVDS Input On-Chip Termination (RD) . 7­27 OCT Calibration . 7­28 OCT Calibration Block Location . 7­28 OCT Calibration Block Architecture . 7­33 OCT Calibration Modes of Operation . 7­33 Termination Schemes for I/O Standards . 7­35 Single-Ended I/O Standards Termination . 7­35 Differential I/O Standards Termination . 7­36 Design Considerations . 7­43 I/O Termination . 7­43 I/O Banks Restrictions . 7­44 vi Altera Corporation Contents Contents I/O Placement Guidelines . 7­45 Conclusion . 7­47 Document Revision History . 7­47 Chapter 8. External Memory Interfaces in Stratix III Devices Introduction . 8­1 Memory Interfaces Pin Support . 8­5 Data and Data Clock/Strobe Pins . 8­5 Optional Parity, DM, BWSn, ECC and QVLD Pins . 8­18 Address and Control/Command Pins . 8­19 Memory Clock Pins . 8­20 Stratix III External Memory Interface Features . 8­22 DQS Phase-Shift Circuitry . 8­22 DQS Logic Block . 8­33 Leveling Circuitry . 8­36 Dynamic On-Chip Termination Control . 8­39 I/O Element (IOE) Registers . 8­39 IOE Features . 8­43 PLL . 8­45 Conclusion . 8­45 Document Revision History . 8­46 Chapter 9. High-Speed Differential I/O Interfaces and DPA in Stratix III Devices Introduction . 9­1 I/O Banks . 9­2 LVDS Channels . 9­3 Differential Transmitter . 9­4 Differential Receiver . 9­6 Receiver Data Realignment Circuit (Bit Slip) . 9­9 Dynamic Phase Aligner (DPA) . 9­10 Synchronizer . 9­11 Differential I/O Termination . 9­11 Left/Right PLLs (PLL_Lx/ PLL_Rx) . 9­12 Clocking . 9­13 Source Synchronous Timing Budget . 9­14 Differential Data Orientation . 9­15 Differential I/O Bit Position . 9­15 Receiver Skew Margin for Non-DPA . 9­17 Differential Pin Placement Guidelines . 9­19 Guidelines for DPA-Enabled Differential Channels . 9­19 Guidelines for DPA-Disabled Differential Channels . 9­26 Document Revision History . 9­32 Altera Corporation vii Contents Stratix III Device Handbook, Volume 2 Section III. Hot Socketing, Configuration, Remote Upgrades, and Testing Chapter 10. Hot Socketing and Power-On Reset in Stratix III Devices Introduction . Stratix III Hot-Socketing Specifications . Devices Can Be Driven Before Power-Up . I/O Pins Remain Tri-Stated During Power-Up . Insertion or Removal of a Stratix III Device from a Powered-Up System . Hot Socketing Feature Implementation in Stratix III Devices . Power-On Reset Circuitry . Power-On Reset Specifications . Conclusion . Document Revision History . 10­1 10­1 10­2 10­2 10­2 10­3 10­4 10­6 10­7 10­7 Chapter 11. Configuring Stratix III Devices Introduction . 11­1 Configuration Devices . 11­1 Configuration Schemes . 11­2 Configuration Features . 11­4 Configuration Data Decompression . 11­5 Design Security Using Configuration Bitstream Encryption . 11­9 Remote System Upgrade . 11­9 Power-On Reset Circuit . 11­9 VCCPGM Pins . 11­10 VCCPD Pins . 11­10 Fast Passive Parallel Configuration . 11­11 FPP Configuration Using a MAX II Device as an External Host . 11­11 FPP Configuration Using a Microprocessor . 11­22 FPP Configuration Using an Enhanced Configuration Device . 11­22 Fast Active Serial Configuration (Serial Configuration Devices) . 11­30 Estimating Active Serial Configuration Time . 11­37 Programming Serial Configuration Devices . 11­38 Passive Serial Configuration . 11­41 PS Configuration Using a MAX II Device as an External Host . 11­42 PS Configuration Using a Microprocessor . 11­49 PS Configuration Using a Configuration Device . 11­50 PS Configuration Using a Download Cable . 11­61 JTAG Configuration . 11­66 Jam STAPL . 11­73 Device Configuration Pins . 11­73 Conclusion . 11­84 Document Revision History . 11­84 viii Altera Corporation Contents Contents Chapter 12. Remote System Upgrades With Stratix III Devices Introduction . 12­1 Enabling Remote Update . 12­4 Configuration Image Types . 12­5 Remote System Upgrade Mode . 12­6 Overview . 12­6 Remote Update Mode . 12­6 Dedicated Remote System Upgrade Circuitry . 12­8 Remote System Upgrade Registers . 12­10 Remote System Upgrade State Machine . 12­13 User Watchdog Timer . 12­14 Quartus II Software Support . 12­15 altremote_update Megafunction . 12­15 Conclusion . 12­16 Document Revision History . 12­16 Chapter 13. IEEE 1149.1 (JTAG) Boundary-Scan Testing in Stratix III Devices Introduction . 13­1 IEEE Std. 1149.1 BST Architecture . 13­2 IEEE Std. 1149.1 Boundary-Scan Register . 13­4 Boundary-Scan Cells of a Stratix III Device I/O Pin . 13­6 IEEE Std. 1149.1 BST Operation Control . 13­9 SAMPLE/PRELOAD Instruction Mode . 13­12 EXTEST Instruction Mode . 13­14 BYPASS Instruction Mode . 13­16 IDCODE Instruction Mode . 13­17 USERCODE Instruction Mode . 13­18 CLAMP Instruction Mode . 13­18 HIGHZ Instruction Mode . 13­18 I/O Voltage Support in JTAG Chain . 13­18 IEEE Std. 1149.1 BST Circuitry . 13­20 IEEE Std. 1149.1 BST for Configured Devices . 13­21 IEEE Std. 1149.1 BST Circuitry (Disabling) . 13­21 IEEE Std. 1149.1 BST Guidelines . 13­22 Boundary-Scan Description Language (BSDL) Support . 13­23 Conclusion . 13­23 References . 13­23 Document Revision History . 13­24 Section IV. Design Security and Single Event Upset (SEU) Mitigation Chapter 14. Design Security in Stratix III Devices Introduction . 14­1 Stratix III Security Protection . 14­2 Security Against Copying . 14­2 Altera Corporation ix Contents Stratix III Device Handbook, Volume 2 Security Against Reverse Engineering . Security Against Tampering . AES Decryption Block . Flexible Security Key Storage . Stratix III Design Security Solution . Security Modes Available . Supported Configuration Schemes . Conclusion . Document Revision History . 14­2 14­2 14­3 14­3 14­4 14­5 14­6 14­9 14­9 Chapter 15. SEU Mitigation in Stratix III Devices Introduction . 15­1 Configuration Error Detection . 15­2 User Mode Error Detection . 15­2 Automated Single Event Upset Detection . 15­6 Critical Error Detection . 15­7 Error Detection Pin Description . 15­8 CRC_ERROR Pin . 15­8 CRITICAL ERROR Pin . 15­8 Error Detection Block . 15­9 Error Detection Registers . 15­10 Error Detection Timing . 15­12 Software Support . 15­13 Recovering From CRC Errors . 15­15 Conclusion . 15­15 Document Revision History . 15­15 Section V. Power and Thermal Management Chapter 16. Programmable Power and Temperature Sensing Diode in Stratix III Devices Introduction . 16­1 Stratix III Power Technology . 16­2 Selectable Core Voltage . 16­2 Programmable Power Technology . 16­3 Relationship Between Selectable Core Voltage and Programmable Power Technology . 16­4 Stratix III External Power Supply Requirements . 16­5 Temperature Sensing Diode . 16­6 External Pin Connections . 16­7 Architecture Description . 16­8 Conclusion . 16­9 Document Revision History . 16­10 x Altera Corporation Contents Contents Section VI. Packaging Information Chapter 17. Stratix III Device Packaging Information Introduction . Thermal Resistance . Package Outlines . Document Revision History . Altera Corporation 17­1 17­2 17­2 17­2 xi Contents xii Stratix III Device Handbook, Volume 2 Altera Corporation Chapter Revision Dates The chapters in this book, Stratix III Device Handbook, Volume 1, were revised on the following dates. Where chapters or groups of chapters are available separately, part numbers are listed. Chapter 1. Stratix III Device Family Overview Revised: May 2007 Part number: SIII51001-1 SIII51001-1.1 Chapter 2. Logic Array Blocks and Adaptive Logic Modules in Stratix III Devices Revised: May 2007 Part number: SIII51002-1 SIII51002-1.1 Chapter 3. MultiTrack Interconnect in Stratix III Devices Revised: November 2006 Part number: SIII51003-1 SIII51003-1.0 Chapter 4. TriMatrix Embedded Memory Blocks in Stratix III Devices Revised: May 2007 Part number: SIII51004-1 SIII51004-1.1 Chapter 5. DSP Blocks in Stratix III Devices Revised: May 2007 Part number: SIII51005-1 SIII51005-1.1 Chapter 6. Clock Networks and PLLs in Stratix III Devices Revised: May 2007 Part number: SIII51006-1 SIII51006-1.1 Chapter 7. Stratix III Device I/O Features Revised: May 2007 Part number: SIII51007-1 SIII51007-1.1 Chapter 8. External Memory Interfaces in Stratix III Devices Revised: May 2007 Part number: SIII51008-1 SIII51008-1.1 Chapter 9. High-Speed Differential I/O Interfaces and DPA in Stratix III Devices Revised: May 2007 Part number: SIII51009-1 SIII51009-1.1 Altera Corporation xiii Chapter Revision Dates Stratix III Device Handbook, Volume 1 Chapter 10. Hot Socketing and Power-On Reset in Stratix III Devices Revised: May 2007 Part number: SIII51010-1 SIII51010-1.1 Chapter 11. Configuring Stratix III Devices Revised: May 2007 Part number: SIII51011-1 SIII51011-1.1 Chapter 12. Remote System Upgrades With Stratix III Devices Revised: May 2007 Part number: SIII51012-1 SIII51012-1.1 Chapter 13. IEEE 1149.1 (JTAG) Boundary-Scan Testing in Stratix III Devices Revised: May 2007 Part number: SIII51013-1 SIII51013-1.1 Chapter 14. Design Security in Stratix III Devices Revised: November 2006 Part number: SIII51014-1 SIII51014-1.0 Chapter 15. SEU Mitigation in Stratix III Devices Revised: May 2007 Part number: SIII51015-1 SIII51015-1.1 Chapter 16. Programmable Power and Temperature Sensing Diode in Stratix III Devices Revised: May 2007 Part number: SIII51016-1 SIII51016-1.1 Chapter 17. Stratix III Device Packaging Information Revised: May 2007 Part number: SIII51017-1 SIII51017-1.1 xiv Altera Corporation About this Handbook This handbook provides comprehensive information about the Altera® Stratix® III family of devices. How to Contact Altera For the most up-to-date information about Altera products, refer to the following table. Contact (1) Contact Method Address Technical support Website www.altera.com/support Technical training Website www.altera.com/training Email custrain@altera.com Product literature Website www.altera.com/literature Altera literature services Email literature@altera.com Non-technical support (General) Email nacomp@altera.com (Software Licensing) Email authorization@altera.com Note to table: (1) Typographic Conventions Visual Cue You can also contact your local Altera sales office or sales representative. This document uses the typographic conventions shown below. Meaning Bold Type with Initial Capital Letters Command names, dialog box titles, checkbox options, and dialog box options are shown in bold, initial capital letters. Example: Save As dialog box. bold type External timing parameters, directory names, project names, disk drive names, filenames, filename extensions, and software utility names are shown in bold type. Examples: fMAX, \qdesigns directory, d: drive, chiptrip.gdf file. Italic Type with Initial Capital Letters Document titles are shown in italic type with initial capital letters. Example: AN 75: High-Speed Board Design. Altera Corporation xv Preliminary Typographic Conventions Visual Cue Italic type Stratix III Device Handbook, Volume 1 Meaning Internal timing parameters and variables are shown in italic type. Examples: tPIA, n + 1. Variable names are enclosed in angle brackets (< >) and shown in italic type. Example: , .pof file. Initial Capital Letters Keyboard keys and menu names are shown with initial capital letters. Examples: Delete key, the Options menu. "Subheading Title" References to sections within a document and titles of on-line help topics are shown in quotation marks. Example: "Typographic Conventions." Courier type Signal and port names are shown in lowercase Courier type. Examples: data1, tdi, input. Active-low signals are denoted by suffix n, e.g., resetn. Anything that must be typed exactly as it appears is shown in Courier type. For example: c:\qdesigns\tutorial\chiptrip.gdf. Also, sections of an actual file, such as a Report File, references to parts of files (e.g., the AHDL keyword SUBDESIGN), as well as logic function names (e.g., TRI) are shown in Courier. 1., 2., 3., and a., b., c., etc. Numbered steps are used in a list of items when the sequence of the items is important, such as the steps listed in a procedure. Bullets are used in a list of items when the sequence of the items is not important. · v The checkmark indicates a procedure that consists of one step only. 1 The hand points to information that requires special attention. c The caution indicates required information that needs special consideration and understanding and should be read prior to starting or continuing with the procedure or process. w The warning indicates information that should be read prior to starting or continuing the procedure or processes. r The angled arrow indicates you should press the Enter key. f The feet direct you to more information on a particular topic. xvi Preliminary Altera Corporation Section I. Device Core This section provides a complete overview of all features relating to the Stratix® III device family, which is the most architecturally advanced, high performance, low power FPGA in the market place. This section includes the following chapters: Chapter 3, MultiTrack Interconnect in Stratix III Devices Chapter 4, TriMatrix Embedded Memory Blocks in Stratix III Devices Chapter 5, DSP Blocks in Stratix III Devices Altera Corporation Chapter 2, Logic Array Blocks and Adaptive Logic Modules in Stratix III Devices Revision History Chapter 1, Stratix III Device Family Overview Chapter 6, Clock Networks and PLLs in Stratix III Devices Refer to each chapter for its own specific revision history. For information on when each chapter was updated, refer to the Chapter Revision Dates section, which appears in the full handbook. Section I­1 Device Core Section I­2 Stratix III Device Handbook, Volume 1 Altera Corporation 1. Stratix III Device Family Overview SIII51001-1 SIII51001-1.1 Introduction The Stratix® III family provides the most architecturally advanced, high performance, low power FPGAs in the market place. Stratix III FPGAs lower power consumption through Altera's innovative Programmable Power Technology, which provides the ability to turn on the performance where needed and turn down the power consumption everywhere else. Selectable Core Voltage and the latest in silicon process optimizations are also employed to deliver the industry's lowest power, high performance FPGAs. Specifically designed for ease of use and rapid system integration, the Stratix III FPGA family offers three family variants optimized to meet different application needs: The Stratix III L family provides balanced logic, memory, and multiplier ratios for mainstream applications. The Stratix III E family is memory and multiplier rich for data-centric applications. The Stratix III GX family contains embedded high-speed serial transceivers and extensive internal memory for high bandwidth applications. Modular I/O banks with a common bank structure for vertical migration lend efficiency and flexibility to the high speed I/O. Package and die enhancements with dynamic on-chip termination, output delay and current strength control provide best-in-class signal integrity. Based on a 1.1-V, 65-nm all-layer copper SRAM process, the Stratix III family is a programmable alternative to custom ASICs and programmable processors for high performance logic, digital signal processing (DSP), and embedded designs and architects. Stratix III devices include optional configuration bit stream security through volatile or non-volatile 256-bit Advanced Encryption Standard (AES) encryption. Where ultra-high reliability is required, Stratix III devices include automatic error detection circuitry to detect data corruption by soft errors in the configuration random-access memory (CRAM) and user memory cells. Altera Corporation May 2007 1­1 Introduction Features Stratix III devices offer the following features: 48,000 to 338,000 equivalent logic elements (LEs), see Table 1­1 2,430 to 20,497 Kbits of enhanced TriMatrix memory consisting of three RAM block sizes to implement true dual-port memory and first-in first-out (FIFO) buffers High-speed DSP blocks provide dedicated implementation of 9×9, 12×12, 18×18, 36×36 multipliers (at up to 550 MHz), multiplyaccumulate functions, and finite impulse response (FIR) filters I/O:GND:PWR ratio of 8:1:1 along with on-die and on-package decoupling for robust signal integrity Programmable Power Technology, which minimizes power while maximizing device performance Selectable Core Voltage, available in low-voltage devices (L ordering code suffix), enables selection of lowest power or highest performance operation Up to 16 global clocks, 88 regional clocks and 116 peripheral clocks per device Up to 12 phase-locked loops (PLLs) per device that support PLL reconfiguration, clock switchover, programmable bandwidth, clock synthesis and dynamic phase shifting Memory interface support with dedicated DQS logic on all I/O banks Support for high-speed external memory interfaces including DDR,DDR2,DDR3 SDRAM, RLDRAM II, QDR II and QDR II+ SRAM on up to 24 modular I/O banks Up to 1,104 user I/O pins arranged in 24 modular I/O banks that support a wide range of industry I/O standards Dynamic On-Chip Termination (OCT) with auto calibration support on all I/O banks High-speed differential I/O support with serializer/deserializer (SERDES) and dynamic phase alignment (DPA) circuitry for 1.25 Gbps performance Support for high-speed networking and communications bus standards including SPI-4.2, SFI-4, SGMII, Utopia IV, 10 Gigabit Ethernet XSLI, Rapid I/O and NPSI The only high-density, high-performance FPGA with support for 256-bit (AES) volatile and non-volatile security key to protect designs Robust on-chip hot socketing and power sequencing support Integrated cyclical redundancy check (CRC) for configuration memory error detection with critical error determination for high availability systems support Built-in error correction coding (ECC) circuitry to detect and correct configuration or user memory error due to SEU events 1­2 Stratix III Device Handbook, Volume 1 Altera Corporation May 2007 Stratix III Device Family Overview Nios II embedded processor support Support for multiple intellectual property megafunctions from Altera® MegaCore® functions and Altera Megafunction Partners Program (AMPP) Table 1­1 lists the Stratix III FPGA family features. Table 1­1. Stratix III FPGA Family Features LEs M9K blocks M144K M144K blocks EP3SL50 EP3SL50 19K 47.5K 108 6 950 1,836 594 2,430 216 4 EP3SL70 EP3SL70 27K 67.5K 150 6 1,350 2,214 844 3,058 288 4 EP3SL110 EP3SL110 43K 107.5K 275 12 2,150 4,203 1,344 5,547 288 8 57K 142.5K 355 16 2,850 5,499 1,781 7,280 384 8 EP3SL200 EP3SL200 80K 200K 468 24 4,000 7,668 2,500 10,168 576 12 EP3SE260 EP3SE260 102K 255K 864 48 5,100 14,688 3,188 17,876 768 12 EP3SL340 EP3SL340 135K 337.5K 1,040 48 6,750 16,272 4,219 20,491 576 12 EP3SE50 EP3SE50 19K 47.5K 400 12 950 5,328 594 5,922 384 4 EP3SE80 EP3SE80 32K 80K 495 12 1,600 6,183 1,000 7,183 672 8 EP3SE110 EP3SE110 43K 107.5K 639 16 2,150 8,055 1,344 9,399 896 8 EP3SE260 EP3SE260 (1) Stratix Enhanced Family ALMs EP3SL150 EP3SL150 Stratix III Logic Family MLAB Blocks 18×18-bit Total Total MLAB Memory multipliers PLLs Embedded Kbits (FIR Mode) Kbits RAM Kbits Device/ Feature 102K 255K 864 48 5,100 14,688 3,188 17,876 768 12 Note to Table 1­1: (1) The EP3SE260 EP3SE260 device is rich in LE, memory, and multiplier resources. Hence, it aligns with both logic (L) and enhanced (E) variants. The Stratix III logic family (L) offers balanced logic, memory, and multipliers to address a wide range of applications, while the enhanced family (E) offers more memory and multipliers per logic and is ideal for wireless, medical imaging, and military applications. Stratix III devices are available in space-saving FineLine BGA packages (see Table 1­2 and Table 1­3). Altera Corporation May 2007 1­3 Stratix III Device Handbook, Volume 1 Introduction Table 1­2 lists the Stratix III FPGA package options and I/O pin counts. Table 1­2. Package Options and I/O Pin Counts Note (1) 484-Pin FineLine BGA (2) 780-Pin FineLine BGA (2) 1152-Pin FineLine BGA (2) 1,517-Pin FineLine BGA (3) 1,760-Pin FineLine BGA (3) EP3SL50 EP3SL50 296 488 - - - EP3SL70 EP3SL70 296 488 - - - EP3SL110 EP3SL110 - 488 744 - - Device EP3SL150 EP3SL150 - 488 744 - - EP3SL200 EP3SL200 - 488 744 880 (4) - EP3SL340 EP3SL340 - - 744 976 1,120 EP3SE50 EP3SE50 296 488 - - - EP3SE80 EP3SE80 - 488 744 - - EP3SE110 EP3SE110 - 488 744 - - EP3SE260 EP3SE260 - 488 744 976 - Note to Table 1­2: (1) (2) (3) (4) The arrows indicate vertical migration. All I/O pin counts include eight dedicated clock inputs (CLK1p, CLK1n, CLK3p, CLK3n, CLK8p, CLK8n, CLK10p and CLK10n) that can be used for data inputs. All I/O pin counts include eight dedicated clock inputs (CLK1p, CLK1n, CLK3p, CLK3n, CLK8p, CLK8n, CLK10p, and CLK10n) and eight dedicated corner PLL clock inputs (PLL_L1_CLKp, PLL_L1_CLKn, PLL_L4_CLKp, PLL_L4_CLKn, PLL_R4_CLKp, PLL_R4_CLKn, PLL_R1_CLKp, and PLL_R1_CLKn) that can be used for data inputs. I/O Bank 1B, 2B, 5B, and 6B are not available in the EP3SL200 EP3SL200 F1517 F1517 FPGA. All Stratix III devices support vertical migration within the same package (for example, you can migrate between the EP3SL50 EP3SL50 and EP3SL70 EP3SL70 devices in the 780-pin FineLine BGA package). Vertical migration allows you to migrate to devices whose dedicated pins, configuration pins, and power pins are the same for a given package across device densities. To ensure that a board layout supports migratable densities within one package offering, enable the applicable vertical migration path within the Quartus® II software (Assignments menu > Device > Migration Devices). You can migrate from the L family to the E family without increasing the number of LEs available. This minimizes the cost of vertical migration. 1­4 Stratix III Device Handbook, Volume 1 Altera Corporation May 2007 Stratix III Device Family Overview Table 1­3 lists the Stratix III FBGA package sizes. Table 1­3. FineLine BGA Package Sizes Dimension 484 Pin 780 Pin Pitch (mm) 1.00 1.00 1.00 1.00 1.00 Area (mm2) 529 841 1,225 1,600 1,849 23/23 29/29 35/35 40/40 43/43 Length/Width (mm/ mm) 1152 Pin 1,517 Pin 1760 Pin Stratix III devices are available in up to three speed grades, -2, -3, and -4, with -2 being the fastest. Stratix III devices are offered in both commercial and industrial temperature range ratings with leaded and lead-free packages. Selectable Core Voltage is available in specially marked lowvoltage devices (L ordering code suffix). Architecture Features The following section briefly describes the various features of the Stratix III family of FPGAs. Logic Array Blocks and Adaptive Logic Modules The Logic Array Block (LAB) is composed of basic building blocks known as Adaptive Logic Modules (ALMs) that can be configured to implement logic, arithmetic, and register functions. Each LAB consists of ten ALMs, carry chains, shared arithmetic chains, LAB control signals, local interconnect, and register chain connection lines. ALMs are part of a unique, innovative logic structure that delivers faster performance, minimizes area, and reduces power consumption. ALMs expand the traditional 4-input look-up table architecture to 7 inputs, increasing performance by reducing LEs, logic levels, and associated routing. In addition, ALMs maximize DSP performance with dedicated functionality to efficiently implement adder trees and other complex arithmetic functions. The Quartus II Compiler places associated logic in an LAB or adjacent LABs, allowing the use of local, shared arithmetic chain, and register chain connections for performance and area efficiency. The Logic Array Block (LAB) of Stratix-III has a new derivative called Memory LAB (or MLAB), which adds SRAM memory capability to the LAB. MLAB is a superset of the LAB and includes all LAB features. MLABs support a maximum of 640-bits of simple dual-port Static Random Access Memory (SRAM). Each ALM in an MLAB can be configured as either a 64×1 or 32×2 block, resulting in a configuration of 64×10 or 32×20 simple dual port SRAM block. MLAB and LAB blocks always co-exist as pairs in all Stratix-III families allowing up to 50% of the logic (LABs) to be traded for memory (MLABs). Altera Corporation May 2007 1­5 Stratix III Device Handbook, Volume 1 Architecture Features f For more information on LABs and ALMs, refer to the Logic Array Blocks and Adaptive Logic Modules in Stratix III Devices chapter in volume 1 of the Stratix III Device Handbook. f For more information on MLAB modes, features and design considerations, refer to the TriMatrix Embedded Memory Blocks in Stratix III Devices chapter in volume 1 of the Stratix III Device Handbook. MultiTrack Interconnect In the Stratix III architecture, connections between ALMs, TriMatrix memory, DSP blocks, and device I/O pins are provided by the MultiTrack interconnect structure with DirectDrive technology. The MultiTrack interconnect consists of continuous, performance-optimized row and column interconnects that span fixed distances. A routing structure with fixed length resources for all devices allows predictable and repeatable performance when migrating through different device densities. The MultiTrack interconnect provides 1-hop connection to 34 adjacent LABs, 2-hop connections to 96 adjacent LABs and 3 hop connections to 160 adjacent LABs. DirectDrive technology is a deterministic routing technology that ensures identical routing resource usage for any function regardless of placement in the device. The MultiTrack interconnect and DirectDrive technology simplify the integration stage of block-based designing by eliminating the reoptimization cycles that typically follow design changes and additions. The Quartus II Compiler also automatically places critical design paths on faster interconnects to improve design performance. f For more information, refer to the MultiTrack Interconnect in Stratix III Devices chapter of the Stratix III Device Handbook, Volume 1. TriMatrix Embedded Memory Blocks TriMatrix embedded memory blocks provide three different sizes of embedded SRAM to efficiently address the needs of Stratix III FPGA designs. TriMatrix memory includes the following blocks: 640-bit MLAB blocks optimized to implement filter delay lines, small FIFO buffers and shift registers 9-Kbit M9K blocks that can be used for general purpose memory applications 144-Kbit M144K M144K blocks that are ideal for processor code storage, packet and video frame buffering 1­6 Stratix III Device Handbook, Volume 1 Altera Corporation May 2007 Stratix III Device Family Overview Each embedded memory block can be independently configured to be a single- or dual-port RAM, ROM, or shift register via the Quartus II MegaWizard. Multiple blocks of the same type can also be stitched together to produce larger memories with minimal timing penalty. TriMatrix memory provides up to 16,272 Kbits of embedded SRAM at up to 600 MHz operation. f For more information on TriMatrix memory blocks, modes, features, and design considerations, refer to the TriMatrix Embedded Memory Blocks in Stratix III Devices chapter in volume 1 of the Stratix III Device Handbook. DSP Blocks Stratix III devices have dedicated high-performance digital signal processing (DSP) blocks optimized for DSP applications requiring high data throughput. Stratix III devices provide you with the ability to implement various high performance DSP functions easily. Complex systems such as WiMAX, 3GPP WCDMA, CDMA2000 CDMA2000, voice over Internet protocol (VoIP), H.264 video compression and high-definition television (HDTV) require high performance DSP blocks to process data. These system designs typically use DSP blocks to implement finite impulse response (FIR) filters, complex FIR filters, infinite impulse response (IIR) filters, fast Fourier transform (FFT) functions, and discrete cosine transform (DCT) functions. Stratix III devices have up to 112 DSP blocks. The architectural highlights of the Stratix III DSP block are the following: High performance, power optimized, fully pipelined multiplication operations Native support for 9-bit, 12-bit, 18-bit, 36-bit word lengths Native support for 18-bit complex multiplications Efficient support for floating point arithmetic formats (24-bit for Single Precision and 53-bit for Double Precision) Signed and unsigned input support Built-in addition, subtraction, and accumulation units to efficiently combine multiplication results Cascading 18-bit input bus to form tap-delay lines Cascading 44-bit output bus to propagate output results from one block to the next block Rich and flexible arithmetic rounding and saturation units Efficient barrel shifter support Loopback capability to support adaptive filtering DSP block multipliers can optionally feed an adder/subtractor or accumulator in the block depending on user configuration. This option saves ALM routing resources and increases performance, because all Altera Corporation May 2007 1­7 Stratix III Device Handbook, Volume 1 Architecture Features connections and blocks are inside the DSP block. Additionally, the DSP Block input registers can efficiently implement shift registers for FIR filter applications, and the Stratix III DSP blocks support rounding and saturation. The Quartus II software includes megafunctions that control the mode of operation of the DSP blocks based on user parameter settings. f For more information, refer to the DSP Blocks in Stratix III Devices chapter in volume 1 of the Stratix III Device Handbook. Clock Networks and PLLs Stratix III devices provide dedicated Global Clock Networks (GCLKs), Regional Clock Networks (RCLKs), and Periphery Clock Networks (PCLKs). These clocks are organized into a hierarchical clock structure that provides up to 104 unique clock domains (16 GCLK + 88 RCLK) within the Stratix III device and allows for up to 38 (16 GCLK + 22 RCLK) unique GCLK/RCLK clock sources per device quadrant. Stratix III delivers abundant PLL resources with up to 12 PLLs per device and up to 10 outputs per PLL. Every output can be independently programmed creating a unique, customizable clock frequency with no fixed relation to any other input or output clock. Inherent jitter filtration and fine granularity control over multiply, divide ratios and dynamic phase-shift reconfiguration provide the high-performance precision required in today's high-speed applications. Stratix III device PLLs are feature rich, supporting advanced capabilities such as clock switchover, reconfigurable phase shift, PLL reconfiguration, and reconfigurable bandwidth. PLLs can be used for general-purpose clock management supporting multiplication, phase shifting, and programmable duty cycle. Stratix III PLLs also support external feedback mode, spread-spectrum input clock tracking and post-scale counter cascading. f For more information, refer to the Clock Networks and PLLs in Stratix III Devices chapter in volume 1 of the Stratix III Device Handbook. I/O Banks and I/O Structure Stratix III devices contain up to 24 modular I/O banks, each of which contains 24, 32, 36, 40 or 48 I/Os. This modular bank structure improves pin efficiency and eases device migration. The left and right side I/O banks contain circuitry to support external memory interfaces at speeds up to 333 MHz and high-speed differential I/O interfaces meeting up to 1.25 Gbps performance. The top and bottom I/O banks contain circuitry to support external memory interfaces at speeds up to 400 MHz, high-speed differential inputs and outputs running at speeds up to 800 MHz and 500 MHz respectively. 1­8 Stratix III Device Handbook, Volume 1 Altera Corporation May 2007 Stratix III Device Family Overview Stratix III devices support a wide range of industry I/O standards, including single-ended, voltage referenced single-ended, and differential I/O standards. The Stratix III I/O supports programmable bus hold, programmable pull-up resistor, programmable slew rate, programmable output delay control, and open-drain output. Stratix III devices also support on-chip series (RS) and on-chip parallel (RT) termination with auto calibration for single-ended I/O standards and on-chip differential termination (RD) for LVDS I/O standards on Left/Right I/O banks. Dynamic OCT is also supported on bi-directional I/O pins in all I/O banks. f For more information, refer to the Stratix III Device I/O Features chapter in volume 1 of the Stratix III Device Handbook. External Memory Interfaces The Stratix III I/O structure has been completely redesigned from the ground up to provide flexibility and enable high-performance support for existing and emerging external memory standards such as DDR, DDR2, DDR3, QDRII, QDRII+ and RLDRAMII at frequencies of up to 400 MHz. Packed with features such as dynamic on-chip termination, trace mismatch compensation, read/write levelling, half-rate registers, 4- to 36-bit programmable DQ group widths, Stratix III I/O's supply the built in functionality required for rapid and robust implementation of external memory interfaces. Double data-rate support is found on all sides of the Stratix III device. Stratix III devices provide an efficient architecture to quickly and easily fit wide external memory interfaces exactly where you want them. A self-calibrating soft IP core (ALTMEMPHY) optimized to take advantage of Stratix III device I/O along with the new Quartus II timing analysis tool (TimeQuest) provide the total solution for the highest reliable frequency of operation across process voltage and temperature. f Altera Corporation May 2007 For more information on external memory interfaces, refer to the External Memory Interfaces in Stratix III Devices chapter in volume 1 of the Stratix III Device Handbook. 1­9 Stratix III Device Handbook, Volume 1 Architecture Features High Speed Differential I/O Interfaces with DPA Stratix III devices contain dedicated circuitry for supporting differential standards at speeds up to 1.25 Gbps. The high-speed differential I/O circuitry supports the following high speed I/O interconnect standards and applications: Utopia IV, SPI-4.2, SFI-4, 10 Gigabit Ethernet XSLI, Rapid I/O, and NPSI. Stratix III devices support 2×, 4×, 6×, 7×, 8× and 10× SERDES modes for high speed differential I/O interfaces and 4×, 6×, 7×, 8× and 10× SERDES modes when using the dedicated DPA circuitry. DPA minimizes bit errors, simplifies PCB layout and timing management for high-speed data transfer, and eliminates channel-to-channel and channelto-clock skew in high-speed data transmission systems. Soft CDR can also be implemented, enabling low-cost 1.25-Gbps clock embedded serial links. Stratix III devices have the following dedicated circuitry for high-speed differential I/O support: f Differential I/O buffer Transmitter serializer Receiver deserializer Data realignment Dynamic phase aligner (DPA) Soft CDR functionality Synchronizer (FIFO buffer) PLLs For more information, refer to the High Speed Differential I/O Interfaces with DPA in Stratix III Devices chapter in volume 1 of the Stratix III Device Handbook. Hot Socketing and Power-On Reset Stratix III devices are hot-socketing compliant. Hot socketing is also known as hot plug-in or hot swap, and power sequencing support without the use of any external devices. Robust on-chip hot-socketing and power-sequencing support ensures proper device operation independent of the power-up sequence. You can insert or remove a Stratix III board in a system during system operation without causing undesirable effects to the running system bus or the board that was inserted into the system. The hot-socketing feature also makes it easier to use Stratix III devices on printed circuit boards (PCBs) that also contain a mixture of 3.0-V, 2.5-V, 1.8-V, 1.5-V and 1.2-V devices. With the Stratix III hot socketing feature, you no longer need to ensure a proper power-up sequence for each device on the board. 1­10 Stratix III Device Handbook, Volume 1 Altera Corporation May 2007 Stratix III Device Family Overview f For more information, refer to the Hot Socketing and Power-On Reset in Stratix III Devices chapter in volume 1 of the Stratix III Device Handbook. Configuration Stratix III devices are configured using one of the following four configuration schemes: Fast passive parallel (FPP) Fast active serial (AS) Passive serial (PS) Joint Test Action Group (JTAG) All configuration schemes use either an external controller (for example, a MAX® II device or microprocessor), a configuration device, or a download cable. Stratix III devices support configuration data decompression, which saves configuration memory space and time. This feature allows you to store compressed configuration data in configuration devices or other memory and transmit this compressed bitstream to Stratix III devices. During configuration, the Stratix III device decompresses the bitstream in real time and programs its SRAM cells. Stratix III devices support decompression in the FPP when using a MAX II device/microprocessor + flash, fast AS, and PS configuration schemes. The Stratix III decompression feature is not available in the FPP when using the enhanced configuration device and JTAG configuration schemes. f For more information, refer to the Configuring Stratix III Devices chapter in volume 1 of the Stratix III Device Handbook. Remote System Upgrades Stratix III devices feature remote system upgrade capability, allowing error-free deployment of system upgrades from a remote location securely and reliably. Soft logic (either the Nios embedded processor or user logic) implemented in a Stratix III device can download a new configuration image from a remote location, store it in configuration memory, and direct the dedicated remote system upgrade circuitry to initiate a reconfiguration cycle. The dedicated circuitry performs error detection during and after the configuration process, and can recover from an error condition by reverting back to a safe configuration image, and provides error status information. This dedicated remote system upgrade circuitry is unique to Stratix series FPGAs and helps to avoid system downtime. Altera Corporation May 2007 1­11 Stratix III Device Handbook, Volume 1 Architecture Features f For more information refer to the Remote System Upgrades with Stratix III Devices chapter in volume 1 of the Stratix III Device Handbook. IEEE 1149.1 (JTAG) Boundary Scan Testing Stratix III devices support the JTAG IEEE Std. 1149.1 specification. The Boundary-Scan Test (BST) architecture offers the capability to test pin connections without using physical test probes and capture functional data while a device is operating normally. Boundary-scan cells in the Stratix III device can force signals onto pins or capture data from pin or logic array signals. Forced test data is serially shifted into the boundaryscan cells. Captured data is serially shifted out and externally compared to expected results. In addition to BST, you can use the IEEE Std. 1149.1 controller for Stratix III device in-circuit reconfiguration (ICR). f For more information refer to the IEEE 1149.1 (JTAG) Boundary Scan Testing in Stratix III Devices chapter in volume 1 of the Stratix III Device Handbook. Design Security Stratix III devices are the only high-density, high-performance FPGAs with support for 256-bit volatile and non-volatile security keys to protect designs against copying, reverse engineering, and tampering. Stratix III devices have the ability to decrypt a configuration bitstream using the Advanced Encryption Standard (AES) algorithm, an industry standard encryption algorithm that is FIPS-197 FIPS-197 certified and requires a 256-bit security key. The design security feature is available when configuring Stratix III FPGAs using the fast passive parallel (FPP) configuration mode with an external host (such as a MAX II device or microprocessor), or when using fast active serial (AS) or passive serial (PS) configuration schemes. f For more information on the design security feature, refer to the Design Security in Stratix III Devices chapter in volume 1 of the Stratix III Device Handbook. SEU Mitigation Stratix III devices have built-in error detection circuitry to detect data corruption due to soft errors in the configuration random-access memory (CRAM) cells. This feature allows all CRAM contents to be read and verified continuously during user mode operation to match a configuration-computed CRC value. The enhanced CRC circuit and frame-based configuration architecture allows detection and location of multiple, single, and adjacent bit errors which, in conjunction with a soft 1­12 Stratix III Device Handbook, Volume 1 Altera Corporation May 2007 Stratix III Device Family Overview circuit supplied as a reference design, allows don't-care soft errors in the CRAM to be ignored during device operation. This provides a step decrease in the effective soft error rate, increasing system reliability. On-chip memory block SEU mitigation is also offered using the 9th bit and a configurable Megafunction in Quartus II for MLAB and M9K blocks while the M144K M144K memory blocks have built-in error correction code (ECC) circuitry. f For more information on the dedicated error detection circuitry, refer to the SEU Mitigation in Stratix III Devices chapter in volume 1 of the Stratix III Device Handbook. Programmable Power Stratix III delivers Programmable Power, the only FPGA with user programmable power options balancing today's power and performance requirements. Stratix III devices utilize the most advanced power saving techniques including a variety of process, circuit, and architecture optimizations and innovations. In addition, user controllable power reduction techniques provide an optimal balance of performance and power reduction specific for each design configured into the Stratix III FPGA. The Quartus II software (starting from Version 6.1) automatically optimizes designs to meet the performance goals while simultaneously leveraging the programmable power saving options available in the Stratix III FPGA without the need for any changes to the design flow. f For more information on Programmable Power in Stratix III devices, refer to the following documents: Programmable Power and Temperature Sensing Diode in Stratix III Devices chapter of the Stratix III Device Handbook, Volume 1 Power Optimization in the Stratix III Devices Application Note Stratix III Power White Paper Signal Integrity Stratix III devices simplify the challenge of signal integrity through a number of chip, package, and board level enhancements to enable efficient high speed data transfer into and out of the device. These enhancements include: Altera Corporation May 2007 8:1:1 user I/O/Gnd/Vcc ratio to reduce the loop inductance in the package Dedicated power supply for each I/O bank, limit of I/Os is 24 to 48 I/Os per bank, to help limit simultaneous switching noise 1­13 Stratix III Device Handbook, Volume 1 Reference and Ordering Information f Reference and Ordering Information Programmable slew-rate support with up to 4 settings to match desired I/O standard, control noise, and overshoot Programmable output-current drive strength support with up to 4 settings to match desired I/O standard performance Programmable output-delay support to control rise/fall times and adjust duty cycle, compensate for skew and reduce simultaneous switching outputs (SSO) noise Dynamic OCT with auto calibration support for series and parallel OCT and differential OCT support for LVDS I/O standard on the left/right banks For more information on SI support in Quartus II, refer to the Quartus II Handbook. The following section describes Stratix III device software support and ordering information. Software Stratix III devices are supported by the Altera Quartus II design software, version 6.1, which provides a comprehensive environment for system-on-a-programmable-chip (SOPC) design. The Quartus II software includes HDL and schematic design entry, compilation and logic synthesis, full simulation and advanced timing analysis, SignalTap® II logic analyzer, and device configuration. See the Quartus II Handbook for more information on the Quartus II software features. The Quartus II software supports the Windows XP/2000/NT/98 XP/2000/NT/98, Sun Solaris, Linux Red Hat v7.1 and HP-UX operating systems. It also supports seamless integration with industry-leading EDA tools through the NativeLink® interface. 1­14 Stratix III Device Handbook, Volume 1 Altera Corporation May 2007 Stratix III Device Family Overview Ordering Information Figure 1­1 describes the ordering codes for Stratix III devices. For more information on a specific package, refer to the Package Information for Stratix III Devices chapter of the Stratix III Device Handbook. Figure 1­1. Stratix III Device Packaging Ordering Information EP3SL 150 F 1152 C 2 ES Family Signature Optional Suffix Indicates specific device options ES: Engineering sample N: Lead-free devices L: Low-voltage devices EP3SL: Stratix III Logic EP3SE: Stratix III DSP/Memory EP3SGX: Stratix III Transceiver Device Type Speed Grade 50 70 80 110 150 200 260 340 Package Type F: FineLine BGA (FBGA) Altera Corporation May 2007 2, 3, or 4, with 2 being the fastest Operating Temperature C: Commercial temperature (t J = 0 C to 85 C) I : Industrial temperature (t J = - 40 C to 100 C) Pin Count Number of pins for a particular package: 484 780 1152 1517 1760 1­15 Stratix III Device Handbook, Volume 1 Document Revision History Document Revision History Table 1­4 shows the revision history for this document. Table 1­4. Document Revision History Date and Document Version May 2007 v 1.1 Changes Made Summary of Changes Minor formatting changes, fixed PLL numbers and ALM, LE and MLAB bit counts in Table 1­1. - November 2006 Initial Release v1.0 1­16 Stratix III Device Handbook, Volume 1 - Altera Corporation May 2007 2. Logic Array Blocks and Adaptive Logic Modules in Stratix III Devices SIII51002-1 SIII51002-1.1 Introduction This chapter describes the features of the logic array block (LAB) in the Stratix® III core fabric. The logic array block is composed of basic building blocks known as adaptive logic modules (ALMs) that can be configured to implement logic functions, arithmetic functions, and register functions. Logic Array Blocks Each LAB consists of ten ALMs, carry chains, shared arithmetic chains, LAB control signals, local interconnect, and register chain connection lines. The local interconnect transfers signals between ALMs in the same LAB. The direct link interconnect allows a LAB to drive into the local interconnect of its left and right neighbors. Register chain connections transfer the output of the ALM register to the adjacent ALM register in an LAB. The Quartus® II Compiler places associated logic in an LAB or adjacent LABs, allowing the use of local, shared arithmetic chain, and register chain connections for performance and area efficiency. Figure 2­1 shows the Stratix III LAB structure and the LAB interconnects. Altera Corporation May 2007 2­1 Logic Array Blocks Figure 2­1. Stratix III LAB Structure C4 C12 Row Interconnects of Variable Speed & Length R20 R4 ALMs Direct link interconnect from adjacent block Direct link interconnect from adjacent block Direct link interconnect to adjacent block Direct link interconnect to adjacent block Local Interconnect LAB MLAB Local Interconnect is Driven from Either Side by Columns & LABs, & from Above by Rows Column Interconnects of Variable Speed & Length The LAB of Stratix III has a new derivative called Memory LAB (MLAB), which adds look-up table (LUT)-based SRAM capability to the LAB as shown in Figure 2­2. The MLAB supports a maximum of 640-bits of simple dual-port static random access memory (SRAM). You can configure each ALM in an MLAB as either a 64 × 1 or 32 × 2 block, resulting in a configuration of 64 × 10 or 32 × 20 simple dual port SRAM block. MLAB and LAB blocks always co-exist as pairs in all Stratix III families. MLAB is a superset of the LAB and includes all LAB features. Figure 2­2 shows an overview of LAB and MLAB topology. f The MLAB is described in detail in the TriMatrix Embedded Memory Blocks in Stratix III Devices chapter in volume 1 of the Stratix III Device Handbook. 2­2 Stratix III Device Handbook, Volume 1 Altera Corporation May 2007 Logic Array Blocks and Adaptive Logic Modules in Stratix III Devices Figure 2­2. Stratix III LAB and MLAB Structure LUT-based-64 x 1 Simple dual port SRAM (1) ALM LUT-based-64 x 1 Simple dual port SRAM (1) LUT-based-64 x 1 Simple dual port SRAM (1) LUT-based-64 x 1 Simple dual port SRAM (1) LUT-based-64 x 1 Simple dual port SRAM (1) ALM ALM ALM LAB Control Block LUT-based-64 x 1 Simple dual port SRAM ALM LAB Control Block (1) ALM LUT-based-64 x 1 Simple dual port SRAM (1) LUT-based-64 x 1 Simple dual port SRAM (1) LUT-based-64 x 1 Simple dual port SRAM (1) LUT-based-64 x 1 Simple dual port SRAM (1) ALM ALM MLAB ALM ALM LAB Note to Figure 2­2: (1) You can use MLAB ALM as a regular LAB ALM or configure it as a dual-port SRAM, as shown. LAB Interconnects The LAB local interconnect can drive ALMs in the same LAB. It is driven by column and row interconnects and ALM outputs in the same LAB. Neighboring LABs/MLABs, M9K RAM blocks, M144K M144K blocks, or DSP blocks from the left and right can also drive a LAB's local interconnect through the direct link connection. The direct link connection feature minimizes the use of row and column interconnects, providing higher performance and flexibility. Each ALM can drive 30 ALMs through fast local and direct link interconnects. Altera Corporation May 2007 2­3 Stratix III Device Handbook, Volume 1 Logic Array Blocks Figure 2­3 shows the direct link connection. Figure 2­3. Direct Link Connection Direct link interconnect from left LAB, TriMatrix memory block, DSP block, or IOE output Direct link interconnect from right LAB, TriMatrix memory block, DSP block, or IOE output ALMs ALMs Direct link interconnect to right Direct link interconnect to left Local Interconnect MLAB LAB LAB Control Signals Each LAB contains dedicated logic for driving control signals to its ALMs. The control signals include three clocks, three clock enables, two asynchronous clears, a synchronous clear, and synchronous load control signals. This gives a maximum of 10 a control signals at a time. Although you generally use synchronous load and clear signals when implementing counters, you can also use them with other functions. Each LAB has two unique clock sources and three clock enable signals, as shown in Figure 2­4. The LAB control block can generate up to three clocks using the two clock sources and three clock enable signals. Each LAB's clock and clock enable signals are linked. For example, any ALM in a particular LAB using the labclk1 signal also uses labclkena1 signal. If the LAB uses both the rising and falling edges of a clock, it also uses two LAB-wide clock signals. De-asserting the clock enable signal turns off the corresponding LAB-wide clock. 2­4 Stratix III Device Handbook, Volume 1 Altera Corporation May 2007 Logic Array Blocks and Adaptive Logic Modules in Stratix III Devices The LAB row clocks [5.0] and LAB local interconnect generate the LAB-wide control signals. The MultiTrackTM interconnect's inherent low skew allows clock and control signal distribution in addition to data. Figure 2­4 shows the LAB control signal generation circuit. Figure 2­4. LAB-Wide Control Signals There are two unique clock signals per LAB. 6 Dedicated Row LAB Clocks 6 6 Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect labclk0 labclk1 labclkena0 or asyncload or labpreset Adaptive Logic Modules Altera Corporation May 2007 labclk2 labclkena1 labclkena2 labclr1 syncload labclr0 synclr The basic building block of logic in the Stratix III architecture, the adaptive logic module (ALM), provides advanced features with efficient logic utilization. Each ALM contains a variety of look-up table (LUT)-based resources that can be divided between two combinational adaptive LUTs (ALUTs) and two registers. With up to eight inputs to the two combinational ALUTs, one ALM can implement various combinations of two functions. This adaptability allows an ALM to be completely backward-compatible with four-input LUT architectures. One ALM can also implement any function of up to six inputs and certain seven-input functions. 2­5 Stratix III Device Handbook, Volume 1 Adaptive Logic Modules In addition to the adaptive LUT-based resources, each ALM contains two programmable registers, two dedicated full adders, a carry chain, a shared arithmetic chain, and a register chain. Through these dedicated resources, an ALM can efficiently implement various arithmetic functions and shift registers. Each ALM drives all types of interconnects: local, row, column, carry chain, shared arithmetic chain, register chain, and direct link interconnects. Figure 2­5 shows a high-level block diagram of the Stratix III ALM while Figure 2­6 shows a detailed view of all the connections in an ALM. Figure 2­5. High-Level Block Diagram of the Stratix III ALM shared_arith_in carry_in Combinational/Memory ALUT0 reg_chain_in labclk To general or local routing dataf0 datae0 6-Input LUT adder0 D Q dataa To general or local routing reg0 datab datac datad datae1 adder1 D Q 6-Input LUT To general or local routing reg1 dataf1 To general or local routing Combinational/Memory ALUT1 reg_chain_out shared_arith_out 2­6 Stratix III Device Handbook, Volume 1 carry_out Altera Corporation May 2007 Altera Corporation May 2007 dataf1 datae1 datad datac dataa datab datae0 dataf0 shared_arith_out 3-INPUT LUT 3-INPUT LUT 4-INPUT LUT 3-INPUT LUT 3-INPUT LUT 4-INPUT LUT shared_arith_in carry_out + + shared_arith_out VCC GND clk[2:0] sclr syncload aclr[1:0] reg_chain_in D D CLR CLR Q Q row, column direct link routing row, column direct link routing local interconnect row, column direct link routing row, column direct link routing local interconnect Logic Array Blocks and Adaptive Logic Modules in Stratix III Devices Figure 2­6. Stratix III ALM Details 2­7 Stratix III Device Handbook, Volume 1 Adaptive Logic Modules One ALM contains two programmable registers. Each register has data, clock, clock enable, synchronous and asynchronous clear, and synchronous load/clear inputs. Global signals, general-purpose I/O pins, or any internal logic can drive the register's clock and clear control signals. Either general-purpose I/O pins or internal logic can drive the clock enable. For combinational functions, the register is bypassed and the output of the LUT drives directly to the outputs of an ALM. Each ALM has two sets of outputs that drive the local, row, and column routing resources. The LUT, adder, or register output can drive these output drivers (refer to Figure 2­6). For each set of output drivers, two ALM outputs can drive column, row, or direct link routing connections, and one of these ALM outputs can also drive local interconnect resources. This allows the LUT or adder to drive one output while the register drives another output. This feature, called register packing, improves device utilization because the device can use the register and the combinational logic for unrelated functions. Another special packing mode allows the register output to feed back into the LUT of the same ALM so that the register is packed with its own fan-out LUT. This provides another mechanism for improved fitting. The ALM can also drive out registered and unregistered versions of the LUT or adder output. ALM Operating Modes The Stratix III ALM can operate in one of the following modes: Normal Extended LUT Mode Arithmetic Shared Arithmetic LUT-Register Each mode uses ALM resources differently. In each mode, eleven available inputs to an ALM-the eight data inputs from the LAB local interconnect, carry-in from the previous ALM or LAB, the shared arithmetic chain connection from the previous ALM or LAB, and the register chain connection-are directed to different destinations to implement the desired logic function. LAB-wide signals provide clock, asynchronous clear, synchronous clear, synchronous load, and clock enable control for the register. These LAB-wide signals are available in all ALM modes. 1 2­8 Stratix III Device Handbook, Volume 1 Refer to "LAB Control Signals" on page 2­4 for more information on the LAB-wide control signals. Altera Corporation May 2007 Logic Array Blocks and Adaptive Logic Modules in Stratix III Devices The Quartus II software and supported third-party synthesis tools, in conjunction with parameterized functions such as the library of parameterized modules (LPM) functions, automatically choose the appropriate mode for common functions such as counters, adders, subtractors, and arithmetic functions. Normal Mode The normal mode is suitable for general logic applications and combinational functions. In this mode, up to eight data inputs from the LAB local interconnect are inputs to the combinational logic. The normal mode allows two functions to be implement