SH7670 SH7670/SH7671/SH7672/SH7673 R5S76700/R5S76710/R5S76720/R5S76730 - Datasheet Archive

 

SH7670 Group Example of BSC SDRAM Interface Connection (32-Bit Data Bus) Introduction This application note introduces the

 

APPLICATION NOTE SH7670 SH7670 Group Example of BSC SDRAM Interface Connection (32-Bit Data Bus) Introduction This application note introduces the synchronous DRAM (SDRAM) interface of the bus state controller (BSC) of SH7670/SH7671/SH7672/SH7673 SH7670/SH7671/SH7672/SH7673 products and includes a sample application. Target Device SH7670 SH7670 Contents 1. Preface. 2 2. Description of Sample Application . 3 3. Listing of Sample Program. 13 4. Documents for Reference . 16 REJ06B0782-0100/Rev.1.00 November 2008 Page 1 of 18 SH7670 SH7670 Group Example of BSC SDRAM Interface Connection (32-Bit Data Bus) 1. Preface 1.1 Specifications · Two 256-Mbit (4 Mwords × 16 bits × 4 banks) SDRAM modules are connected to the SH7670 SH7670 with a 32-bit data bus width. · SDRAM is initialized by using the SDRAM interface function of the SH7670 SH7670. 1.2 Module Used · Bus state controller (BSC) 1.3 Applicable Conditions · MCU · Operating frequency · Integrated development environement · C compiler · Compiler options 1.4 SH7670/SH7671/SH7672/SH7673 SH7670/SH7671/SH7672/SH7673 (R5S76700/R5S76710/R5S76720/R5S76730 R5S76700/R5S76710/R5S76720/R5S76730) Internal clock: 200 MHz Bus clock: 66.67 MHz Peripheral clock: 33.33 MHz High-performance Embedded Workshop Ver.4.03.00 from Renesas Technology SuperH RISC Engine Family C/C+ Compiler Package Ver.9.01 Release01 from Renesas Technology Default settings of High-performance Embedded Workshop (-cpu = sh2afpu -fpu = single -object = "$(CONFIGDIR)\$(FILELEAF).obj" -debug -gbr = auto -chgincpath -errorpath -global_volatile = 0 -opt_range = all -infinite_loop = 0 -del_vacant_loop = 0 -struct_alloc = 1 -nologo) Related Application Note The operation of the reference program for this document was confirmed with the setting conditions described in the SH7670 SH7670 Group Application Note: Example of Initialization (REJ06B0799 REJ06B0799). Please refer to that document in combination with this one. REJ06B0782-0100/Rev.1.00 November 2008 Page 2 of 18 SH7670 SH7670 Group Example of BSC SDRAM Interface Connection (32-Bit Data Bus) 2. 2.1 Description of Sample Application Operational Overview of Module Used The bus state controller (BSC) of the SH7670 SH7670 supports an SDRAM interface that is directly connectable to SDRAM units that have 11, 12, or 13 bits of row address, 8, 9, or 10 bits of column address, 4 or fewer banks, and in which the A10 pin is used to set pre-charge mode in read and write command cycles. Burst reading/single writing (burst length 1) and burst reading/burst writing (burst length 1) are supported as SDRAM operating modes. Table 1 provides the specifications of SDRAM used in this sample application. Table 1 Specifications of SDRAM Used in This Sample Application Item Clock frequency Capacity Configuration CAS latency Refresh cycle Burst length Row address Column address Pre-charge Specification Up to 133 MHz 256 Mbits (32 MB) × 2 4 banks × 4 Mwords × 16 bits 2 or 3 (programmable) 8192 refresh cycles per 64 ms 1, 2, 4 or 8 full pages (programmable) A12 to A0 A8 to A0 Auto pre-charge/all bank pre-charge controlled via A10 Figure 1 shows a memory map. SDRAM can be connected to the CS3 space of the SH7670 SH7670. The value of bit A29 in internal addresses can control enabling and disabling of the cache. SH7670 SH7670 internal address H'0C00 0000 Memory space CS3 space: 64 MB (Cache enabled area) H'0C00 0000 SDRAM: 64 MB (256 Mbits × 2) H'0FFF FFFF H'0FFF FFFF H'2C00 0000 CS3 space: 64 MB (Cache disabled area) H'2FFF FFFF Figure 1 Memory Map in Relation to SDRAM REJ06B0782-0100/Rev.1.00 November 2008 Page 3 of 18 SH7670 SH7670 Group Example of BSC SDRAM Interface Connection (32-Bit Data Bus) Figure 2 shows an example of circuitry for SDRAM connection. Table 2 gives a list of the address-multiplexing output pins in the case of 256-Mbit SDRAM. SDRAM 256 Mbits (16-bit data bus) 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V SH7670 SH7670 2 A16-A15 A16-A15 13 A14-A2 A14-A2 BA1-BA0 A12-A0 A12-A0 CS3 CS CKIO CLK CKE CKE WE RD/WR RASL RAS CAS UDQM CASL WE3/DQMUU/ICIOWR WE2/DQMUL/ICIORD LDQM 16 D31-D16 D31-D16 GND 3.3 V 3.3 V WE1/DQMLU/WE DQ15-DQ0 DQ15-DQ0 SDRAM 256 Mbits (16-bit data bus) BA1-BA0 WE0/DQMLL A12-A0 A12-A0 D15-D0 D15-D0 CS CLK CKE WE RAS CAS UDQM LDQM 16 DQ15-DQ0 DQ15-DQ0 Figure 2 Example of Circuitry for SDRAM Connection (256-Mbit SDRAM × 2 and 32-Bit Bus) Note: Handling of control signal pins with external pull-up or pull-down resistors In general, the criterion for whether control pins should be pulled up or down is stability of operation. We thus recommend that the CS, RAS, CAS, WE, DQMU, and DQML pins be pulled up (set to the high level) by external resistors. The CKE pin is pulled down (set to the low level) by an external resistor for a reason other than that stated above. In this case, the intention is to continue the self-refresh state so that data in the SDRAM are protected even after signals from the MCU have stopped. REJ06B0782-0100/Rev.1.00 November 2008 Page 4 of 18 SH7670 SH7670 Group Example of BSC SDRAM Interface Connection (32-Bit Data Bus) Table 2 Connections between SH7670 SH7670 Pin Functions and SDRAM SH7670 SH7670 Pin Row Address Column Address (32 bits) (13 bits) (9 bits) SDRAM Pin Function A17 A26 A17 Not in use A16 A25*2 A25*2 A14 (BA1) Specifies bank A15 A24*2 A24*2 A13 (BA0) A14 A23 A14 A12 Address A13 A22 A13 A11 A12 A21 L/H*1 A10/AP A10/AP Specifies address/pre-charge A11 A20 A11 A9 Address A10 A19 A10 A8 A9 A18 A9 A7 A8 A17 A8 A6 A7 A16 A7 A5 A6 A15 A6 A4 A5 A14 A5 A3 A4 A13 A4 A2 A3 A12 A3 A1 A2 A11 A2 A0 A1 A10 A1 Not in use A0 A9 A0 Notes: 1. The L/H bit is used in command specification; it is fixed at low or high according to the access mode. 2. Bank address specification REJ06B0782-0100/Rev.1.00 November 2008 Page 5 of 18 SH7670 SH7670 Group Example of BSC SDRAM Interface Connection (32-Bit Data Bus) 2.2 2.2.1 Procedure for Setting Module Used Example of the Initialization Procedure for SDRAM Figure 3 gives an example of the initialization procedure to place SDRAM in the CS3 space. START Idle period elapsed? No · SDRAM requires a certain idle period after power is supplied. Yes Set pin function controller (PFC). Set CS3 bus control register (CS3BCR). Set CS3 space wait control register (CS3WCR). Set SDRAM control register (SDCR). Set refresh timer control/ status register (RTCSR). Set refresh timer counter (RTCNT). Set refresh time constant register (RTCOR). Write to the SDRAM mode register. END · Since these registers are enabled by default, no further settings are required. [Function] Selecting multiplexed pin functions · Setting of CS3BCR [Functions] Setting for insertion of an idle period between cycles Setting the memory type to SDRAM Setting for endian Setting for data bus width · Setting of CS3WC [Functions] Setting for the number of cycles to wait for precharging to be completed Setting for the number of cycles to be inserted between the ACTV command and READ(A)/WRIT(A) commands Setting for CAS latency of area 3 Setting for the number of cycles to wait for precharging to be activated Setting for the number of idle cycles to be inserted between cancellation of the REF command/self-refresh and ACTV/REF/MRS commands · Setting of SDCR [Functions] Setting for deep power-down mode corresponding to low-power SDRAM Setting for implementing refresh operation for SDRAM Setting for power-down mode Setting for auto-precharge mode Setting for row address of area 3 Setting for column address of area 3 · Setting of RTCSR*1 [Functions] Settings to enable or disable interrupts from timer counting Selecting the clock frequency to drive counting up by the refresh timer counter (RTCNT) Setting for the number of consecutive refresh operations · Setting of RTCNT*1 [Function] Initializing the refresh timer counter · Setting of RTCOR*1 [Function] Setting for interval between refresh requests for SDRAM · Writing to the SDRAM mode register*2 [Functions] Setting for burst length Setting for wrap type Setting for CAS latency Notes *: 1. With write protection (disabled by writing 0xa55a to the 16 higher-order bits) 2. Values of settings are specified by address values. Figure 3 Example of the Procedure for Initial Settings to Place SDRAM in the CS3 Space REJ06B0782-0100/Rev.1.00 November 2008 Page 6 of 18 SH7670 SH7670 Group Example of BSC SDRAM Interface Connection (32-Bit Data Bus) 2.2.2 Example of the Switching Procedure for AC Characteristics To connect SDRAM to the SH7670 SH7670 and use it clock mode 0 or 1, the AC characteristics must be switched. To use the AC characteristics switching function, set the AC characteristics switching register (ACSWR) and AC characteristics switching key register (ACKEYR). In clock mode 2 or 3, set nothing to keep the initial value. Figure 4 gives an example of the procedure for setting the AC characteristics switching register (ACSWR). These settings must be made from the on-chip RAM. For a sample program that handles AC characteristics switching, please refer to the SH7670 SH7670 Group Application Note: Example of Initialization (REJ06B0799 REJ06B0799). START · Setting of ACKEYR (AC characteristics switching key register) [Function] Enabling setting of ACSWR (The data value has no effect.) Write to ACKEYR in bytes. Write to ACKEYR in bytes. · Setting of ACSWR The ACOSW (AC characteristics switching) bits are set. [Function] Switching AC characteristics (Extension of the delay time is selected.) · Whether the value written to ACOSW has been written correctly is confirmed. Write to ACSWR in longwords. Read ACSWR. Written value = read value? No Yes END Figure 4 Example of the Procedure for Setting the AC Characteristics Switching Register (ACSWR) REJ06B0782-0100/Rev.1.00 November 2008 Page 7 of 18 SH7670 SH7670 Group Example of BSC SDRAM Interface Connection (32-Bit Data Bus) 2.2.3 Power-On Sequence To perform SDRAM initialization, registers of the bus state controller must first be set, followed by a write to the SDRAM mode register. Burst length, wrap type, CAS latency, etc. can be set in the mode register. SDRAM requires a certain idle period after power is supplied, and this period differs with the SDRAM specifications. Please confirm the specifications of the SDRAM to be used, and make settings after the idle period has elapsed. Settings are written to the SDRAM mode register by writing a word (16 bits) with any value to the addresses shown in table 3. Select the address for access in accord with the settings. Table 3 Addresses for Access to Write Values to the SDRAM Mode Register Data Bus Width CAS Latency Burst Read/Single Write (Burst Length 1) Burst Read/Burst Write (Burst Length 1) Access Address External Address Pin Access Address External Address Pin 16 bits 2 3 2 3 H'FFFC 5440 H'FFFC 5460 H'FFFC 5880 H'FFFC 58C0 H'0000 0440 H'0000 0460 H'0000 0880 H'0000 08C0 H'FFFC 5040 H'FFFC 5060 H'FFFC 5080 H'FFFC 50C0 H'0000 0040 H'0000 0060 H'0000 0080 H'0000 00C0 32 bits Writing a word to an access address writes the corresponding settings to the SDRAM mode register. Writing is executed by the following commands being issued in sequence. Figure 5 shows an example of timing for writing to the SDRAM mode register. 1. All bank pre-charge command (PALL) Idle cycles (Tpw) as specified by the WTRP[1:0] bits in CS3WCR are inserted between the PALL and the first REF. 2. Auto-refresh command (REF, eight times) The REF command is issued and is followed by the number of idle cycles (Trc) specified by the WTRC[1:0] bits in CS3WCR. This is repeated eight times. 3. Mode-register setting command (MRS) The mode-register setting command is issued in combination with CS3, RAS, CAS, and RD/WR. The combination of levels on the external address pins determines the value of the setting written to the SDRAM. Furthermore, the burst length is always set to 1 for the SH7670 SH7670. Accordingly, burst operations to transfer more data than the width of the data bus, for example to transfer 16 bytes of data, are realized by issuing consecutive commands. This is efficient because unnecessary bus cycles are not generated even when the access size is small. Selection of burst read/single write (burst length 1) or burst read/burst write (burst length 1) as given in table 3 does not affect the operation of the SH7670 SH7670. REJ06B0782-0100/Rev.1.00 November 2008 Page 8 of 18 SH7670 SH7670 Group Example of BSC SDRAM Interface Connection (32-Bit Data Bus) Tp Tpw Trr Trc Trr Trc Tmw Tnop DESL MRS DESL CKIO Issues REF command 8 times SDRAM command PALL DESL REF DESL REF A0 to A25 A12* CS3 RASL CASL RD/WR DQMxx (High) D0 to D31 Hi-Z PALL: All banks pre-charge command (idle cycles (Tpw) as set by the WTRP bits in CS3WCR are inserted.) REF: Auto-refresh command (idle cycles (Trc) as set by the WTRC bits in CS3WCR are inserted.) MRS: Mode register write command DESL: Deselect command Note *: This address pin is connected to the A10 pin of the SDRAM. Figure 5 Example of Timing for Writing to the SDRAM Mode Register REJ06B0782-0100/Rev.1.00 November 2008 Page 9 of 18 SH7670 SH7670 Group Example of BSC SDRAM Interface Connection (32-Bit Data Bus) 2.3 Operation of the Sample Program SDRAM read and write operations for sample program are described as follows: 1. Read operation Figure 6 shows an example of SDRAM single-read timing in operation with the bus clock running at 66.67 MHz. The operations below are performed on successive cycles of the SH7670 SH7670. Tr Trw1, Trw2 Tcl Tcw Td1 Tde Tap : An ACTV command is issued, activating the relevant rows and banks. : Wait cycles are inserted between the ACTV command and READ(A)/WRIT(A) commands. The number of wait cycles (two) for insertion is set by the WTRCD bits in CS3WCR. : A READ(A) command is issued; a read command with auto-precharge is issued. : Wait cycles are inserted between the Tcl and Tdl cycles. The wait cycles are equivalent to the number set for the CAS latency ­1; the number of wait cycles (one) for insertion is set by the A3CL bits in CS3WCR. : Read data are retrieved. In the case of burst reading, consecutive READ(A) commands are issued to read the data in sequence. : This is an idle cycle that is necessary for transfer of the read data within this LSI. One cycle must be allowed without fail for both burst-read and single-read operations. : This is a cycle of waiting for completion of auto-precharge. The number of wait cycles (one) for insertion is set by the WTRP bits in CS3WCR. Tr Trw1 Trw2 Tc1 Tcw ACTV DESL DESL READA DESL Td1 Tde Tap DESL DESL DESL CKIO SDRAM command CKE (High) CS3 RAS CAS RD/WR DQMxx A2 to A14 Row address Column address A12 A16, A15 D0 to D31 2 cycles of CAS latency ACTV : Row and bank activating command READA : Read command with auto pre-charge DESL : Deselect command Figure 6 Example of SDRAM Single-Read Timing (Auto-Precharge) REJ06B0782-0100/Rev.1.00 November 2008 Page 10 of 18 SH7670 SH7670 Group Example of BSC SDRAM Interface Connection (32-Bit Data Bus) 2. Write operation Figure 7 shows an example of SDRAM single-write timing in operation with the bus clock running at 66.67 MHz. The operations below are performed on successive cycles of the SH7670 SH7670. Tr Trw1, Trw2 Tcl Trw1, Trw2 Tap : An ACTV command is issued, activating the relevant rows and banks. : Wait cycles are inserted between the ACTV command and READ(A)/WRIT(A) commands. The number of wait cycles (two) for insertion is set by the WTRCD bits in CS3WCR. : A WRIT(A) command is issued; a write command with auto-precharge is issued. In case of burst writing, a WRIT(A) command is consecutively issued. : These are cycles of waiting for activation of auto-precharge. The number of wait cycles (two) for insertion is set by the TRWL bits in CS3WCR. : This is a cycle of waiting for completion of auto-precharge. The number of wait cycles (one) for insertion is set by the WTRP bits in CS3WCR. Tr Trw1 Trw2 Tc1 Trwl1 Trwl2 Tap ACTV DESL DESL WRITA DESL DESL DESL CKIO SDRAM command (High) CKE CS3 RAS CAS RD/WR DQMxx A2 to A14 Row address Column address A12 A16, A15 D0 to D31 ACTV : Row and bank activating command WRITA : Write command with auto pre-cahrge DESL : Deselect command Figure 7 Example of Timing for Single-Writing to SDRAM (Auto Pre-charge) REJ06B0782-0100/Rev.1.00 November 2008 Page 11 of 18 SH7670 SH7670 Group Example of BSC SDRAM Interface Connection (32-Bit Data Bus) 2.4 Sample Settings of Bus State Controller Table 4 provides sample settings of the BSC in operation with the SH7670 SH7670 bus clock running at 66.67 MHz. For details on individual registers, please refer to the section on the bus state controller in the SH7670 SH7670 Group hardware manual (REJ09B0437 REJ09B0437). Table 4 Sample Settings of the BSC Name of Register CS3 space bus control register (CS3BCR) Address H'FFFC 0010 Setting Value H'0000 4600 CS3 space wait control register (CS3WCR) H'FFFC 0034 H'0000 2892 SDRAM control register (SDCR) H'FFFC 004C H'0000 0811 Refresh timer control register/status register (RTCSR) H'FFFC 0050 H'A55A 0010* Refresh time constant register (RTCOR) H'FFFC 0058 H'A55A 0020* Description · IWW[2:0], IWRWD[2:0], IWRWS[2:0], IWRRD[2:0], IWRRS[2:0] = B'000: No idle cycles are inserted. · TYPE[2:0] = B'100: SDRAM · ENDIAN = 0: Arranged in big endian · BSZ[1:0] = B'11: 32-bit data bus width · WTRP[1:0] = B'01: Number of cycles to wait for completion of precharging is 1. · WTRCD[1:0] = B'10: Number of wait cycles inserted between ACTV command and READ(A)/WRIT(A) commands is 2. · A3CL[1:0] = B'01: CAS latency of area 3 is 2 cycles. · TRWL[1:0] = B'10: Number of cycles to wait for activation of precharging is 2. · WTRC[1:0] = B'10: Number of idle cycles inserted between cancellation of REF command/self-refresh and ACTV/REF/MRS commands is 5. · DEEP = 0: Deep power-down mode is not in use. · RFSH = 1: Refresh · RMODE = 0: Auto-refresh · PDOWN = 0: Power-down mode is not in use. · BACTV = 0: Auto pre-charge mode · A3ROW[1:0] = B'10: Row address of area 3 is 13 bits. · A3COL[1:0] = B'01: Column address of area 3 is 9 bits. · CKS[2:0] = B'010: B/16 is selected. · RRC[2:0] = B'000: Refresh count is once. · Interval between refresh requests for SDRAM = H'20 Request interval: 8192 cycles/64 ms = 7.8125 µs/time, 1 cycle: 1/(B (66.67 MHz)/16) = 240 ns, 7.8125 µs/240 ns > 32 = H'20 · Initialization of counter H'FFFC 0054 H'A55A 0000* Refresh timer counter (RTCNT) Note: When writing, set the upper 16 bits to H'A55A to disable write protection. REJ06B0782-0100/Rev.1.00 November 2008 Page 12 of 18 SH7670 SH7670 Group Example of BSC SDRAM Interface Connection (32-Bit Data Bus) 3. 3.1 Listing of Sample Program Sample Program Listing: "bscsdram.c" (1) 1 /*""FILE COMMENT""* 2 * 3 * System Name : SH7670 SH7670 Sample Program 4 * File Name : bscsdram.c 5 * Version : 1.00.00 6 * Contents : SH7670 SH7670 Initial Settings 7 * Model : M3A-HS71 M3A-HS71 8 * CPU : SH7670 SH7670 9 * Compiler : SHC9.1.1.0 10 * OS : None 11 * 12 * Note : 13 * 14 * This sample program is for reference and its 15 * operation is not guaranteed. 16 * Please use this sample for technical reference 17 * in software development. 18 * 19 * The information described here may contain technical inaccuracies or 20 * typographical errors. Renesas Technology Corporation and Renesas Solutions 21 * assume no responsibility for any damage, liability, or other loss rising 22 * from such inaccuracies or errors. 23 * 24 * Copyright (C) 2008 Renesas Technology Corp. All Rights Reserved 25 * AND Renesas Solutions Corp. All Rights Reserved 26 * 27 * History 28 *""FILE COMMENT END""*/ 29 #include "iodefine.h" 30 #include "defs.h" : 2008.03.03 ver.1.00.00 31 32 /* = Macro Name definition = */ 33 34 /* The address when writing in a SDRAM mode register */ 35 #define SDRAM_MODE (*(volatile unsigned short *)(0xfffc5080) 36 37 /* = Prototype Declaration = */ 38 void io_init_sdram(void); 39 REJ06B0782-0100/Rev.1.00 November 2008 Page 13 of 18 SH7670 SH7670 Group Example of BSC SDRAM Interface Connection (32-Bit Data Bus) 3.2 Sample Program Listing: "bscsdram.c" (2) 40 #pragma section ResetPRG 41 /*""FUNC COMMENT""* 42 * ID : 43 * Outline : SDRAM 16 bit bus width connection settings 44 *- 45 * Include : #include "iodefine.h" 46 * : #include "defs.h" 47 *- 48 * Declaration 49 *- 50 * Function 51 *- 52 * Argument 53 *- 54 * Return Value : None 55 *- 56 * Note 57 *""FUNC COMMENT END""*/ 58 void io_init_sdram(void) 59 { : void io_init_sdram(void); : A connection setup to SDRAM of CS3 space. : None : 60 61 /* 200 µs wait */ volatile int j = LOOP_100us*2; 62 63 /* = 200us interval elapsed ? = */ 64 while(j- > 0){ 65 66 /* wait */ } 67 68 /* = CS3BCR settings = */ 69 BSC.CS3BCR.LONG = 0x00004600ul; /* Idle Cycles between Write-read Cycles 70 and Write-write Cycles :2-idle cycles */ 71 /* Memory type :SDRAM */ 72 /* Data Bus Size :32-bit size */ 73 74 75 /* = CS3WCR settings = */ 76 BSC.CS3WCR_SDRAM.LONG = 0x00002892ul; 77 78 79 80 /* Precharge completion wait cycles :1 cycle */ /* Wait cycles between ACTV command and READ(A)/WRITE(A) command :2 cycles */ 81 /* CAS latency for Area 3 :2 cycles */ 82 /* Auto-precharge startup wait cycles 83 84 :2 cycles */ /* Idle cycles from REF command/self-refresh 85 Release to ACTV/REF/MRS command 86 :5 cycles */ 87 REJ06B0782-0100/Rev.1.00 November 2008 Page 14 of 18 SH7670 SH7670 Group Example of BSC SDRAM Interface Connection (32-Bit Data Bus) 3.3 Sample Program: Listing of "bscsdram.c" (3) 88 /* = SDCR settings = */ 89 BSC.SDCR.LONG = 0x00000811ul; /* 90 Refresh Control :Refresh start 91 RMODE :Auto-refresh is performed 92 BACTV :Auto-precharge mode 93 Row address for Area3 :13 bits 94 Column Address for Area3 :9 bits 95 */ 96 97 /* = RTCOR settings = */ 98 BSC.RTCOR.LONG = 0xa55a0020ul; /* 99 7.8 µs /240 ns 100 >= 32(0x20)cycles per refresh 101 */ 102 103 /* = RTCSR settings = */ 104 BSC.RTCSR.LONG = 0xa55a0010ul; 105 /* 106 Initialization sequence start 107 Clock select B-phy/16 = 240 ns 108 Refresh count :Once 109 */ 110 /* = Written in SDRAM Mode Register = */ 111 SDRAM_MODE = 0; /* 112 SDRAM mode register setting(CS3 area) 113 dummy write 114 burst read / burst write (burst length 1) 115 */ 116 } 117 /* End of File */ REJ06B0782-0100/Rev.1.00 November 2008 Page 15 of 18 SH7670 SH7670 Group Example of BSC SDRAM Interface Connection (32-Bit Data Bus) 4. Documents for Reference · Software manual SH-2A/SH2A-FPU Software Manual (REJ09B0051 REJ09B0051) The most up-to-data version of this document is available on the Renesas Technology Website. · Hardware manual SH7670 SH7670 Group Hardware Manual (REJ09B0437 REJ09B0437) The most up-to-data version of this document is available on the Renesas Technology Website. REJ06B0782-0100/Rev.1.00 November 2008 Page 16 of 18 SH7670 SH7670 Group Example of BSC SDRAM Interface Connection (32-Bit Data Bus) Website and Support Renesas Technology Website http://www.renesas.com/ Inquiries http://www.renesas.com/inquiry csc@renesas.com Revision Record Rev. 1.00 Date Nov.19.08 Description Page Summary - First edition issued All trademarks and registered trademarks are the property of their respective owners. REJ06B0782-0100/Rev.1.00 November 2008 Page 17 of 18 SH7670 SH7670 Group Example of BSC SDRAM Interface Connection (32-Bit Data Bus) Notes regarding these materials 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples. 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