SG3524 DIP16 SG3524N SG3524P SG2524

® REGULATING PULSE WIDTH MODULATORS COMPLETE PWM POWER CONTROL CIRCUITRY UNCOMMITTED OUTPUTS FOR SINGLEENDED OR PUSH PULL

SG3524 SG3524 ® REGULATING PULSE WIDTH MODULATORS COMPLETE PWM POWER CONTROL CIRCUITRY UNCOMMITTED OUTPUTS FOR SINGLEENDED OR PUSH PULL APPLICATIONS LOW STANDBY CURRENT 8mA TYPICAL OPERATION UP TO 300KHz 1% MAXIMUM TEMPERATURE VARIATION OF REFERENCE VOLTAGE DESCRIPTION The SG3524 SG3524 incorporates on a single monolithic chip all the function required for the construction of regulating power suppies inverters or switching regulators. They can also be used as the control element for high power-output applications. The SG3524 SG3524 family was designed for switching regulators of either polarity, transformer-coupled dcto-dc converters, transformerless voltage doublers and polarity converter applications employing fixed-frequency, pulse-width modulation techniques. The dual alternating outputs allows either single-ended or push-pull applications. DIP16 DIP16 SO16 ORDERING NUMBERS: SG3524N SG3524N (DIP16 DIP16) SG3524P SG3524P (SO16) Each device includes an on-ship reference, error amplifier, programmable oscillator, pulse-steering flip flop, two uncommitted output transistors, a high-gain comparator, and current-limiting and shut-down circuitry. BLOCK DIAGRAM July 2000 1/9 This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice. SG3524 SG3524 ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Unit VIN Supply Voltage 40 V IC Collector Output Current 100 mA IR Reference Output Current 50 mA IT Current Through CT Terminal 5 mA Ptot Total Power Dissipation at Tamb = 70°C Tstg Storage Temperature Range Top 1000 mW 65 to 150 Operating Ambient Temperature Range: °C 0 to 70 °C PIN CONNECTION (Top view) THERMAL DATA Symbol Rth j-amb Rth j-alumina Parameter Thermal Resistance Junction-ambient Thermal Resistance Junction-alumina DIP16 DIP16 (*) Max. Max. SO16 Unit 80 50 °C/W °C/W (*) Thermal resistance junction-alumina with the device soldered on the middle of an alumina supporting substrate measuring 15 x 20mm; 0.65mm thickness with infinite heatsink. 2/9 SG3524 SG3524 ELECTRICAL CHARACTERISTICS (unless otherwise stated, these specifications apply for Tj = 0 to 70°C, VIN = 20V, and f = 20KHz). Symbol Parameter Test Condition Min. Typ. Max. Unit REFERENCE SECTION VREF Output Voltage VREF Line Regulation VREF V 30 mV Load Regulation IL = 0 to 20mA 20 50 mV f = 120Hz, Tj = 25°C 66 Short Circuit Current Limit VREF 5.4 10 Ripple Rejection VREF/T 5 VIN = 8 to 40V 4.6 VREF = 0, Tj = 25°C 100 Temperature Stability Over Operating Temperature range 0.3 Long Term Stability Tj = 125°C, t = 1000Hrs 20 mV 300 KHz dB mA 1 % OSCILLATOR SECTION CT = 0.001µF, RT = 2K R T and CT Constant Voltage Stability f/T Maximum Frequency Initial Accuracy fMAX VIN = 8 to 40V, Tj = 25°C 5 % 1 % 2 % Temperature Stability Over Operating Temperature Range Output Amplitude Pin 3, Tj = 25°C 3.5 V Output Pulse Width C T = 0.01µF, Tj = 25°C 0.5 µs ERROR AMPLIFIER SECTION VOS Input Offset Voltage VCM = 2.5V Input Bias Current GV Open Loop Voltage Gain CMV Common Mode Voltage Tj = 25°C CMR Common Mode Rejection 2 Tj = 25°C 60 B Small Signal Bandwidth Output Voltage Tj = 25°C mV 10 µA 80 1.8 dB 3.4 70 AV = 0dB, Tj = 25°C VO 10 2 Ib 3 0.5 V dB MHz 3.8 V 45 % COMPARATOR SECTION Duty-cycle % Each Output On VIT Input Threshold Zero Duty-cycle Ib 0 Input Bias Current 1 Maximum Duty-cycle V 3.5 V 1 µA CURRENT LIMITING SECTION Sense Voltage Pin 9 = 2V with Error Amp. Set for Max. Out. Tj = 25°C 180 Sense Voltage T.C. CMV 200 220 0.2 Common Mode Voltage 1 mV mV/°C 1 OUTPUT SECTION(each output) Collector-emitter Voltage 40 V Collector Leackage Curr. VCE = 40V 0.1 50 µA Saturation Voltage IC = 50mA 1 2 V Emitter Output Voltage VIN = 20V tr Rise Time tf Iq (*) 17 18 V R C = 2K, Tj = 25°C 0.2 µs Fall Time R C = 2K, Tj = 25°C 0.1 Total Standby Current VIN = 40V 8 µs 10 mA (*) Excluding oscillator charging current, error and current limit dividers, and with outputs open. 3/9 SG3524 SG3524 Figure 1: Open-loop Voltage Amplification of Error Amplifier vs. Frequency Figure 2: Oscillator Frequency vs. Timing Components. Figure 3: Output Dead Time vs. Timing Capacitance Value. Figure 4: Output Saturation Voltage vs. load Current. Figure 5: Open Loop Test Circuit. 4/9 SG3524 SG3524 PRINCIPLES OF OPERATION The SG3524 SG3524 is a fixed frequency pulse-withmodulation voltage regulator control circuit. The regulator operates at a frequency that is programmed by one timing resistor (RT) and one timing capacitor (CT). RT established a constant charging current for CT. This results in a linear voltage ramp at CT, which is fed to the comparator providing linear control of the output pulse width by the error amplifier. the SG3524 SG3524 contains, an on-board 5V regulator that serves as a reference as well as powering the SG3524 SG3524's internal control circuitry and is also useful in supplying external support functions. This reference voltage is lowered externally by a resistor divider to provide a reference within the common mode range the error amplifier or an external reference may be used. The power supply output is sensed by a second resistor divider network to generale a feedback signal to error amplifier. The amplifier output voltage is then compared to the linear voltage ramp at CT. The resulting modulated pulse out of the high-gain comparator is then steered to the appropriate output pass transistors (QA or QB) by the pulse-steering flip-flop, which is synchronously toggled by the oscillator output. The oscillator output pulse also serves as a blanking pulse to assure both output are never on simultaneously during the transition times. The width of the blanking pulse is controlled by the value of CT. The outputs may be applied in a push-pull configuration in which their frequency is half that of the base oscillator, or paralleled for single-ended applications in which the frequency is equal to that of the oscillator. The output of the error amplifier shares a common input to the comparator with the current limiting at shutdown circuitry and can be overridden by signals from either of these inputs. This common point is also available externally and may be employed to control the gain of, or to compensate, the error amplifier, or to provide additional control to the regulator. RECOMMENDED OPERATING CONDITIONS Supply voltage VIN 8 to 40V Reference Output Current 0 to 20mA Current trough CT Terminal - 0.03 to -2mA Timing Resistor, RT 1.8 to 100K Timing Capacitor, CT 0.001 to 0.1µF TYPICAL APPLICATIONS DATA OSCILLATOR The oscillator controls the frequency of the SG3524 SG3524 and is programmed by RT and CT ac- cording to the approximate formula: f= 1.18 RT CT where: RT is in K CT is in µF f is in KHz Pratical values of CT fall between 0.001 and 0.1µF. Pratical values of RT fall between 1.8 and 100K. This results in a frequency range typically from 120Hz to to 500KHz. BLANKING The output pulse of oscillator is used as a blanking pulse at the output. This pulse width is controlled by the value of CT.If small values of CT are required for frequency control, the oscillator output pulse width may still be increased by applying a shunt capacitance of up to 100pF from pin 3 to ground. If still greater dead-time is required, it should be accomplished by limiting the maximum duty cycle by clamping the output of the error amplifier. This can easily be done with the circuit below: Figure 6. SYNCRONOUS OPERATION When an external clock is desired, a clock pulse of approximately 3V can be applied directly to the oscillator output terminal. The impedance to ground at this point is approximately 2K. In this configuration RT CT must be selected for a clock period slightly greater than that the external clock. If two more SG2524 SG2524 regulators are to be operated synchronously, all oscillator output terminals should be tied together, all CT terminals connected to a single timing capacitor, and timing resistor connected to a single RT terminal. The other RT terminals can be left open or shorted to VREF. Minimum lead lengths should be used between the CT terminals. 5/9 SG3524 SG3524 Figure 7: Flyback Converter Circuit. Figure 8: PUSH-PULL Transformer-coupled circuit. 6/9 SG3524 SG3524 mm DIM. MIN. a1 0.77 MAX. 0.51 B TYP. inch MIN. TYP. MAX. OUTLINE AND MECHANICAL DATA 0.020 1.65 0.030 0.065 b 0.5 0.020 b1 0.25 0.010 D 20 0.787 E 8.5 0.335 e 2.54 0.100 e3 17.78 0.700 F 7.1 0.280 I 5.1 0.201 L Z 3.3 0.130 1.27 DIP16 DIP16 0.050 7/9 SG3524 SG3524 mm DIM. MIN. TYP. A a1 inch MAX. MIN. TYP. 1.75 0.1 0.25 a2 MAX. OUTLINE AND MECHANICAL DATA 0.069 0.004 0.009 1.6 0.063 b 0.35 0.46 0.014 0.018 b1 0.19 0.25 0.007 0.010 C 0.5 c1 0.020 45° (typ.) D (1) 9.8 10 0.386 0.394 E 5.8 6.2 0.228 0.244 e 1.27 0.050 e3 8.89 0.350 F (1) 3.8 4 0.150 0.157 G 4.6 5.3 0.181 0.209 L 0.4 1.27 0.016 0.050 M S 0.62 0.024 SO16 Narrow 8°(max.) (1) D and F do not include mold flash or protrusions. Mold flash or potrusions shall not exceed 0.15mm (.006inch). 8/9 SG3524 SG3524 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. 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