SED1770/71 SED1770 SED1771 SED1743F SED1743 SEG159 SED1771DOA SEG157 SEG158 - Datasheet Archive

 

CMOS LCD DRIVER s DESCRIPTION The SED1770 and the SED1771 are 160-bit output LCD segment (column) analog drivers for driving

 

SED1770/71 SED1770/71 CMOS LCD DRIVER s DESCRIPTION The SED1770 SED1770 and the SED1771 SED1771 are 160-bit output LCD segment (column) analog drivers for driving highcapacity active matrix LCD MIM- or TFT-type panels. These devices take 3-bit analog input (VA, VB, VC) which are (R, G, B) signals, and can support duty cycle higher than 1/100 (up to 1/500). Also, the LSI features a wide range of LCD voltages from 5 to 17V. The device uses a high-speed daisy-chain enable system which decreases power consumption and eliminates the need for separate enable signals for each driver. The SED1770/71 SED1770/71 is used in conjunction with the SED1743F SED1743F common drivers to support a large-capacity TFT/ MIM active matrix LCD panel. s FEATURES · Low-power, high-speed CMOS technology · LCD driver output . 160 (SED1770 SED1770) 162 (SED1771 SED1771) High-speed data transfer . 10MHz · daisy-chain · Support high-speed consumptiondata transfer which reduces power · Takes 3-bit video inputs (VA, VB, VC) · Built-in high-speed sampling circuitry · Selectable output shift direction · Low output resistance · Wide range of LCD voltage . 5 to 17V · Supply voltage . 4.5 to 5.5V TAB (2-sided) · Package . Al pad (D ) OA s SYSTEM BLOCK DIAGRAM VA, VB, VC XSCL LCD CONTR LP, FR YSCL YD SED1770/71 SED1770/71 160 SED1743 SED1743 160 SED1743 SED1743 160 160 SED1743 SED1743 SED1770/71 SED1770/71 160 320 SEG × 480 COM DUTY: 1/480 673 SED1770/71 SED1770/71 s BLOCK DIAGRAM VDDH VDD VSS OE Vd2 Vd1 SEG0 Buffer Ability Adjust/Select Circuit SEG1 Liquid Crystal Driver Buffer Line Memory­2 Output Transfer Buffer LP VCOM Line Memory-1 VA ~ VC Sampling Circuit SHL EIO1 EIO2 2 Way Shift Register Enable Control Circuit XSCL TEST1 TEST2 674 SED1770/71 SED1770/71 s FUNCTIONS OF BLOCKS · Enable control circuit If the enable signal is in the disable status, the internal clock signal is fixed to "L" and placed in the POWER SAVE mode. When using multiple segment drivers, the EIO terminals of the drivers should be cascade-connected while the EIO terminal of the front driver is connected to VSS. In this case, the sampling of the front driver starts from XSCL's initial rising. As the enable control circuit automatically detects that sampling of data of the portion of 160 outputs has been finished thus automatically transferring the enable signal, the control signal by the control LSI is not necessary. The EIO output is reset by LP input. · Shift register The shift register shifts the sampling signal by shift clock input. And it selects the shift direction by SHL input. · Sampling circuit The sampling circuit samples analog input signals sequentially by means of the sampling signals from the shift register. At this time, input/output are corresponded as follows: VA with SEG0, 3, 6 - 159; VB with SEG1, 4, 7 -157; and VC with SEG2, 5, 8 - 158. · Line memory - 1 The line memory-1 stores the analog data sampled by the sampling circuit. · Output transfer buffer With the rising of LP, the output transfer buffer transfers the data of line memory-1 to line memory-2 and at the same time switches over to another liquid crystal drive output. When LP = H, make sure that XSCL = L. While sampling the data, make sure that LP = L. The ability of this buffer can be adjusted by Vd1. · Line memory - 2 The line memory-2 holds the voltage of the liquid crystal drive output for the period until the next switching. · Liquid crystal drive buffer The crystal drive buffer outputs the liquid crystal drive voltage. The ability of this buffer can be adjusted by Vd2 and switched over by OE. · Buffer ability adjustment and switching circuit This circuit performs two types of buffer ability adjustment and switching. The buffer abilities of both Vd1 and Vd2 reach their lowest level when they are equivalent to VDDH; the respective abilities can be increased by lowering the electric potential, thus enabling them to cope with various liquid crystal panels. The ability (output current) of the liquid crystal drive buffer is switched over by the OE to be used. With the time of writing data in the panel set at OE = "H", the large current is used to drive the buffer; after writing the data, the small current is used to drive the buffer at OE = "L". This not only improves the data write ability but also prevents the leakage of the hold time, thus making it possible to save power. 675 SED1770/71 SED1770/71 s PIN DESCRIPTION Terminal Name EIO1 EIO2 I/O Power Function Number of Terminals Shift register data input/output; I/O VDD Connected to the lower-stage EIO in cascade connection; Changes at XSCL's rising edge XSCL I LP I OE I ~ 2 VSS Clock signal input; 1 1 1 1 Display data latch signal input; switches the output data at rising edge. Shift register operation at rising and falling edges 2 Liquid crystal drive buffer ability switching signal input: H: Large current drive L: Small current drive Shift direction select signal input of shift register SHL TEST1 I I TEST2 EIO1 EIO2 SEG Output H Input Output 01-> 1 -> 2 - -> 158 -> 159 L SHL Output Input 159 -> 158 -> - -> 2 -> 1 -> 0 Test input: Normally L. Pulldown is not built in. Buffer ability adjustment input: Vd1 Vd2 The buffer ability for output transfer and that for liquid crystal drive I can be varied by the voltage applied to the terminal. Vd1: Output transfer buffer ability adjustment VDDH ~ 2 VSS Vd2: Liquid crystal drive buffer ability adjustment VA VB I VC Analog signal input: 3 160 1 Power supply for high voltage LCD drive circuit. - 2 Power supply for logic circuit. - 1 - 3 Inputs image signals (R, G, and B). Liquid crystal drive segment output: SEG0 ~ Outputs the level, based on the analog signal input O SEG159 SEG159* (VA, VB and VC) data as a sample holder. The input/output are corresponded as VA ->SEG0, 3, 6., VB -> SEG1, 4, 7., VC -> SEG2, 5, 8 . Sample hold reference voltage input; VCOM I VDDH P VDD P Reference power of the sample hold circuit; To input the central electric potential of the analog signal input (VA, VB, VC) is the standard. VSS P LSI's common GND: Shall be externally connected among VSS terminals. (*) In the case of SED1771DOA SED1771DOA, this is up to 162 outputs and SEG 162, and the number of terminals increases by two. 676 Total: 183 (NC 3) SED1770/71 SED1770/71 s ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings · (VSS=0V) Parameter Symbol Rating Unit Supply voltage (1) VDD ­0.3 to +7.0 V Supply voltage (2) V VDDH ­0.3 to +25.0 Input voltage *1 VID ­0.3 to VDD+0.3 V Input voltage *2 VIA ­0.3 to VDDH+0.3 V Storage temperature Tstg ­65 to +150 °C Operating temperature Topr ­20 to +75 °C Notes: 1. Applies to EIO1, EIO2, XSCL, LP, OE, SHL, TEST1, and TEST2. 2. Applies to VA, VB, VC, Vd1, Vd2, and VCOM. · DC Characteristics Parameter (VSS=0V, VDD=5V±10%, VDDH=15V, and Ta= ­20 to +75°C unless otherwise noted) Symbol Condition Applicable Rating Min Typ Max 4.5 - 5.5 V Supply voltage (1) VDD VDD Supply voltage (2) VDDH VDDH VDD - 17.0 V 0.8·VDD - VDD V VSS - 0.2·VDD V - - 8.0 pF - 2.0 µA - VDD V - 0.4 V - 15.0 pF µA "H" input voltage VIH "L" input voltage VIL Input terminal capacity CID Ta = 25° Input leak current ILID 0 < VI < VDD - "H" output voltage VOH IOH = ­0.4mA VDD­0.4 "L" output voltage VOL IOL = 0.4mA VSS CI/O Ta = 25°C - 0 < VI < VDD Input/output terminal capacity *1 *2 EIO1 EIO2 Input/output leak current ILI/O Analog input voltage Vvideo Analog input capacity CIA VC dVO SEG 0 Between-output voltage deviation - VA, VB, VSS+1.5 ~ - - 15.0 - VDDH­1.5 V - 80 pF MAX ­ MIN = 100 mV Gv "1" output current IOH *3 "0" output current IOL *4 Current consumption (1) IDD *5 - Current consumption (2) IDDH *5 - SEG 161 EIO1, EIO2, XSCL, LP, OE, SHL, TEST1, TEST2 XSCL, LP, OE, SHL, TEST1, TEST2 Vd2 = 12V, Vvideo = 13V, OE = H Vd2 = 12V, Vvideo=2V, OE=H fXSCL = 10MHz, 1H = 63.5µs, Vvideo=+2~+13V, TOE (OE=H) = 10µs, without load 677 95 - 105 % - 0.1 - mA - Input/output gain Notes: 1. 2. 3. 4. 5. Unit Signal 0.1 - mA - - 5 mA - - 15 mA SED1770/71 SED1770/71 · AC Characteristics VSS = 0V, VDD = 5V±10%, VDDH = 15V, and Ta = ­20 to +75°C unless otherwise noted. ° Input Timing Characteristics tWLH 90% LP 10% tLD tC tLH XSCL tSUE tWCH tWCL EIO Parameter Symbol Condition Rating Unit Min Typ Max tc 100 - - ns XSCL "H" pulse width tWCH 40 - - ns XSCL "L" pulse width tWCL 40 - - ns XSCL-to-LP rise time tLD 40 - - ns 2.5 - - µs tLH 1 - - µs tSUE 50 - - ns XSCL cycle LP pulse width LP-to-XSCL time EIO setup time tWLH *1 Notes: 1. Time of XSCL=L and LP=H. 678 SED1770/71 SED1770/71 ° Output Timing Characteristics LP XSCL tDCL tER EIO 90% 10% tLSD 90% SEGout 10% Parameter Symbol EIO output delay time tDCL EIO output reset time tER LP-to-SEGout delay time Condition tLSD CL = 15pF Rating Max Unit Min Typ - - 40 ns - - 12.0 ns Variable by Vdl and Vd2 *1 Notes: 1. Vd1 = Vd2 = 12V, Vvideo = 2~13V, load capacity = 100pF, OE = "H". 679 - - 15 µs SED1770/71 SED1770/71 · Signal Timing Example (with specifications of SHL = H, 160 outputs, 1:1 correspondence) XSCL EIO1 (in) EIO2 (out) VA SEG0 SEG3 SEG1 VB SEG4 SEG2 VC SEG159 SEG159 SEG157 SEG157 SEG158 SEG158 Sampling is started from the rising edge of the next XSCL after EIO1 has fallen. 1H OE LP EIO Sa VCS SEGout Idr Sa : Analog switch input of the sampling circuit VCS : Electric potential of the sampling capacitor Idr : Size of the drive current 680 SED1770/71 SED1770/71 s ALUMINUM MASTER SLICE OPTIONS On this LSI, the following switchings are available by the aluminum master slice options. · Switching of number of output pins (1) 160 outputs : Outputs EIO at the time of SEG158 SEG158 sampling. At this time, the SEG160 SEG160 and 161 terminals are placed in the NC status. (2) 162 outputs : Outputs EIO at the time of SEG160 SEG160 sampling. Note: This applies if SHL = H. If SHL = L, the first output becomes SEG159 SEG159 with (1), and SEG161 SEG161 with (2). · Correspondence between the shift register and the sampling analog switch (1) Shift registers and analog switches shall be corresponded at the ratio of 1:1. (2) One shift register stage shall be connected with three analog switches; and the shift register shall operate for every 3 stages. (1) 1 : 1 Correspondence Shift Register 3n 3n+1 3n+2 (2) 1 : 3 Correspondence 3(n+1) Shift Register VA VC Analog Switch Analog Switch 3n 3n+1 3n+2 3(n+1) 3n SEG Output 3n+1 3n+2 SEG Output [n = 0 ~53] · 3(n+1) VB VC Skip VA VB 3n Correspondence with product names SED1770DOA SED1770DOA: Selects 160 outputs for 1) and 1:1 correspondence for 1) SED1771DOA SED1771DOA: Selects 162 outputs for 1) and 1:3 correspondence for 2) 681 3(n+1) SED1770/71 SED1770/71 s PAD LAYOUT D177 * DOA 1 Y 185 X (0,0) Die size: Pad pitch: X Y 11.27mm × 3.79mm 0.12mm (min) * Metallic bump specifications Die thickness: Bump Size 0.25mm ± 0.025mm X Y PAD No. Bump size A 350µm × 150µm ± 20µm 23, 24, 28, 29, 30, 31 Bump size B 200µm × 150µm ± 20µm 15, 16, 17, 18, 19, 20, 21, 22, 25, 26, 27, Bump size C 95µm × 150µm ± 20µm Other than above 32, 33, 34, 35, 36, 37 (The X in X and Y of the bump size shall be the direction parallel to the scribe line.) 682 SED1770/71 SED1770/71 Unit = µm s PAD COORDINATES Pad Number Name 1 SEG148 SEG148 2 SEG149 SEG149 3 SEG150 SEG150 4 SEG151 SEG151 5 SEG152 SEG152 6 SEG153 SEG153 7 SEG154 SEG154 8 SEG155 SEG155 9 SEG156 SEG156 10 SEG157 SEG157 11 SEG158 SEG158 12 SEG159 SEG159 13 SEG160 SEG160* 14 SEG161 SEG161* 15 TEST1 16 OE 17 LP 18 XSCL 19 SHL 20 EIO2 21 EIO1 22 TEST2 23 VSS 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 VDDH Vd1 Vd2 VCOM VSS VDD VDDH VSS VA (NC) VB (NC) VC (NC) SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 X Y 5210 5090 4970 4850 4730 4610 4490 4370 4250 4130 4010 3890 3770 3650 3400 3150 2900 2650 2400 2150 1900 1650 1699 1699 1699 1699 1699 1699 1699 1699 1699 1699 1699 1699 1699 1699 1699 1699 1699 1699 1699 1699 1699 1699 1270 830 440 190 ­60 ­450 ­890 ­1330 ­1770 ­2150 ­2400 ­2650 ­2900 ­3150 ­3400 ­3650 ­3770 ­3890 ­4010 ­4130 ­4250 ­4370 1699 1699 1699 1699 1699 1699 1699 1699 1699 1699 1699 1699 1699 1699 1699 1699 1699 1699 1699 1699 1699 1699 Pad Number Name 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 SEG7 SEG8 SEG9 SEG10 SEG10 SEG11 SEG11 SEG12 SEG12 SEG13 SEG13 SEG14 SEG14 SEG15 SEG15 SEG16 SEG16 SEG17 SEG17 SEG18 SEG18 SEG19 SEG19 SEG20 SEG20 SEG21 SEG21 SEG22 SEG22 SEG23 SEG23 SEG24 SEG24 SEG25 SEG25 SEG26 SEG26 SEG27 SEG27 SEG28 SEG28 SEG29 SEG29 SEG30 SEG30 SEG31 SEG31 SEG32 SEG32 SEG33 SEG33 SEG34 SEG34 SEG35 SEG35 SEG36 SEG36 SEG37 SEG37 SEG38 SEG38 SEG39 SEG39 SEG40 SEG40 SEG41 SEG41 SEG42 SEG42 SEG43 SEG43 SEG44 SEG44 SEG45 SEG45 SEG46 SEG46 SEG47 SEG47 SEG48 SEG48 SEG49 SEG49 SEG50 SEG50 X Y ­4490 ­4610 ­4730 ­4850 ­4970 ­5090 ­5210 ­5436 ­5436 ­5436 ­5436 ­5436 ­5436 ­5436 ­5436 ­5436 ­5436 ­5436 ­5436 ­5436 ­5436 ­5436 ­5436 ­5436 ­5436 ­5436 ­5436 ­5436 ­5436 ­5436 ­5436 ­5100 ­4980 ­4860 ­4740 ­4620 ­4500 ­4380 ­4260 ­4140 ­4020 ­3900 ­3780 ­3660 1699 1699 1699 1699 1699 1699 1699 1343 1223 1103 983 863 743 623 503 383 263 143 23 ­97 ­217 ­337 ­457 ­577 ­697 ­817 ­937 ­1057 ­1177 ­1297 ­1417 ­1699 ­1699 ­1699 ­1699 ­1699 ­1699 ­1699 ­1699 ­1699 ­1699 ­1699 ­1699 ­1699 683 Pad Number Name 89 SEG51 SEG51 90 SEG52 SEG52 91 SEG53 SEG53 92 SEG54 SEG54 93 SEG55 SEG55 94 SEG56 SEG56 95 SEG57 SEG57 96 SEG58 SEG58 97 SEG59 SEG59 98 SEG60 SEG60 99 SEG61 SEG61 100 SEG62 SEG62 101 SEG63 SEG63 102 SEG64 SEG64 103 SEG65 SEG65 104 SEG66 SEG66 105 SEG67 SEG67 106 SEG68 SEG68 107 SEG69 SEG69 108 SEG70 SEG70 109 SEG71 SEG71 110 SEG72 SEG72 111 SEG73 SEG73 112 SEG74 SEG74 113 SEG75 SEG75 114 SEG76 SEG76 115 SEG77 SEG77 116 SEG78 SEG78 117 SEG79 SEG79 118 SEG80 SEG80 119 SEG81 SEG81 120 SEG82 SEG82 121 SEG83 SEG83 122 SEG84 SEG84 123 SEG85 SEG85 124 SEG86 SEG86 125 SEG87 SEG87 126 SEG88 SEG88 127 SEG89 SEG89 128 SEG90 SEG90 129 SEG91 SEG91 130 SEG92 SEG92 131 SEG93 SEG93 132 SEG94 SEG94 X Y ­3540 ­3420 ­3300 ­3180 ­3060 ­2940 ­2820 ­2700 ­2580 ­2460 ­2340 ­2220 ­2100 ­1980 ­1860 ­1740 ­1620 ­1500 ­1380 ­1260 ­1140 ­1020 ­900 ­780 ­660 ­540 ­420 ­300 ­180 ­60 60 180 300 420 540 660 780 900 1020 1140 1260 1380 1500 1620 ­1699 ­1699 ­1699 ­1699 ­1699 ­1699 ­1699 ­1699 ­1699 ­1699 ­1699 ­1699 ­1699 ­1699 ­1699 ­1699 ­1699 ­1699 ­1699 ­1699 ­1699 ­1699 ­1699 ­1699 ­1699 ­1699 ­1699 ­1699 ­1699 ­1699 ­1699 ­1699 ­1699 ­1699 ­1699 ­1699 ­1699 ­1699 ­1699 ­1699 ­1699 ­1699 ­1699 ­1699 SED1770/71 SED1770/71 Pad Number Name 133 SEG95 SEG95 134 SEG96 SEG96 135 SEG97 SEG97 136 SEG98 SEG98 137 SEG99 SEG99 138 SEG100 SEG100 139 SEG101 SEG101 140 SEG102 SEG102 141 SEG103 SEG103 142 SEG104 SEG104 143 SEG105 SEG105 144 SEG106 SEG106 145 SEG107 SEG107 146 SEG108 SEG108 147 SEG109 SEG109 148 SEG110 SEG110 149 SEG111 SEG111 150 SEG112 SEG112 X Y 1740 1860 1980 2100 2220 2340 2460 2580 2700 2820 2940 3060 3180 3300 3420 3540 3660 3780 ­1699 ­1699 ­1699 ­1699 ­1699 ­1699 ­1699 ­1699 ­1699 ­1699 ­1699 ­1699 ­1699 ­1699 ­1699 ­1699 ­1699 ­1699 Pad Number Name 151 SEG113 SEG113 152 SEG114 SEG114 153 SEG115 SEG115 154 SEG116 SEG116 155 SEG117 SEG117 156 SEG118 SEG118 157 SEG119 SEG119 158 SEG120 SEG120 159 SEG121 SEG121 160 SEG122 SEG122 161 SEG123 SEG123 162 SEG124 SEG124 163 SEG125 SEG125 164 SEG126 SEG126 165 SEG127 SEG127 166 SEG128 SEG128 167 SEG129 SEG129 168 SEG130 SEG130 X Y 3900 4020 4140 4260 4380 4500 4620 4740 4860 4980 5100 5436 5436 5436 5436 5436 5436 5436 ­1699 ­1699 ­1699 ­1699 ­1699 ­1699 ­1699 ­1699 ­1699 ­1699 ­1699 ­1417 ­1297 ­1177 ­1057 ­937 ­817 ­697 (*) SEG160 SEG160 and 161 become NC in the case of SED1770DOA SED1770DOA 684 Pad Number Name 169 SEG131 SEG131 170 SEG132 SEG132 171 SEG133 SEG133 172 SEG134 SEG134 173 SEG135 SEG135 174 SEG136 SEG136 175 SEG137 SEG137 176 SEG138 SEG138 177 SEG139 SEG139 178 SEG140 SEG140 179 SEG141 SEG141 180 SEG142 SEG142 181 SEG143 SEG143 182 SEG144 SEG144 183 SEG145 SEG145 184 SEG146 SEG146 185 SEG147 SEG147 X Y 5436 5436 5436 5436 5436 5436 5436 5436 5436 5436 5436 5436 5436 5436 5436 5436 5436 ­577 ­457 ­337 ­217 ­97 23 143 263 383 503 623 743 863 983 1103 1223 1343 SED1770/71 SED1770/71 s EXTERNAL PACKAGE DIMENSIONS 1.50 9.40 9.82 NCx3 Ø 1.00 NC 216­ TEST­1 OE LP XSCL SHL EIO2 EIO1 0.18 1.00 TEST­2 VSS VDDH 30.06 23.00 28.00 24.00 NC Vd1 SED1770DOA SED1770DOA Vd2 VCOM VSS VDD VDDH VSS VA VB VC 216­ NC 1.00 NCx3 3.92 5.90 X(+) IC MAX 0.8 MAX 0.8 MAX 0.3 685 SED1770/71 SED1770/71 THIS PAGE INTENTIONALLY BLANK 686