HC4059 CD54/74HC4059 SCHS206A CD4059A CD4000B AN6374 CD54HC4059F3A CD74HC4059E - Datasheet Archive

 

(CD74 HC4059 ) /Subject (HighSpeed CMOS Logic CMOS Pro- CD54/74HC4059 Data sheet acquired from Harris Semiconductor SCHS206A

 

[ /Title (CD74 HC4059 HC4059 ) /Subject (HighSpeed CMOS Logic CMOS Pro- CD54/74HC4059 CD54/74HC4059 Data sheet acquired from Harris Semiconductor SCHS206A SCHS206A High-Speed CMOS Logic CMOS Programmable Divide-by-N Counter February 1998 - Revised May 2000 Features Description · Synchronous Programmable ÷N Counter N = 3 to 9999 or 15999 The 'HC4059 HC4059 are high-speed silicon-gate devices that are pin-compatible with the CD4059A CD4059A devices of the CD4000B CD4000B series. These devices are divide-by-N down-counters that can be programmed to divide an input frequency by any number "N" from 3 to 15,999. The output signal is a pulse one clock cycle wide occurring at a rate equal to the input frequency divide by N. The down-counter is preset by means of 16 jam inputs. · Presettable Down-Counter · Fully Static Operation · Mode-Select Control of Initial Decade Counting Function (÷10, 8, 5, 4, 2) · Master Preset Initialization The three Mode-Select Inputs Ka, Kb and Kc determine the modulus ("divide-by" number) of the first and last counting sections in accordance with the truth table. Every time the first (fastest) counting section goes through one cycle, it reduces by 1 the number that has been preset (jammed) into the three decades of the intermediate counting section an the last counting section, which consists of flip-flops that are not needed for opening the first counting section. For example, in the ÷2 mode, only one flip-flop is needed in the first counting section. Therefore the last counting section has three flip-flops that can be preset to a maximum count of seven with a place value of thousands. If ÷10 is desired for the first section, Ka is set "high", Kb "high" and Kc "low". Jam inputs J1, J2, J3, and J4 are used to preset the first counting section and there is no last counting section. The intermediate counting section consists of three cascaded BCD decade (÷10) counters presettable by means of Jam Inputs J5 through J16. · Latchable ÷N Output · Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads · Wide Operating Temperature Range . . . -55oC to 125oC · Balanced Propagation Delay and Transition Times · Significant Power Reduction Compared to LSTTL Logic ICs · HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V The Mode-Select Inputs permit frequency-synthesizer channel separations of 10, 12.5, 20, 25 or 50 parts. These inputs set the maximum value of N at 9999 (when the first counting section divides by 5 or 10) or 15,999 (when the first counting section divides by 8, 4, or 2). Applications · Communications Digital Frequency Synthesizers; VHF, UHF, FM, AM, etc. · Fixed or Programmable Frequency Division The three decades of the intermediate counter can be preset to a binary 15 instead of a binary 9, while their place values are still 1, 10, and 100, multiplied by the number of the ÷N mode. For example, in the ÷8 mode, the number from which counting down begins can be preset to: 3rd Decade 1500 2nd Decade 150 1st Decade 15 Last Counting Section 1000 · "Time Out" Timer for Consumer-Application Industrial Controls · AN6374 AN6374 "Application of the CMOS CD4059A CD4059A Programmable Divide-by-N Counter in FM and Citizens Band Transceiver Digital Tuners" Ordering Information PART NUMBER TEMP. RANGE (oC) The total of these numbers (2665) times 8 equals 12,320. The first counting section can be preset to 7. Therefore, 21,327 is the maximum possible count in the ÷8 mode. PACKAGE CD54HC4059F3A CD54HC4059F3A -55 to 125 24 Ld CERDIP CD74HC4059E CD74HC4059E -55 to 125 24 Ld PDIP The highest count of the various modes is shown in the Extended Counter Range column. Control inputs Kb and Kc can be used to initiate and lock the counter in the "master preset" state. In this condition the flip-flops in the counter are preset in accordance with the jam inputs and the counter remains in that state as long as Kb and Kc both remain low. The counter begins to count down from the preset state when a counting mode other than the master preset mode is selected. NOTE: 1. Wafer and die is available which meets all electrical specifications. Please contact your local TI sales office or customer service for ordering information. CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2000, Texas Instruments Incorporated 1 CD54/74HC4059 CD54/74HC4059 Pinout The counter should always be put in the master preset mode before the ÷5 mode is selected. Whenever the master preset mode is used, control signals Kb = "low" and Kc = "low" must be applied for at least 3 full clock pulses. CD54HC4059 CD54HC4059 (CERDIP) CD74HC4059 CD74HC4059 (PDIP) TOP VIEW After Preset Mode inputs have been changed to one of the ÷ modes, the next positive-going clock transition changes an internal flip-flop so that the countdown can begin at the second positive-going clock transition. Thus, after an MP (Master Preset) mode, there is always one extra count before the output goes high. Figure 1 illustrates a total count of 3 (÷8 mode). If the Master Preset mode is started two clock cycles or less before an output pulse, the output pulse will appear at the time due. If the Master Preset Mode is not used, the counter jumps back to the "Jam" count when the output pulse appears. CP 1 23 Q J1 3 22 J5 J2 4 21 J6 J3 5 20 J7 J4 6 19 J8 J16 7 18 J9 J15 8 17 J10 J14 9 16 J11 J13 10 15 J12 Kc 11 14 Ka GND 12 A "high" on the Latch Enable input will cause the counter output to remain high once an output pulse occurs, and to remain in the high state until the latch input returns to "low". If the Latch Enable is "low", the output pulse will remain high for only one cycle of the clock-input signal. 24 VCC LE 2 13 Kb Functional Diagram J1 - J16 CP Ka f IN Q = - N Kb Kc LE TRUTH TABLE COUNTER RANGE MODE SELECT INPUT FIRST COUNTING SECTION CAN BE PRESET MODE TO A MAX DIVIDES-BY OF: (NOTE 3) JAM INPUTS USED: LAST COUNTING SECTION CAN BE PRESET MODE TO A MAX DIVIDES-BY OF: DESIGN EXTENDED (NOTE 3) JAM INPUTS USED: MAX MAX Ka Kb Kc H H H 2 1 J1 8 7 J2, J3, J4 15,999 17,331 L H H 4 3 J1, J2 4 3 J3, J4 15,999 18,663 H L H 5 (Note 4) 4 J1, J2, J3 2 1 J4 9,999 13,329 L L H 8 7 J1, J2, J3 2 1 J4 15,999 21,327 H H L 10 9 J1, J2, J3, J4 1 0 - 9,999 16,659 X L L - - Master Preset Master Preset NOTES: 2. X = Don't Care 3. J1 = Least Significant Bit. J4 = Most Significant Bit. 4. Operation in the ÷5 mode (1st counting section) requires going through the Master Preset mode prior to going into the ÷5 mode. At power turn-on, Kc must be "low" for a period of 3 input clock pulses after VCC reaches a minimum of 3V. 2 CD54/74HC4059 CD54/74HC4059 How to Preset the HC/HCT4059 HC/HCT4059 to Desired ÷N The value N is determined as follows: N Preset Value = Mode (EQ. 1) N = (MODE) (1000 x Decade 5 Preset + 100 x Decade 4 Preset + 10 x Decade 3 Preset + 1 x Decade 2 Preset) + Decade 1 Preset Example: N = 8479, Mode = 5 MODE = First counting section divider (10, 8, 5, 4 or 2) To calculate preset values for any N count, divide the N count by the Mode. The resultant is the corresponding preset values of the 5th through 2nd decade with the remainder being equal to the 1st decade value. (EQ. 2) Mode Select = 5 Ka Kb Kc H L H 1695 + 4 (Preset Values) 5 | 8479 Mode N Program Jam Inputs (BCD) 4 J1 L 1 J2 J3 L 9 5 J4 J5 J6 J7 H H H L J9 J10 J8 H H L 6 J11 J12 J13 J14 J15 J16 L H L H H L L NOTE: To verify the results, use Equation 1: N = 5 (1000 x 1 + 100 x 6 + 10 x 9 + 1 x 5) + 4 N = 8479 PROGRAM JAM INPUTS (BCD) J1 J2 J3 3 12 4 J4 5 J5 6 J6 22 J7 21 J8 20 J9 J10 J11 J12 19 18 17 16 J13 J14 J15 J16 15 10 9 8 7 P.E. GND PRESETTABLE LOGIC 24 VCC CLOCK INPUT FIRST COUNTING SECTION ÷10, 8, 5, 4, 2 1 LAST COUNTING SECTION ÷1, 2, 2, 4, 8 INTERMEDIATE COUNTING SECTION ÷10 ÷10 ÷10 RECOGNITION GATING 14 Ka MODE SELECT INPUTS 13 Kb 11 MODE CONTROL PRESET ENABLE Kc 23 2 OUTPUT STAGE LATCH ENABLE FIGURE 1. FUNCTIONAL BLOCK DIAGRAM 3 DIVIDE-BY-N OUTPUT CD54/74HC4059 CD54/74HC4059 Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA Thermal Resistance (Typical, Note 5) JA (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Maximum Junction Temperature (Hermetic Package or Die) . . . 175oC Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC Operating Conditions Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max) CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 5. JA is measured with the component mounted on an evaluation PC board in free air. DC Electrical Specifications TEST CONDITIONS 25oC -40oC TO 85oC -55oC TO 125oC IO (mA) MIN TYP MAX MIN MAX MIN MAX UNITS - - 2 1.5 - - 1.5 - 1.5 - V 4.5 3.15 - - 3.15 - 3.15 - V 4.2 - - 4.2 - 4.2 - V 2 - - 0.5 - 0.5 - 0.5 V 4.5 - - 1.35 - 1.35 - 1.35 V - - 1.8 - 1.8 - 1.8 V -0.02 2 1.9 - - 1.9 - 1.9 - V -0.02 4.5 4.4 - - 4.4 - 4.4 - V -0.02 6 5.9 - - 5.9 - 5.9 - V - - - - - - - - - V -4 4.5 3.98 - - 3.84 - 3.7 - V -5.2 6 5.48 - - 5.34 - 5.2 - V 0.02 2 - - 0.1 - 0.1 - 0.1 V 0.02 4.5 - - 0.1 - 0.1 - 0.1 V 0.02 High Level Output Voltage CMOS Loads VI (V) VIH 6 Low Level Input Voltage SYMBOL 6 PARAMETER High Level Input Voltage VCC (V) 6 - - 0.1 - 0.1 - 0.1 V VIL VOH - VIH or VIL High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads VOL VIH or VIL Low Level Output Voltage TTL Loads - Quiescent Device Current - - - - - - - - V 4.5 - - 0.26 - 0.33 - 0.4 V 5.2 Input Leakage Current 4 6 - - 0.26 - 0.33 - 0.4 V II VCC or GND - 6 - - ±0.1 - ±1 - ±1 µA ICC VCC or GND 0 6 - - 8 - 80 - 160 µA 4 CD54/74HC4059 CD54/74HC4059 Prerequisite for Switching Specifications 25oC PARAMETER -40oC TO 85oC -55oC TO 125oC TYP MAX MIN TYP MAX MIN TYP MAX UNITS tW 2 90 - - 115 - - 135 - - ns 18 - - 23 - - 27 - - ns 15 - - 20 - - 23 - - ns 2 75 - - 95 - - 110 - - ns 4.5 15 - - 19 - - 22 - - ns 6 13 - - 16 - - 19 - - ns 2 5 - - 4 - - 4 - - MHz 4.5 27 - - 22 - - 18 - - MHz 6 CP Frequency MIN 6 Setup Time Kb, Kc to CP VCC (V) 4.5 Pulse Width CP SYMBOL 32 - - 26 - - 21 - - MHz tSU fMAX Switching Specifications Input tr, tf = 6ns 25oC -40oC TO 85oC -55oC TO 125oC Power Dissipation Capacitance (Notes 6, 7) MAX MIN MAX UNITS tPLH, tPHL CL = 50pF 2 - - 200 - 250 - 300 ns 4.5 - - 40 - 50 - 60 ns - - 34 - 43 - 51 ns 5 - 17 - - - - - ns CL = 50pF 2 - - 175 - 220 - 265 ns 4.5 - - 35 - 44 - 53 ns - - 30 - 37 - 45 ns 5 - 14 - - - - - ns CL = 50pF 2 - - 75 - 95 - 110 ns - - 15 - 19 - 22 ns 6 Input Capacitance MIN 4.5 CP Frequency MAX CL = 15pF Output Transition Time TYP 6 Propagation Delay, LE to Q MIN CL = 15pF Propagation Delay, CP to Q SYMBOL VCC (V) 6 PARAMETER TEST CONDITIONS - - 13 - 16 - 19 ns tPLH, tPHL tTHL, tTLH fMAX CL = 15pF 5 - 54 - - - - - MHz CI - - - - 10 - 10 - 10 pF CPD - 5 - 36 - - - - - pF NOTES: 6. CPD is used to determine the dynamic power consumption, per package. 7. PD = CPD VCC2 fi + CL VCC2 fo where fi = input frequency, fo = output frequency, CL = output load capacitance, VCC = supply voltage. 5 CD54/74HC4059 CD54/74HC4059 Test Circuits and Waveforms tr = 6ns tfCL trCL CLOCK 90% 10% I tWL + tWH = fCL tf = 6ns VCC 50% 10% tWL 50% VCC 90% 50% 10% INPUT GND 50% tTHL GND tTLH 90% 50% 10% tWH INVERTING OUTPUT NOTE: Outputs should be switching from 10% VCC to 90% VCC in accordance with device truth table. For fMAX, input duty cycle = 50%. tPHL FIGURE 2. HC CLOCK PULSE RISE AND FALL TIMES AND PULSE WIDTH FIGURE 3. HC TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC tfCL trCL CLOCK INPUT VCC 90% 50% 10% GND tH(H) tH(L) VCC DATA INPUT 50% GND tSU(H) tSU(L) 90% tTLH tTHL 90% 50% 10% tPLH tPHL OUTPUT tREM VCC SET, RESET OR PRESET tPLH 50% GND IC CL 50pF FIGURE 4. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME, AND PROPAGATION DELAY TIMES FOR EDGE TRIGGERED SEQUENTIAL LOGIC CIRCUITS 6 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof. Copyright © 2000, Texas Instruments Incorporated