CD74H CT533 CT563 CD54/74HC533 CD54/74HCT533 CD54/74HC563 CD74HCT563 SCHS187C - Datasheet Archive

 

(CD74H C533, CD74H CT533, CD74H C563, CD74H CT563) /Subject (High Speed CD54/74HC533, CD54/74HCT533, CD54/74HC563, CD74HCT563

 

[ /Title (CD74H CD74H C533, CD74H CD74H CT533 CT533, CD74H CD74H C563, CD74H CD74H CT563 CT563) /Subject (High Speed CD54/74HC533 CD54/74HC533, CD54/74HCT533 CD54/74HCT533, CD54/74HC563 CD54/74HC563, CD74HCT563 CD74HCT563 Data sheet acquired from Harris Semiconductor SCHS187C SCHS187C January 1998 - Revised July 2003 High-Speed CMOS Logic Octal Inverting Transparent Latch, Three-State Outputs Features Description · Common Latch-Enable Control The 'HC533 HC533, 'HCT533 HCT533, 'HC563 HC563, and CD74HCT563 CD74HCT563 are high-speed Octal Transparent Latches manufactured with silicon gate CMOS technology. They possess the low power consumption of standard CMOS integrated circuits, as well as the ability to drive 15 LSTTL devices. · Common Three-State Output Enable Control · Buffered Inputs · Three-State Outputs The outputs are transparent to the inputs when the latch enable (LE) is high. When the latch enable (LE) goes low the data is latched. The output enable (OE) controls the three-state outputs. When the output enable (OE) is high the outputs are in the high impedance state. The latch operation is independent of the state of the output enable. · Bus Line Driving Capacity · Typical Propagation Delay = 13ns at VCC = 5V, CL = 15pF, TA = 25oC (Data to Output) · Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads The 'HC533 HC533 and 'HCT533 HCT533 are identical in function to the 'HC563 HC563 and CD74HCT563 CD74HCT563 but have different pinouts. The 'HC533 HC533 and 'HCT533 HCT533 are similar to the 'HC373 HC373 and 'HCT373 HCT373; the latter are non-inverting types. · Wide Operating Temperature Range . . . -55oC to 125oC · Balanced Propagation Delay and Transition Times Ordering Information · Significant Power Reduction Compared to LSTTL Logic ICs · HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V PART NUMBER TEMP. RANGE (oC) PACKAGE CD54HC533F3A CD54HC533F3A 20 Ld CERDIP CD54HC563F3A CD54HC563F3A -55 to 125 20 Ld CERDIP CD54HCT533F3A CD54HCT533F3A -55 to 125 20 Ld CERDIP CD74HC533E CD74HC533E -55 to 125 20 Ld PDIP CD74HC563E CD74HC563E -55 to 125 20 Ld PDIP CD74HC563M CD74HC563M -55 to 125 20 Ld SOIC CD74HCT533E CD74HCT533E -55 to 125 20 Ld PDIP CD74HCT563E CD74HCT563E -55 to 125 20 Ld PDIP CD74HCT563M CD74HCT563M · HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il 1µA at VOL, VOH -55 to 125 -55 to 125 20 Ld SOIC CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, Texas Instruments Incorporated 1 CD54/74HC533 CD54/74HC533, CD54/74HCT533 CD54/74HCT533, CD54/74HC563 CD54/74HC563, CD74HCT563 CD74HCT563 Pinouts CD54HC533 CD54HC533, CD54HCT533 CD54HCT533 (CERDIP) CD74HC533 CD74HC533, CD74HCT533 CD74HCT533 (PDIP) TOP VIEW CD54HC563 CD54HC563 (CERDIP) CD74HC563 CD74HC563, CD74HCT563 CD74HCT563 (PDIP, SOIC) TOP VIEW OE 1 20 VCC OE 1 Q0 2 19 Q7 D0 2 19 Q0 D0 3 18 D7 D1 3 18 Q1 20 VCC D1 4 17 D6 D2 4 17 Q2 Q1 5 16 Q6 D3 5 16 Q3 Q2 6 15 Q5 D4 6 15 Q4 D2 7 14 D5 D5 7 14 Q5 D3 8 13 D4 D6 8 13 Q6 Q3 9 12 Q4 D7 9 12 Q7 GND 10 11 LE GND 10 11 LE Functional Block Diagram HC/HCT533 HC/HCT533 D0 D1 D O D2 D G O D3 D G O D4 O D G D5 D G O D6 D G O D7 D G O D G O G LE OE O0 O1 O2 O3 O4 O5 O6 O7 TRUTH TABLE OUTPUT ENABLE LATCH ENABLE DATA Q OUTPUT L H H L L H L H L L l H L L h L H X X Z H = High Voltage Level, L = Low Voltage Level, X = Don't Care, Z = High Impedance State, l = Low voltage level one set-up time prior to the high to low latch enable transition, h = High voltage level one set-up time prior to the high to low latch enable transition. 2 CD54/74HC533 CD54/74HC533, CD54/74HCT533 CD54/74HCT533, CD54/74HC563 CD54/74HC563, CD74HCT563 CD74HCT563 Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Drain Current, per Output, IO For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±35mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA Thermal Resistance (Typical, Note 1) JA (oC/W) E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . 69 M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . 58 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Operating Conditions Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max) CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. The package thermal impedance is calculated in accordance with JESD 51-7. DC Electrical Specifications TEST CONDITIONS PARAMETER SYMBOL VI (V) VIH - 25oC IO (mA) VCC (V) -40oC TO 85oC -55oC TO 125oC MIN TYP MAX MIN MAX MIN MAX UNITS 2 1.5 - - 1.5 - 1.5 - V 4.5 3.15 - - 3.15 - 3.15 - V 6 4.2 - - 4.2 - 4.2 - V HC TYPES High Level Input Voltage Low Level Input Voltage VOH - VIH or VIL - 2 - - 0.5 - 0.5 - 0.5 V 4.5 - - 1.35 - 1.35 - 1.35 V 6 High Level Output Voltage CMOS Loads VIL - - - 1.8 - 1.8 - 1.8 V 2 1.9 - - 1.9 - 1.9 - V -0.02 4.5 4.4 - - 4.4 - 4.4 - V -0.02 High Level Output Voltage TTL Loads -0.02 6 5.9 - - 5.9 - 5.9 - V Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current - - 3.84 - 3.7 - V 5.48 - - 5.34 - 5.2 - V 0.02 2 - - 0.1 - 0.1 - 0.1 V 0.02 4.5 - - 0.1 - 0.1 - 0.1 V 6 - - 0.1 - 0.1 - 0.1 V 4.5 - - 0.26 - 0.33 - 0.4 V 7.8 VIH or VIL 3.98 6 6 VOL 4.5 0.02 Low Level Output Voltage CMOS Loads -6 -7.8 6 - - 0.26 - 0.33 - 0.4 V II VCC or GND - 6 - - ±0.1 - ±1 - ±1 µA ICC VCC or GND 0 6 - - 8 - 80 - 160 µA 3 CD54/74HC533 CD54/74HC533, CD54/74HCT533 CD54/74HCT533, CD54/74HC563 CD54/74HC563, CD74HCT563 CD74HCT563 DC Electrical Specifications (Continued) TEST CONDITIONS 25oC SYMBOL VI (V) IO (mA) VCC (V) - VIL or VIH VO = VCC or GND High Level Input Voltage VIH - Low Level Input Voltage VIL High Level Output Voltage CMOS Loads VOH PARAMETER Three-State Leakage Current -40oC TO 85oC -55oC TO 125oC MIN TYP MAX MIN MAX MIN MAX UNITS 6 - - ±0.5 - ±5 - ±10 µA - 4.5 to 5.5 2 - - 2 - 2 - V - - 4.5 to 5.5 - - 0.8 - 0.8 - 0.8 V VIH or VIL -0.02 4.5 4.4 - - 4.4 - 4.4 - V -6 4.5 3.98 - - 3.84 - 3.7 - V 0.02 4.5 - - 0.1 - 0.1 - 0.1 V 6 4.5 - - 0.26 - 0.33 - 0.4 V HCT TYPES High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads VOL VIH or VIL Low Level Output Voltage TTL Loads II VCC to GND - 5.5 - - ±0.1 - ±1 - ±1 µA ICC VCC or GND 0 5.5 - - 8 - 80 - 160 µA Three-State Leakage Current - VIL or VIH VO = VCC or GND 5.5 - - ±0.5 - ±5 - ±10 µA Additional Quiescent Device Current Per Input Pin: 1 Unit Load ICC (Note 2) VCC -2.1 - 4.5 to 5.5 - 100 360 - 450 - 490 µA Input Leakage Current Quiescent Device Current NOTE: 2. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA. HCT Input Loading Table INPUT UNIT LOADS D0 - D7 0.15 LE 0.30 OE 0.55 NOTE: Unit Load is ICC limit specified in DC Electrical Specifications table, e.g., 360µA max at 25oC. 4 CD54/74HC533 CD54/74HC533, CD54/74HCT533 CD54/74HCT533, CD54/74HC563 CD54/74HC563, CD74HCT563 CD74HCT563 Prerequisite For Switching Specifications 25oC -40oC TO 85oC -55oC TO 125oC SYMBOL VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS tW - 2 80 - - 100 - 120 - ns 4.5 16 - - 20 - 24 - ns 6 14 - - 17 - 20 - ns 2 50 - - 65 - 75 - ns 4.5 10 - - 13 - 15 - ns 6 9 - - 11 - 13 - ns 2 35 - - 45 - 55 - ns 4.5 7 - - 9 - 11 - ns 6 6 - - 8 - 7 - ns 2 4 - - 4 - 4 - ns 4.5 4 - - 4 - 4 - ns 6 PARAMETER TEST CONDITIONS 4 - - 4 - 4 - ns HC TYPES LE Pulse Width Set-up Time Data to LE tSU Hold Time, Data to LE (533) - tH Hold Time, Data to LE (563) - tH - HCT TYPES LE Pulse Width tw - 4.5 16 - - 20 - 24 - ns Set-up Time Data to LE tw - 4.5 10 - - 13 - 15 - ns Hold Time, Data to LE (533) tH - 4.5 8 - - 10 - 12 - ns Hold Time, Data to LE (563) tH - 4.5 5 - - 5 - 5 - ns Switching Specifications Input tr, tf = 6ns -40oC TO 85oC 25oC -55oC TO 125oC HC TYPES Propagation Delay, Data to Qn (HC533 HC533) SYMBOL TEST CONDITIONS VCC (V) TYP MAX MAX MAX UNITS tPLH, tPHL CL = 50pF 2 - 165 205 250 ns 4.5 - 33 41 50 ns 6 PARAMETER - 28 35 43 ns 5 13 - - - ns CL = 15pF Propagation Delay, Data to Qn (HC563 HC563) - 150 190 225 ns - 30 38 45 ns - 26 33 38 ns CL = 15pF 5 12 - - - ns CL = 50pF 2 - 175 220 265 ns 4.5 - 35 44 53 ns 6 tPLH, tPHL 2 4.5 6 Propagation Delay, LE to Qn (HC533 HC533) tPLH, tPHL CL = 50pF - 30 37 45 ns 5 14 - - - ns CL = 15pF Propagation Delay, LE to Qn (HC563 HC563) tPLH, tPHL CL = 50pF - 165 205 250 ns - 33 41 50 ns 6 CL = 15pF 2 4.5 - 28 35 43 ns 5 13 - - - ns 5 CD54/74HC533 CD54/74HC533, CD54/74HCT533 CD54/74HCT533, CD54/74HC563 CD54/74HC563, CD74HCT563 CD74HCT563 Switching Specifications PARAMETER Enable Times (HC533 HC533) Input tr, tf = 6ns (Continued) SYMBOL TEST CONDITIONS tPZH, tPZL CL = 50pF -40oC TO 85oC 25oC VCC (V) -55oC TO 125oC TYP MAX MAX MAX UNITS 150 190 225 ns 30 38 45 ns - 26 33 38 ns CL = 15pF 5 12 - - - ns CL = 50pF 2 - 150 190 225 ns 4.5 - 30 38 45 ns 6 tPHZ, tPLZ - 6 Disable Times (HC533 HC533) 2 4.5 - 26 33 38 ns 5 12 - - - ns CL = 15pF Enable and Disable Times (HC563 HC563) tPZH, tPZL, tPHZ, tPLZ CL = 50pF 2 - 150 190 225 ns 4.5 - 30 38 45 ns 6 - 26 33 38 ns CL = 15pF 5 12 - - - ns Input Capacitance CI - - - 10 10 10 pF Three-State Output Capacitance CO - - - 20 20 20 pF Power Dissipation Capacitance (Notes 3, 4) CPD - 5 42 - - - pF tPLH, tPHL CL = 50pF 4.5 - 34 43 51 ns CL = 15pF 5 14 - - - ns CL = 50pF 4.5 - 30 38 45 ns CL = 15pF 5 12 - - - ns CL = 50pF 4.5 - 38 48 57 ns CL = 15pF 5 16 - - - ns CL = 50pF 4.5 - 35 44 53 ns CL = 15pF 5 14 - - - ns CL = 50pF 4.5 - 35 44 53 ns CL = 15pF 5 14 - - - ns CL = 50pF 4.5 - 30 38 45 ns CL = 15pF 5 12 - - - ns HCT TYPES Propagation Delay, Data to Qn (HC/HCT533 HC/HCT533) Propagation Delay, Data to Qn (HC/HCT563 HC/HCT563) tPLH, tPHL Propagation Delay, LE to Qn (HC/HCT533 HC/HCT533) tPLH, tPHL Propagation Delay, LE to Qn (HC/HCT563 HC/HCT563) tPZL, tPZH Enable Times (HC/HCT533 HC/HCT533) tPLZ, tPZH Disable Times (HC/HCT533 HC/HCT533) tTLH, tTHL Enable and Disable Times (HC/HCT563 HC/HCT563) tPZH, tPZL, tPHZ, tPLZ CL = 50pF 4.5 - 35 44 53 ns CL = 15pF 5 14 - - - ns Input Capacitance CI - - - 10 10 10 pF Power Dissipation Capacitance (Notes 3, 4) CPD - 5 42 - - - pF NOTES: 3. CPD is used to determine the no-load dynamic power consumption, per latch. 4. PD (total power per latch) = CPD VCC2 fi + CL VCC2 fo where fi = Input Frequency, fo = Output Frequency, CL = Output Load Capacitance, VCC = Supply Voltage. 6 CD54/74HC533 CD54/74HC533, CD54/74HCT533 CD54/74HCT533, CD54/74HC563 CD54/74HC563, CD74HCT563 CD74HCT563 Test Circuits and Waveforms tWL + tWH = tfCL trCL 50% 10% 10% tf = 6ns tr = 6ns tTLH 90% INVERTING OUTPUT tPHL FIGURE 3. HC TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC tPLH FIGURE 4. HCT TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC trCL tfCL VCC tfCL GND 1.3V 0.3V GND tH(H) tH(L) VCC DATA INPUT 3V 2.7V CLOCK INPUT 50% tH(H) tTLH 1.3V 10% tPLH 10% GND tTHL 90% 50% 10% 90% 3V 2.7V 1.3V 0.3V GND tTHL trCL tWH FIGURE 2. HCT CLOCK PULSE RISE AND FALL TIMES AND PULSE WIDTH INPUT INVERTING OUTPUT GND NOTE: Outputs should be switching from 10% VCC to 90% VCC in accordance with device truth table. For fMAX, input duty cycle = 50%. VCC 90% 50% 10% 1.3V 1.3V tWL tf = 6ns tPHL 1.3V 0.3V tWH FIGURE 1. HC CLOCK PULSE RISE AND FALL TIMES AND PULSE WIDTH INPUT 2.7V 0.3V GND tr = 6ns DATA INPUT 50% tH(L) 3V 1.3V 1.3V 1.3V GND tSU(H) tSU(H) tSU(L) tTLH 90% OUTPUT tTHL 90% 50% 10% tTLH 90% 1.3V OUTPUT tREM 3V SET, RESET OR PRESET GND tTHL 1.3V 10% FIGURE 5. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME, AND PROPAGATION DELAY TIMES FOR EDGE TRIGGERED SEQUENTIAL LOGIC CIRCUITS tPHL 1.3V GND IC CL 50pF GND 90% tPLH 50% IC tSU(L) tPHL tPLH I fCL 3V NOTE: Outputs should be switching from 10% VCC to 90% VCC in accordance with device truth table. For fMAX, input duty cycle = 50%. tREM VCC SET, RESET OR PRESET tfCL = 6ns CLOCK 50% 50% tWL CLOCK INPUT tWL + tWH = trCL = 6ns VCC 90% CLOCK I fCL CL 50pF FIGURE 6. HCT SETUP TIMES, HOLD TIMES, REMOVAL TIME, AND PROPAGATION DELAY TIMES FOR EDGE TRIGGERED SEQUENTIAL LOGIC CIRCUITS 7 CD54/74HC533 CD54/74HC533, CD54/74HCT533 CD54/74HCT533, CD54/74HC563 CD54/74HC563, CD74HCT563 CD74HCT563 Test Circuits and Waveforms 6ns (Continued) 6ns OUTPUT DISABLE tr VCC 90% 50% 10% OUTPUTS ENABLED OUTPUT HIGH TO OFF 50% OUTPUTS DISABLED FIGURE 7. HC THREE-STATE PROPAGATION DELAY WAVEFORM OTHER INPUTS TIED HIGH OR LOW OUTPUT DISABLE IC WITH THREESTATE OUTPUT GND 1.3V tPZH 90% OUTPUTS ENABLED OUTPUTS ENABLED 0.3 10% tPHZ tPZH 90% 3V tPZL tPLZ OUTPUT LOW TO OFF 50% OUTPUT HIGH TO OFF 6ns GND 10% tPHZ tf 2.7 1.3 tPZL tPLZ OUTPUT LOW TO OFF 6ns OUTPUT DISABLE 1.3V OUTPUTS DISABLED OUTPUTS ENABLED FIGURE 8. HCT THREE-STATE PROPAGATION DELAY WAVEFORM OUTPUT RL = 1k CL 50pF VCC FOR tPLZ AND tPZL GND FOR tPHZ AND tPZH NOTE: Open drain waveforms tPLZ and tPZL are the same as those for three-state shown on the left. The test circuit is Output RL = 1k to VCC, CL = 50pF. FIGURE 9. HC AND HCT THREE-STATE PROPAGATION DELAY TEST CIRCUIT 8 MECHANICAL MPDI002C MPDI002C ­ JANUARY 1995 ­ REVISED DECEMBER 20002 N (R-PDIP-T*) PLASTIC DUAL-IN-LINE PACKAGE 16 PINS SHOWN PINS * 14 16 18 20 A MAX 0.775 (19,69) 0.775 (19,69) 0.920 (23,37) 1.060 (26,92) A MIN 0.745 (18,92) 0.745 (18,92) 0.850 (21,59) 0.940 (23,88) MS-100 MS-100 VARIATION AA BB AC DIM A 16 9 0.260 (6,60) 0.240 (6,10) 1 C AD 8 0.070 (1,78) 0.045 (1,14) 0.045 (1,14) 0.030 (0,76) D D 0.325 (8,26) 0.300 (7,62) 0.020 (0,51) MIN 0.015 (0,38) Gauge Plane 0.200 (5,08) MAX Seating Plane 0.010 (0,25) NOM 0.125 (3,18) MIN 0.100 (2,54) 0.430 (10,92) MAX 0.021 (0,53) 0.015 (0,38) 0.010 (0,25) M 14/18 PIN ONLY 20 pin vendor option D 4040049/E 4040049/E 12/2002 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-001 MS-001, except 18 and 20 pin minimum body lrngth (Dim A). D. The 20 pin end lead shoulder width is a vendor option, either half or full width. POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 1 MECHANICAL DATA MSOI003E MSOI003E ­ JANUARY 1995 ­ REVISED SEPTEMBER 2001 DW (R-PDSO-G*) PLASTIC SMALL-OUTLINE PACKAGE 16 PINS SHOWN 0.020 (0,51) 0.014 (0,35) 9 0.050 (1,27) 16 0.010 (0,25) 0.419 (10,65) 0.400 (10,15) 0.010 (0,25) NOM 0.299 (7,59) 0.291 (7,39) Gage Plane 0.010 (0,25) 1 8 0°­ 8° 0.050 (1,27) 0.016 (0,40) A Seating Plane 0.104 (2,65) MAX 0.012 (0,30) 0.004 (0,10) PINS * 0.004 (0,10) 16 18 20 24 28 A MAX 0.410 (10,41) 0.462 (11,73) 0.510 (12,95) 0.610 (15,49) 0.710 (18,03) A MIN 0.400 (10,16) 0.453 (11,51) 0.500 (12,70) 0.600 (15,24) 0.700 (17,78) DIM 4040000/E 4040000/E 08/01 NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). Falls within JEDEC MS-013 MS-013 POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 1