HC374 HCT37 HC574 HCT57 CD74HC374 CD74HCT374 CD74HC574 CD74HCT574 SCHS183 - Datasheet Archive

 

(CD74 HC374 , CD74 HCT37 4, CD74 HC574 , CD74 HCT57 CD74HC374, CD74HCT374, CD74HC574, CD74HCT574 Data sheet acquired from Harris

 

[ /Title (CD74 HC374 HC374 , CD74 HCT37 HCT37 4, CD74 HC574 HC574 , CD74 HCT57 HCT57 CD74HC374 CD74HC374, CD74HCT374 CD74HCT374, CD74HC574 CD74HC574, CD74HCT574 CD74HCT574 Data sheet acquired from Harris Semiconductor SCHS183 SCHS183 February 1998 High Speed CMOS Logic Octal D-Type Flip-Flop, Three-State Positive-Edge Triggered Features Description · Buffered Inputs The Harris CD74HC374 CD74HC374, CD74HCT374 CD74HCT374, CD74HC574 CD74HC574 and CD74HCT574 CD74HCT574 are Octal D-Type Flip-Flops with Three-State Outputs and the capability to drive 15 LSTTL loads. The eight edge-triggered flip-flops enter data into their registers on the LOW to HIGH transition of clock (CP). The Output Enable (OE) controls the three-state outputs and is independent of the register operation. When Output Enable (OE) is HIGH the outputs will be in the high impedance state. The 374 and 574 are identical in function and differ only in their pinout arrangements. · Common Three-State Output Enable Control · Three-State Outputs · Bus Line Driving Capability · Typical Propagation Delay (Clock to Q) = 15ns at VCC = 5V, CL = 15pF, TA = 25oC · Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads Ordering Information · Wide Operating Temperature Range . . . -55oC to 125oC PART NUMBER · Balanced Propagation Delay and Transition Times TEMP. RANGE (oC) PKG. NO. PACKAGE CD74HC374E CD74HC374E -55 to 125 20 Ld PDIP E20.3 CD74HCT374E CD74HCT374E -55 to 125 20 Ld PDIP E20.3 CD74HCT574E CD74HCT574E -55 to 125 20 Ld PDIP E20.3 · HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V CD74HC574E CD74HC574E -55 to 125 20 Ld PDIP E20.3 CD74HC574M CD74HC574M -55 to 125 20 Ld SOIC M20.3 CD74HC374M CD74HC374M -55 to 125 20 Ld SOIC M20.3 CD74HCT374M CD74HCT374M -55 to 125 20 Ld SOIC M20.3 · HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il 1µA at VOL, VOH CD74HCT574M CD74HCT574M -55 to 125 20 Ld SOIC M20.3 · Significant Power Reduction Compared to LSTTL Logic ICs NOTES: 1. When ordering, use the entire part number. Add the suffix 96 to obtain the variant in the tape and reel. 2. Wafer and die for this part number is available which meets all electrical specifications. Please contact your local sales office or Harris customer service for ordering information. Pinouts CD74HC374 CD74HC374, CD74HCT374 CD74HCT374 (PDIP, SOIC) TOP VIEW CD74HCT574 CD74HCT574 (PDIP, SOIC) TOP VIEW OE 1 20 VCC OE 1 Q0 2 19 Q7 D0 2 19 Q0 D0 3 18 D7 D1 3 18 Q1 D1 4 17 D6 D2 4 17 Q2 20 VCC Q1 5 16 Q6 D3 5 16 Q3 Q2 6 15 Q5 D4 6 15 Q4 D2 7 14 D5 D5 7 14 Q5 D3 8 13 D4 D6 8 13 Q6 Q3 9 12 Q4 D7 9 12 Q7 GND 10 11 CP GND 10 11 CP CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © Harris Corporation 1998 1 File Number 1663.1 CD74HC374 CD74HC374, CD74HCT374 CD74HCT374, CD74HC574 CD74HC574, CD74HCT574 CD74HCT574 Functional Diagram D0 D1 D2 D D CP Q CP Q D3 D D4 D5 D6 D7 D D D D D CP Q CP Q CP Q CP Q CP Q CP Q CP OE Q0 Q1 Q2 Q3 Q4 Q5 TRUTH TABLE INPUTS OUTPUT OE CP Dn Qn L H H L L L L L X Q0 H X X Z NOTE: H = High Level (Steady State) L = Low Level (Steady State) X = Don't Care = Transition from Low to High Level Q0 = The level of Q before the indicated steady-state input conditions were established Z = High Impedance State 2 Q6 Q7 CD74HC374 CD74HC374, CD74HCT374 CD74HCT374, CD74HC574 CD74HC574, CD74HCT574 CD74HCT574 Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Drain Current, per Output, IO For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±35mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA Thermal Resistance (Typical, Note 3) JA (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Operating Conditions Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max) CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 3. JA is measured with the component mounted on an evaluation PC board in free air. DC Electrical Specifications TEST CONDITIONS 25oC -40oC TO 85oC -55oC TO 125oC SYMBOL VI (V) IO (mA) VIH - - 2 1.5 - - 1.5 4.5 3.15 - - 3.15 - 3.15 - V 6 PARAMETER VCC (V) 4.2 - - 4.2 - 4.2 - V MIN TYP MAX MIN MAX MIN MAX UNITS - 1.5 - V HC TYPES High Level Input Voltage Low Level Input Voltage VIL VOH VIH or VIL - 2 - - 0.5 - 0.5 - 0.5 V 4.5 - - 1.35 - 1.35 - 1.35 V 6 High Level Output Voltage CMOS Loads - - - 1.8 - 1.8 - 1.8 V 2 1.9 - - 1.9 - 1.9 - V -0.02 4.5 4.4 - - 4.4 - 4.4 - V -0.02 6 5.9 - - 5.9 - 5.9 - V - High Level Output Voltage TTL Loads -0.02 - - - - - - - - V VIH or VIL Low Level Output Voltage TTL Loads 3.98 - - 3.84 - 3.7 - V 6 5.48 - - 5.34 - 5.2 - V 0.02 2 - - 0.1 - 0.1 - 0.1 V 0.02 VOL 4.5 4.5 - - 0.1 - 0.1 - 0.1 V 0.02 Low Level Output Voltage CMOS Loads -6 -7.8 6 - - 0.1 - 0.1 - 0.1 V II VCC or GND - - - - - - - - V 4.5 - - 0.26 - 0.33 - 0.4 V 7.8 Input Leakage Current 6 6 - - 0.26 - 0.33 - 0.4 V - 6 - - ±0.1 - ±1 - ±1 µA 3 CD74HC374 CD74HC374, CD74HCT374 CD74HCT374, CD74HC574 CD74HC574, CD74HCT574 CD74HCT574 DC Electrical Specifications (Continued) TEST CONDITIONS PARAMETER Quiescent Device Current 25oC -40oC TO 85oC -55oC TO 125oC SYMBOL VI (V) IO (mA) VCC (V) ICC VCC or GND 0 6 - - 8 - 80 - 160 µA - 6 - - ±0.5 - ±5.0 - ±10 µA Three- State Leakage VIL or VIH VO = VCC Current or GND MIN TYP MAX MIN MAX MIN MAX UNITS HCT TYPES High Level Input Voltage VIH - - 4.5 to 5.5 2 - - 2 - 2 - V Low Level Input Voltage VIL - - 4.5 to 5.5 - - 0.8 - 0.8 - 0.8 V High Level Output Voltage CMOS Loads VOH VIH or VIL -0.02 4.5 4.4 - - 4.4 - 4.4 - V -6 4.5 3.98 - - 3.84 - 3.7 - V 0.02 4.5 - - 0.1 - 0.1 - 0.1 V 6 4.5 - - 0.26 - 0.33 - 0.4 V ±0.1 - ±1 - ±1 µA High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads VOL VIH or VIL Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current II VCC and GND 0 5.5 - ICC VCC or GND 0 5.5 - - 8 - 80 - 160 µA - 6 - - ±0.5 - ±5.0 - ±10 µA - 4.5 to 5.5 - 100 360 - 450 - 490 µA Three- State Leakage VIL or VIH VO = VCC Current or GND Additional Quiescent Device Current Per Input Pin: 1 Unit Load ICC VCC -2.1 NOTE: For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA. HCT Input Loading Table UNIT LOADS INPUT HCT374 HCT374 HCT574 HCT574 D0 - D7 0.3 0.4 CP 0.9 0.75 OE 1.3 0.6 NOTE: Unit load is ICC limit specific in DC Electrical Specifications Table, e.g., 360µA max. at 25oC. 4 CD74HC374 CD74HC374, CD74HCT374 CD74HCT374, CD74HC574 CD74HC574, CD74HCT574 CD74HCT574 Prerequisite for Switching Specifications 25oC PARAMETER -40oC TO 85oC -55oC TO 125oC SYMBOL VCC (V) MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS fMAX 2 6 - - 5 - - 4 - - MHz 4.5 30 - - 25 - - 20 - - MHz 6 35 - - 29 - - 23 - - MHz 2 80 - - 100 - - 120 - - ns 4.5 16 - - 20 - - 24 - - ns 6 14 - - 17 - - 20 - - ns 2 60 - - 75 - - 90 - - ns 4.5 12 - - 15 - - 18 - - ns 6 10 - - 13 - - 15 - - ns 2 5 - - 5 - - 5 - - ns 4.5 5 - - 5 - - 5 - - ns 6 5 - - 5 - - 5 - - ns fMAX 4.5 30 - - 25 - - 20 - - MHz Clock Pulse Width tW 4.5 16 - - 20 - - 24 - - ns Setup Time Data to Clock tSU 4.5 12 - - 15 - - 18 - - ns Hold Time Data to Clock tH 4.5 5 - - 5 - - 5 - - ns HC TYPES Maximum Clock Frequency Clock Pulse Width Setup Time Data to Clock Hold Time Data to Clock tW tSU tH HCT TYPES Maximum Clock Frequency Switching Specifications CL = 50pF, Input tr, tf = 6ns SYMBOL TEST CONDITIONS tPLH, tPHL -40oC TO 85oC 25oC -55oC TO 125oC CL = 50pF VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS 2 - - 165 - 205 - 250 ns 4.5 - - 33 - 41 - 50 ns CL = 15pF 5 - 15 - - - - - ns CL = 50pF PARAMETER 6 - - 28 - 35 - 43 ns CL = 50pF 2 - - 135 - 170 - 205 ns 4.5 - - 27 - 34 - 41 ns CL = 15pF 5 - 11 - - - - - ns CL = 50pF 6 - - 23 - 29 - 35 ns HC TYPES Propagation Delay Clock to Output Output Disable to Q tPLZ, tPHZ 5 CD74HC374 CD74HC374, CD74HCT374 CD74HCT374, CD74HC574 CD74HC574, CD74HCT574 CD74HCT574 Switching Specifications CL = 50pF, Input tr, tf = 6ns (Continued) -40oC TO 85oC 25oC -55oC TO 125oC PARAMETER SYMBOL TEST CONDITIONS VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS Output Enable to Q tPZL, tPZH CL = 50pF 2 - - 150 - 190 - 225 ns 4.5 - - 30 - 38 - 45 ns CL = 15pF 5 - 12 - - - - - ns CL = 50pF 6 - - 26 - 33 - 38 ns fMAX CL = 15pF 5 - 60 - - - - - MHz tTHL, tTLH CL = 50pF 2 - - 60 - 75 - 90 ns 4.5 - - 12 - 15 - 18 ns 6 - - 10 - 13 - 15 ns Maximum Clock Frequency Output Transition Time Input Capacitance CI CL = 50pF - 10 - 10 - 10 - 10 pF Three-State Output Capacitance CO - - 20 - 20 - 20 - 20 pF Power Dissipation Capacitance (Notes 4, 5) CPD CL = 15pF 5 - 39 - - - - - pF CL = 50pF 4.5 - - 33 - 41 - 50 ns CL = 15pF 5 - 15 - - - - - ns CL = 50pF 4.5 - - 28 - 35 - 42 ns CL = 15pF 5 - 11 - - - - - ns CL = 50pF 4.5 - - 30 - 38 - 45 ns CL = 15pF 5 - 12 - - - - - ns fMAX CL = 15pF 5 - 60 - - - - - MHz tTLH, tTHL CL = 50pF 4.5 - - 12 - 15 - 18 ns Input Capacitance CI CL = 50pF - 10 - 10 - 10 - 10 pF Three-State Output Capacitance CO - - 20 - 20 - 20 - 20 pF Power Dissipation Capacitance (Notes 4, 5) CPD CL = 15pF 5 - 47 - - - - - pF HCT TYPES Propagation Delay tPHL, tPLH Clock to Output Output Disable to Q Output Enable to Q Maximum Clock Frequency Output Transition Time tPLZ, tPHZ tPZL, tPZH NOTES: 4. CPD is used to determine the dynamic power consumption, per package. 5. PD = CPD VCC2 fi + VCC2 fO CL where fi = Input Frequency, fO = Output Frequency, CL = Output Load Capacitance, VCC = Supply Voltage. 6 CD74HC374 CD74HC374, CD74HCT374 CD74HCT374, CD74HC574 CD74HC574, CD74HCT574 CD74HCT574 Test Circuits and Waveforms tWL + tWH = tfCL trCL 50% 10% 10% tf = 6ns tr = 6ns tTLH 90% INVERTING OUTPUT tPHL FIGURE 3. HC TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC tPLH FIGURE 4. HCT TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC trCL tfCL VCC tfCL GND 1.3V 0.3V GND tH(H) tH(L) VCC DATA INPUT 3V 2.7V CLOCK INPUT 50% tH(H) tTLH 1.3V 10% tPLH 10% GND tTHL 90% 50% 10% 90% 3V 2.7V 1.3V 0.3V GND tTHL trCL tWH FIGURE 2. HCT CLOCK PULSE RISE AND FALL TIMES AND PULSE WIDTH INPUT INVERTING OUTPUT GND NOTE: Outputs should be switching from 10% VCC to 90% VCC in accordance with device truth table. For fMAX, input duty cycle = 50%. VCC 90% 50% 10% 1.3V 1.3V tWL tf = 6ns tPHL 1.3V 0.3V tWH FIGURE 1. HC CLOCK PULSE RISE AND FALL TIMES AND PULSE WIDTH INPUT 2.7V 0.3V GND tr = 6ns DATA INPUT 50% tH(L) 3V 1.3V 1.3V 1.3V GND tSU(H) tSU(H) tSU(L) tTLH 90% OUTPUT tTHL 90% 50% 10% tTLH 90% 1.3V OUTPUT tREM 3V SET, RESET OR PRESET GND tTHL 1.3V 10% FIGURE 5. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME, AND PROPAGATION DELAY TIMES FOR EDGE TRIGGERED SEQUENTIAL LOGIC CIRCUITS tPHL 1.3V GND IC CL 50pF GND 90% tPLH 50% IC tSU(L) tPHL tPLH I fCL 3V NOTE: Outputs should be switching from 10% VCC to 90% VCC in accordance with device truth table. For fMAX, input duty cycle = 50%. tREM VCC SET, RESET OR PRESET tfCL = 6ns CLOCK 50% 50% tWL CLOCK INPUT tWL + tWH = trCL = 6ns VCC 90% CLOCK I fCL CL 50pF FIGURE 6. HCT SETUP TIMES, HOLD TIMES, REMOVAL TIME, AND PROPAGATION DELAY TIMES FOR EDGE TRIGGERED SEQUENTIAL LOGIC CIRCUITS 7 CD74HC374 CD74HC374, CD74HCT374 CD74HCT374, CD74HC574 CD74HC574, CD74HCT574 CD74HCT574 Test Circuits and Waveforms 6ns (Continued) 6ns OUTPUT DISABLE 90% 50% 10% OUTPUTS ENABLED 2.7 1.3 OUTPUT HIGH TO OFF 50% OUTPUTS DISABLED FIGURE 7. HC THREE-STATE PROPAGATION DELAY WAVEFORM OTHER INPUTS TIED HIGH OR LOW OUTPUT DISABLE IC WITH THREESTATE OUTPUT GND 1.3V tPZH 90% OUTPUTS ENABLED OUTPUTS ENABLED 0.3 10% tPHZ tPZH 90% 3V tPZL tPLZ OUTPUT LOW TO OFF 50% OUTPUT HIGH TO OFF 6ns GND 10% tPHZ tf OUTPUT DISABLE tPZL tPLZ OUTPUT LOW TO OFF 6ns tr VCC 1.3V OUTPUTS DISABLED OUTPUTS ENABLED FIGURE 8. HCT THREE-STATE PROPAGATION DELAY WAVEFORM OUTPUT RL = 1k CL 50pF VCC FOR tPLZ AND tPZL GND FOR tPHZ AND tPZH NOTE: Open drain waveforms tPLZ and tPZL are the same as those for three-state shown on the left. The test circuit is Output RL = 1k to VCC, CL = 50pF. FIGURE 9. HC AND HCT THREE-STATE PROPAGATION DELAY TEST CIRCUIT 8 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. 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