CDCLVD110A SCAS841C QFN32 CDCLVD110 CDCLVD110ARHBR CDCLVD110ARHBRG4 - Datasheet Archive

 

www.ti.com SCAS841C ­ FEBRUARY 2007 ­ REVISED NOVEMBER 2009 PROGRAMMABLE LOW-VOLTAGE 1:10 LVDS CLOCK DRIVER Check for

 

CDCLVD110A CDCLVD110A www.ti.com SCAS841C SCAS841C ­ FEBRUARY 2007 ­ REVISED NOVEMBER 2009 PROGRAMMABLE LOW-VOLTAGE 1:10 LVDS CLOCK DRIVER Check for Samples: CDCLVD110A CDCLVD110A FEATURES 1 · 2 · · · · · · · · Low-Output Skew 2000 V Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS MIN VDD VIC Receiver common-mode input voltage TA Operating free-air temperature NOM MAX UNIT 2.375 Supply voltage 2.5 2.625 V 0.5|VID| VDD ­ 0.5|VID| V ­40 85 °C Submit Documentation Feedback Copyright © 2007­2009, Texas Instruments Incorporated Product Folder Link(s): CDCLVD110A CDCLVD110A 3 CDCLVD110A CDCLVD110A SCAS841C SCAS841C ­ FEBRUARY 2007 ­ REVISED NOVEMBER 2009 www.ti.com ELECTRICAL CHARACTERISTICS over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 250 450 600 mV 50 mV DRIVER |VOD| Differential output voltage VOD VOD magnitude change RL = 100 VOS Offset voltage VOS VOS magnitude change IOS Output short circuit current VBB Reference output voltage VDD = 2.5 V, IBB = ­100 A CO Output capacitance VO = VDD or GND ­40°C to 85°C 0.95 1.2 V 350 VO = 0 V 1.45 mV ­20 |VOD| = 0 V mA 20 1.15 1.25 1.35 V 3 pF RECEIVER VIDH Input threshold high VIDL Input threshold low |VID| Input differential voltage IIH 100 mV ­100 IIL Input current, CLK0/CLK0, CLK1/CLK1 VI = VDD CI Input capacitance mV 200 mV VI = VDD or GND ­5 VI = 0 V A 5 3 pF SUPPLY CURRENT IDD Supply current All outputs enabled and loaded, RL = 100 , f = 100 MHz 100 110 All outputs enabled and loaded, RL = 100 , f = 800 MHz Full loaded 150 160 Outputs enabled, no output load, f = 0 Hz All outputs 3-state by control logic, f = 0 Hz mA 35 3-State IDDZ No load 35 JITTER CHARACTERISTICS characterized with CDCLVD110 CDCLVD110 performance EVM, VDD = 3.3 V, OUTPUTS NOT UNDER TEST are terminated to 50 PARAMETER tjitterLVDS 4 Additive phase jitter from input to LVDS output Q3 and Q3 TEST CONDITIONS MIN TYP 12 kHz to 5 MHz, fout = 30.72 MHz 281 12 kHz to 20 MHz, fout = 125 MHz 111 Submit Documentation Feedback MAX UNIT fs rms Copyright © 2007­2009, Texas Instruments Incorporated Product Folder Link(s): CDCLVD110A CDCLVD110A CDCLVD110A CDCLVD110A www.ti.com SCAS841C SCAS841C ­ FEBRUARY 2007 ­ REVISED NOVEMBER 2009 LVDS - SWITCHING CHARACTERISTICS over recommended operating free-air temperature range, VDD = 2.5 V ±5% FROM (INPUT) tPLH tPHL TO (OUTPUT) CLK0, CLK0 CLK1, CLK1 PARAMETER MAX Qn, Qn 2 3 ns Qn, Qn 2 3 ns CLK0, CLK0 CLK1, CLK1 Propagation delay high-to-low TYP CLK0, CLK0 CLK1, CLK1 Propagation delay low-to-high MIN Qn, Qn tduty Duty cycle tsk(o) Output skew Any Qn, Qn tsk(p) Pulse skew Any Qn, Qn 50 ps tsk(pp) Part-to-part skew Any Qn, Qn 600 ps tr Output rise time, 20% to 80%, RL = 100 , CL = 5 pF Any Qn, Qn 350 ps tf Output fall time, 20% to 80%, RL = 100 , CL = 5 pF Any Qn, Qn 350 ps fclk Max input frequency CLK0, CLK0 CLK1, CLK1 45% UNIT 55% 30 Any Qn, Qn ps 900 1100 MHz CONTROL REGISTER CHARACTERISTICS over recommended operating free-air temperature range, VDD = 2.5 V ±5% (unless otherwise noted) PARAMETER fMAX TYP 150 Setup time, clock to SI th MIN 100 Maximum frequency of shift register tsu TEST CONDITIONS MAX UNIT MHz 2 ns Hold time, clock to SI 1.5 ns tremoval Removal time, enable to clock 1.5 ns tstartup Startup time after disable through SI 1.0 s tw Clock pulse width, minimum VIH Logic input high VDD = 2.5 V VIL Logic input low VDD = 2.5 V IIH IIL Input current, CK pin Input current, SI and EN pins Input current, CK pin Input current, SI and EN pins 3 VI = VDD VI = GND ns 2 V 0.8 ­5 5 10 ­30 ­10 30 ­5 5 Submit Documentation Feedback Copyright © 2007­2009, Texas Instruments Incorporated Product Folder Link(s): CDCLVD110A CDCLVD110A V A A 5 CDCLVD110A CDCLVD110A SCAS841C SCAS841C ­ FEBRUARY 2007 ­ REVISED NOVEMBER 2009 www.ti.com SPECIFICATION OF CONTROL REGISTER The CDCLVD110A CDCLVD110A has an 11-bit, serial-in shift register and an 11-bit control register. The control Register enables/disables each output clock, and selects either CLK0 or CLK1 as the input clock. The CDCLVD110A CDCLVD110A has two modes of operation: Programmable Mode (EN=1) The shift register uses a serial input (SI) and a clock input (CK). Once the shift register is loaded with 11 clock pulses, the 12th clock pulse loads the control register. The first bit (bit 0) on SI enables the Q9-Q9 output pair, and the 10th bit (bit 9) enables the Q0-Q0 pair. The 11th bit (bit 10) on SI selects either CLK0 or CLK1 as the input clock; a bit value of 0 selects CLK0, whereas a bit value of 1 selects CLK1. To restart the control register configuration, a reset of the state machine must be done with a clock pulse on CK (shift register clock input) and EN set to low. The control register can be configured only once after each reset. Standard Mode (EN=0) In this mode, the CDCLVD110A CDCLVD110A is not programmable and all the clock outputs are enabled. The clock input (CLK0 or CLK1) is selected with the SI pin, as is shown in the table entitled control register. STATE-MACHINE INPUTS EN SI CK OUTPUT L L X All outputs enabled, CLK0 selected, control register disabled, default state L H X All outputs enabled, CLK1 selected, control register disabled H L First stage stores L, other stage stores data of previous stage H H First stage stores H, other stage stores data of previous stage L X Reset of state machine, shift and control registers CONTROL REGISTER BIT 10 BITS [0-9] QN[0-9] CLK0 L H H H CLK1 X L Outputs disabled SERIAL INPUT (SI) SEQUENCE BIT 10 BIT 9 BIT 8 CLK_SEL Q0 Q1 BIT 7 Q2 TRUTH TABLE FOR CONTROL LOGIC CK EN SI L L L L L L L L L L L H L L H L L H All outputs enabled 6 BIT 6 Q3 CLK0 L H Open X X X BIT 5 Q4 CLK0 H L Open X X X BIT 4 Q5 BIT 3 Q6 CLK1 X X X L H Open X = Don't care Submit Documentation Feedback BIT 2 Q7 CLK1 X X X H L Open BIT 1 Q8 Q(0-9) L H L L H L BIT 0 Q9 Q(0-9) H L H H L H Copyright © 2007­2009, Texas Instruments Incorporated Product Folder Link(s): CDCLVD110A CDCLVD110A CDCLVD110A CDCLVD110A www.ti.com SCAS841C SCAS841C ­ FEBRUARY 2007 ­ REVISED NOVEMBER 2009 APPLICATION INFORMATION Fall-Safe Information For VDD = 0 V (power-down mode) the CDCLVD110A CDCLVD110A has fail-safe input and output pins. In power-on mode, fail-safe biasing at input pins can be accomplished with a 10-k pullup resistor from CLK0/CLK1 to VDD and a 10-k pulldown resistor from CLK0/CLK1 to GND. LVDS Receiver Input Termination The LVDS receiver inputs require 100- termination resistors placed as close as possible across the input pins. Control Inputs Termination No external termination is required. The CK control input has an internal 120-k pullup resistor, while the SI­ and EN­control inputs each have an internal 120-k pulldown resistor. If the control pins are left open per the default, all outputs are enabled, CLK0, CLK0 is selected, and the control register is disabled. Submit Documentation Feedback Copyright © 2007­2009, Texas Instruments Incorporated Product Folder Link(s): CDCLVD110A CDCLVD110A 7 CDCLVD110A CDCLVD110A SCAS841C SCAS841C ­ FEBRUARY 2007 ­ REVISED NOVEMBER 2009 www.ti.com PARAMETER MEASUREMENT INFORMATION A. Output skew, tsk(o), is calculated as the greater of: ­ The difference between the fastest and the slowest tPLHn (n = 1, 2,.10) ­ The difference between the fastest and the slowest tPHLn (n = 1, 2,.10) B. Part-to-part skew, tsk(pp), is calculated as the greater of: ­ The difference between the fastest and the slowest tPLHn (n = 1, 2,.10) across multiple devices ­ The difference between the fastest and the slowest tPHLn (n = 1, 2,.10) across multiple devices C. Pulse skew, tsk(p), is calculated as the magnitude of the absolute time difference between the high-to-low (tPHL) and the low-to-high (tPLH) propagation delays when a single switching input causes one or more outputs to switch, tsk(p) = | tPHL ­ tPLH |. Pulse skew is sometimes referred to as pulse-width distortion or duty-cycle skew. Figure 1. Waveforms for Calculation of tsk(o) and tsk(pp) 8 Submit Documentation Feedback Copyright © 2007­2009, Texas Instruments Incorporated Product Folder Link(s): CDCLVD110A CDCLVD110A CDCLVD110A CDCLVD110A www.ti.com SCAS841C SCAS841C ­ FEBRUARY 2007 ­ REVISED NOVEMBER 2009 PARAMETER MEASUREMENT INFORMATION (continued) Figure 2. Test Criteria for fclk, Duty Cycle, tr, tf, VOD Spacer REVISION HISTORY Changes from Original (February 2007) to Revision A · Page Changed Pinout Package title From: TQFP PACKAGE and QFN PACKAGE To: LQFP PACKAGE and QFN PACKAGE . 1 Changes from Revision A (January 2008) to Revision B Page · Changed Feature From: Available in 32-Pin LQFP Package To: Available in 32-Pin LQFP and QFN Package . 1 · Added Applications . 1 Changes from Revision B (October 2008) to Revision C Page · Added PowerPAD information to the Pinout Package . 1 · Added PowerPAD information to the PIn FUNCTIONS table . 3 Submit Documentation Feedback Copyright © 2007­2009, Texas Instruments Incorporated Product Folder Link(s): CDCLVD110A CDCLVD110A 9 PACKAGE OPTION ADDENDUM www.ti.com 30-Oct-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty CDCLVD110ARHBR CDCLVD110ARHBR ACTIVE QFN RHB 32 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR CDCLVD110ARHBRG4 CDCLVD110ARHBRG4 ACTIVE QFN RHB 32 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR CDCLVD110ARHBT CDCLVD110ARHBT ACTIVE QFN RHB 32 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR CDCLVD110ARHBTG4 CDCLVD110ARHBTG4 ACTIVE QFN RHB 32 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR CDCLVD110AVF CDCLVD110AVF ACTIVE LQFP VF 32 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CDCLVD110AVFG4 CDCLVD110AVFG4 ACTIVE LQFP VF 32 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CDCLVD110AVFR CDCLVD110AVFR ACTIVE LQFP VF 32 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CDCLVD110AVFRG4 CDCLVD110AVFRG4 ACTIVE LQFP VF 32 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 30-Oct-2009 TAPE AND REEL INFORMATION *All dimensions are nominal Device CDCLVD110ARHBR CDCLVD110ARHBR Package Package Pins Type Drawing QFN RHB 32 CDCLVD110ARHBT CDCLVD110ARHBT QFN RHB CDCLVD110AVFR CDCLVD110AVFR LQFP VF SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 8.0 12.0 Q2 3000 330.0 12.4 5.3 5.3 1.5 32 250 330.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2 32 1000 330.0 16.4 9.6 9.6 1.9 12.0 16.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 30-Oct-2009 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CDCLVD110ARHBR CDCLVD110ARHBR QFN RHB 32 3000 340.5 333.0 20.6 CDCLVD110ARHBT CDCLVD110ARHBT QFN RHB 32 250 340.5 333.0 20.6 CDCLVD110AVFR CDCLVD110AVFR LQFP VF 32 1000 333.2 345.9 28.6 Pack Materials-Page 2 MECHANICAL DATA MTQF002B MTQF002B ­ JANUARY 1995 ­ REVISED MAY 2000 VF (S-PQFP-G32 S-PQFP-G32) PLASTIC QUAD FLATPACK 0,45 0,25 0,80 24 0,20 M 17 25 16 32 9 0,13 NOM 1 8 5,60 TYP 7,20 SQ 6,80 9,20 SQ 8,80 Gage Plane 0,05 MIN 0,25 0°­ 7° 1,45 1,35 Seating Plane 0,75 0,45 0,10 1,60 MAX 4040172/D 4040172/D 04/00 NOTES: A. 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