74ACT11873 SCAS096 - Datasheet Archive

 

DUAL 4-BIT D-TYPE LATCH WITH 3­STATE OUTPUTS SCAS096 ­ FEBRUARY 1990 ­ REVISED APRIL 1993 · · ·

 

74ACT11873 74ACT11873 DUAL 4-BIT D-TYPE LATCH WITH 3­STATE OUTPUTS SCAS096 SCAS096 ­ FEBRUARY 1990 ­ REVISED APRIL 1993 · · · · · · · · Inputs Are TTL-Voltage Compatible 3-State Buffer-Type Outputs Drive Bus Lines Directly Bus-Structured Pinout Flow-Through Architecture to Optimize PCB Layout Center-Pin VCC and GND Configurations to Minimize High-Speed Switching Noise EPIC (Enhanced-Performance Implanted CMOS) 1-mm Process 500-mA Typical Latch-Up Immunity at 125°C Package Options Include Plastic SmallOutline Packages and Standard Plastic 300-mil DIPs DW OR NT PACKAGE (TOP VIEW) 1C 1Q1 1Q2 1Q3 1Q4 GND GND GND GND 2Q1 2Q2 2Q3 2Q4 2C t 1 28 2 27 3 26 4 25 5 24 6 23 7 22 8 21 9 20 10 19 11 18 12 17 13 16 14 15 1OC 1CLR 1D1 1D2 1D3 1D4 VCC VCC 2D1 2D2 2D3 2D4 2CLR 2OC description These dual 4-bit registers feature 3-state outputs designed specifically for bus driving. This makes these devices particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The dual 4-bit latch is transparent D-type. When the latch enable input (1C or 2C) is high, the (Q) outputs will follow the data (D) inputs in true form, according to the function table. When the latch enable input is taken low, the outputs will be latched. When CLR goes low, the Q outputs go low independently of enable C. The outputs are in a high-impedance state when OC (output control) is at a high logic level. The 74ACT11873 74ACT11873 is characterized for operation from ­ 40°C to 85°C. FUNCTION TABLE INPUTS OC L L L L H CLR L H H H X C X H H L X D X H L X X OUTPUT Q L H L Qo Z EPIC is a trademark of Texas Instruments Incorporated. Copyright © 1993, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 1 74ACT11873 74ACT11873 DUAL 4-BIT D-TYPE LATCH WITH 3­STATE OUTPUTS SCAS096 SCAS096 ­ FEBRUARY 1990 ­ REVISED APRIL 1993 logic symbol logic diagram (positive logic) each quad latch 1OE 1CLK 1CLR 1D1 1D2 1D3 1D4 2OE 2CLK 2CLR 2D1 2D2 2D3 2D4 28 1 27 23 22 EN OE C1 CLK R 1D 2 3 21 4 20 5 15 14 16 20 19 1Q1 CLR 1Q2 R 1Q3 1Q4 Q1 C1 D1 1D EN R C1 C1 D2 R 1D 10 11 18 12 17 13 Q2 1D 2Q1 R 2Q2 2Q3 2Q4 Q3 C1 D3 This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. 1D R Q4 C1 D4 1D absolute maximum ratings over operating free-air temperature range (unless otherwise noted)} Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ­ 0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ­ 0.5 V to VCC + 0.5 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ­ 0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 200 mA Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ­ 65°C to 150°C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2 POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 74ACT11873 74ACT11873 DUAL 4-BIT D-TYPE LATCH WITH 3­STATE OUTPUTS SCAS096 SCAS096 ­ FEBRUARY 1990 ­ REVISED APRIL 1993 recommended operating conditions MIN MAX 4.5 5.5 VCC VIH Supply voltage VIL VI Low-level input voltage Input voltage 0 VO IOH Output voltage 0 IOL Dt/Dv Low-level output current TA Operating free-air temperature High-level input voltage 2 UNIT V V 0.8 VCC VCC V ­ 24 High-level output current V mA V 24 mA 0 10 ns/V ­ 40 Input transition rise or fall rate 85 °C electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC 4.5 V TA = 25°C TYP MAX MIN 5.4 3.8 5.5 V 4.94 4.8 V IOH = ­ 75 mA 5.5 V IOL = 50 mA VOL UNIT 5.4 3.94 MAX 4.4 4.5 V IOH = ­ 24 mA 4.4 5.5 V IOH = ­ 50 mA VOH MIN 4.5 V 0.1 0.1 5.5 V 0.1 0.1 4.5 V 0.36 0.44 5.5 V 0.36 0.44 IOL = 24 mA 3.85 V IOL = 75 mA VO = VCC or GND 5.5 V 5.5 V ± 0.5 ±5 5.5 V ± 0.1 ±1 ICC VI = VCC or GND VI = VCC or GND, 5.5 V 8 80 mA mA mA DICC One input at 3.4 V, , Other inputs at GND or VCC 5.5 55V 0.9 09 1 mA Ci VI = VCC or GND VO = VCC or GND IOZ II IO = 0 5V 1.65 4.5 pF Co 5V 13.5 Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms. This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V to VCC. pF timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 1) TA = 25°C MIN MAX tw Pulse duration tsu Setup time before C th Hold time after C MIN CLR low 5 5 C high 5 5 Data high 6 6 Data low 3 3 Data high 0 0 Data low 0 0 POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 MAX UNIT ns ns ns 3 74ACT11873 74ACT11873 DUAL 4-BIT D-TYPE LATCH WITH 3­STATE OUTPUTS SCAS096 SCAS096 ­ FEBRUARY 1990 ­ REVISED APRIL 1993 switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) tPLH tPHL D Q tPLH tPHL C Q CLR Q tPHL tPZH tPZL tPHZ tPLZ OC TA = 25°C TYP MAX MIN MAX 4.4 8.8 4.4 10 6.6 9.1 3 10.2 4.7 8.1 10 4.7 11.3 5.2 8.9 10.9 5.2 12.3 2.9 6.5 9 2.9 10 1.9 4.9 7.1 1.9 8 2.7 6.4 9.1 2.7 10.3 5.7 8 9.5 5.7 10.2 5.2 Q 7.2 3 Q OC MIN 7.8 9.1 5.2 9.8 UNIT ns ns ns ns ns operating characteristics, VCC = 5 V, TA = 25°C PARAMETER Cpd d 4 TEST CONDITIONS Power dissipation capacitance per latch Outputs enabled Outputs disabled POST OFFICE BOX 655303 CL = 50 pF f = 1 MHz pF, · DALLAS, TEXAS 75265 TYP 40 7 UNIT pF 74ACT11873 74ACT11873 DUAL 4-BIT D-TYPE LATCH WITH 3­STATE OUTPUTS SCAS096 SCAS096 ­ FEBRUARY 1990 ­ REVISED APRIL 1993 PARAMETER MEASUREMENT INFORMATION 2 X VCC S1 500 From Output Under Test TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open GND 500 CL = 50 pF (see Note A) S1 Open 2 x VCC GND LOAD CIRCUIT 3V Timing Input (see Note B) 3V High-Level Input 1.5 V 1.5 V 1.5 V 0V tsu Data Input 0 th tw 3V 3V 1.5 V 1.5 V Low-Level Input 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 1.5 V 1.5 V 3V 1.5 V VOH 50% 50% VOL tPLH tPHL VOH 50% 50% VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES 1.5 V 0 tPZL tPLZ tPHL tPLH Out-of-Phase Output 0 Output Control (Low-Level Enabling) 0 In-Phase Output 1.5 V VOLTAGE WAVEFORMS PULSE DURATION 3V Input (see Note B) 1.5 V VCC Output Waveform 1 S1 at 2 x VCC (see Note C) 50% 20% VOL tPZH Output Waveform 2 S1 at GND (see Note C) tPHZ 50% 80% VOH 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2.5 ns, tf 2.5 ns. C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. D. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 5 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof. Copyright © 1998, Texas Instruments Incorporated