SAF7118 SAF7118EH HBGA156 SAF7118H QFP160 DNC20 DNC10 VDDD13 VDDD12 VDDD11 - Datasheet Archive

 

Multistandard video decoder with adaptive comb filter and component video input Rev. 04 - 4 July 2008 Product data sheet 1.

 

SAF7118 SAF7118 Multistandard video decoder with adaptive comb filter and component video input Rev. 04 - 4 July 2008 Product data sheet 1. General description The SAF7118 SAF7118 is a video capture device that, due to its improved comb filter performance, is suitable for various applications such as in-car video reception, in-car entertainment or in-car navigation. The SAF7118 SAF7118 is a combination of a four-channel analog preprocessing circuit including source selection, anti-aliasing filter and Analog-to-Digital Converter (ADC) with succeeding decimation filters from 27 MHz to 13.5 MHz data rate. Each preprocessing channel comes with an automatic clamp and gain control. The SAF7118 SAF7118 combines a Clock Generation Circuit (CGC), a digital multistandard decoder containing two-dimensional chrominance/luminance separation by an adaptive comb filter and a high performance scaler, including variable horizontal and vertical up and downscaling and a brightness, contrast and saturation control circuit. It is a highly integrated circuit for desktop video and similar applications. The decoder is based on the principle of line-locked clock decoding and is able to decode the color of PAL, SECAM and NTSC signals into ITU 601 compatible color component values. The SAF7118 SAF7118 accepts CVBS or S-video (Y/C) as analog inputs from TV or VCR sources, including weak and distorted signals as well as baseband component signals Y-PB-PR or RGB. An expansion port (X port) for digital video (bidirectional half duplex, D1 compatible) is also supported to connect to MPEG or a video phone codec. At the so called image port (I port) the SAF7118 SAF7118 supports 8-bit or 16-bit wide output data with auxiliary reference data for interfacing to VGA controllers. The target application for the SAF7118 SAF7118 is to capture and scale video images, to be provided as a digital video stream through the image port of a VGA controller, for capture to system memory, or just to provide digital baseband video to any picture improvement processing. The SAF7118 SAF7118 also provides a means for capturing the serially coded data in the Vertical Blanking Interval (VBI) data. Two principal functions are available: 1. To capture raw video samples, after interpolation to the required output data rate, via the scaler 2. A versatile data slicer (data recovery) unit The SAF7118 SAF7118 also incorporates field-locked audio clock generation. This function ensures that there is always the same number of audio samples associated with a field, or a set of fields. This prevents the loss of synchronization between video and audio during capture or playback. All of the ADCs may be used to digitize a Vestigial Side Band (VSB) signal for subsequent decoding; a dedicated output port and a selectable VSB clock input is provided. SAF7118 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter The circuit is I2C-bus controlled (full write/read capability for all programming registers, bit rate up to 400 kbit/s). 2. Features 2.1 Video acquisition/clock I Up to sixteen analog CVBS, split as desired (all of the CVBS inputs optionally can be used to convert e.g. VSB signals) I Up to eight analog Y + C inputs, split as desired I Up to four analog component inputs, with embedded or separate sync, split as desired I Four on-chip anti-aliasing filters in front of the ADCs I Automatic Clamp Control (ACC) for CVBS, Y and C (or VSB) and component signals I Switchable white peak control I Four 9-bit low noise CMOS ADCs running at twice the oversampling rate (27 MHz) I Fully programmable static gain or Automatic Gain Control (AGC), matching to the particular signal properties I On-chip line-locked clock generation in accordance with "ITU 601" I Requires only one crystal (32.11 MHz or 24.576 MHz) for all standards I Horizontal and vertical sync detection 2.2 Video decoder I Digital Phase-Locked Loop (PLL) for synchronization and clock generation from all standards and non-standard video sources e.g. consumer grade VTR I Automatic detection of any supported color standard I Luminance and chrominance signal processing for PAL B, G, D, H, I and N, combination PAL N, PAL M, NTSC M, NTSC-Japan, NTSC 4.43 and SECAM I Adaptive 2/4-line comb filter for two dimensional chrominance/luminance separation, also with VTR signals N Increased luminance and chrominance bandwidth for all PAL and NTSC standards N Reduced cross color and cross luminance artefacts I PAL delay line for correcting PAL phase errors I Brightness Contrast Saturation (BCS) adjustment, separately for composite and baseband signals I User programmable sharpness control I Detection of copy-protected signals according to the Macrovision standard, indicating level of protection I Independent gain and offset adjustment for raw data path 2.3 Component video processing I I I I RGB component inputs Y-PB-PR component inputs Fast blanking between CVBS and synchronous component inputs Digital RGB to Y-CB-CR matrix SAF7118 SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 - 4 July 2008 2 of 175 SAF7118 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter 2.4 Video scaler I Horizontal and vertical downscaling and upscaling to randomly sized windows I Horizontal and vertical scaling range: variable zoom to 1/64 (icon) (it should be noted that the H and V zoom are restricted by the transfer data rates) I Anti-alias and accumulating filter for horizontal scaling I Vertical scaling with linear phase interpolation and accumulating filter for anti-aliasing (6-bit phase accuracy) I Horizontal phase correct up and downscaling for improved signal quality of scaled data, especially for compression and video phone applications, with 6-bit phase accuracy (1.2 ns step width) I Two independent programming sets for scaler part, to define two `ranges' per field or sequences over frames I Fieldwise switching between decoder part and expansion port (X port) input I Brightness, contrast and saturation controls for scaled outputs 2.5 VBI data decoder and slicer I Versatile VBI data decoder, slicer, clock regeneration and byte synchronization e.g. for World Standard Teletext (WST), North American Broadcast Text System (NABTS), closed caption, Wide Screen Signalling (WSS), etc. 2.6 Audio clock generation I Generation of a field-locked audio master clock to support a constant number of audio clocks per video field I Generation of an audio serial and left/right (channel) clock signal 2.7 Digital I/O interfaces I Real-time signal port (R port), inclusive continuous line-locked reference clock and real-time status information supporting RTC level 3.1 (refer to document "RTC Functional Specification" for details) I Bidirectional expansion port (X port) with half duplex functionality (D1), 8-bit Y-CB-CR: N Output from decoder part, real-time and unscaled N Input to scaler part, e.g. video from MPEG decoder (extension to 16-bit possible) I Video image port (I port) configurable for 8-bit data (extension to 16-bit possible) in master mode (own clock), or slave mode (external clock), with auxiliary timing and handshake signals I Discontinuous data streams supported I 32-word × 4-byte FIFO register for video output data I 28-word × 4-byte FIFO register for decoded VBI data output I Scaled 4 : 2 : 2, 4 : 1 : 1, 4 : 2 : 0, 4 : 1 : 0 Y-CB-CR output I Scaled 8-bit luminance only and raw CVBS data output I Sliced, decoded VBI data output 2.8 Miscellaneous I Power-on control I 5 V tolerant digital inputs and I/O ports SAF7118 SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 - 4 July 2008 3 of 175 SAF7118 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter I Software controlled power saving standby modes supported I Programming via serial I2C-bus, full read back ability by an external controller, bit rate up to 400 kbit/s I Boundary scan test circuit complies with the "IEEE Std. 1149.b1 - 1994". 3. Applications I I I I General industrial video applications In-car TV reception In-car entertainment In-car navigation platforms 4. Quick reference data Table 1. Quick reference data Symbol Parameter Min Typ Max Unit VDDD digital supply voltage 3.0 3.3 3.6 V VDDA analog supply voltage 3.1 3.3 3.5 V Tamb ambient temperature -40 - +85 °C - 1105 1350 mW Ptot(A+D) [1] Conditions total power dissipation analog and digital part component mode [1] 8-bit image port output mode, expansion port is 3-stated. 5. Ordering information Table 2. Ordering information Type number Package Name Description Version SAF7118EH SAF7118EH HBGA156 HBGA156 plastic thermal enhanced ball grid array package; 156 balls; body 15 × 15 × 1.15 mm; heatsink SOT807-1 SAF7118H SAF7118H QFP160 QFP160 plastic quad flat package; 160 leads (lead length 1.6 mm); body 28 × 28 × 3.4 mm; high stand-off height SOT322-2 SAF7118 SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 - 4 July 2008 4 of 175 xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x xxxxxxxxxxxxxx xxxxxxxxxx xxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x x AD PORT DNC0 to DNC20 DNC20 CONTROL SDA I2C-BUS REGISTER MAP ANALOG INPUT CONTROL RAW CB C CR COMB FILTER Y S ANALOG4 and ADC4 CHROMINANCE PROCESSING LUMINANCE PROCESSING S Y-CB-CR SAF7118 SAF7118 Y S S ICLK IDQ ITRDY ITRI VBI DATA SLICER SYNCHRONIZATION CB-CR CB-CR VIDEO/TEXT ARBITER Y-CB-CR, S POWER-ON CONTROL POWER SUPPLY VSSD VDDA Block diagram VIDEO CLOCK GPO CRYSTAL X PORT H PORT AUDIO CLOCK BOUNDARY SCAN VDD(xtal) LLC2 RTS0 RTCO XTALI XRDY XCLK AMXCLK ALRCLK TDO TMS XRH XTRI TRST VSS(xtal) VDDD LLC mbl751 RTS1 XTALO XTOUT XPD[7:0] XDQ AMCLK ASCLK TDI TCK HPD[7:0] XRV SAF7118 SAF7118 5 of 175 © NXP B.V. 2008. All rights reserved. VSSA Fig 1. IGP1 IGP0 IGPV IGPH IPD[7:0] S AOUT AGNDA TEXT FIFO RAW Y-CB-CR OUTPUT FORMATTER I PORT CR VIDEO FIFO COMPONENTS PROCESSING VERTICAL SCALING HORIZONTAL FINE (PHASE) SCALING ANALOG3 and ADC3 B FIR PREFILTER PRESCALER BCS SCALER AI31 AI32 AI33 AI34 AI3D G SCALER EVENT CONTROLLER Y CB DECODER OUTPUT CONTROL ANALOG2 and ADC2 FAST SWITCH DELAY R Multistandard video decoder with adaptive comb filter ANALOG1 and ADC1 AI21 AI22 AI23 AI24 AI2D Rev. 04 - 4 July 2008 AI11 AI12 AI13 AI14 AI1D AGND INT_A SECOND TASK I2C-BUS REGISTER MAP SCALER FSW AI41 AI42 AI43 AI44 AI4D SCL FIRST TASK I2C-BUS REGISTER MAP SCALER LINE FIFO BUFFER EXMCLR CE NXP Semiconductors CLKEXT 6. Block diagram SAF7118 SAF7118_4 Product data sheet RES ADP[8:0] SAF7118 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter 7. Pinning information 7.1 Pinning ball A1 index area A B C D E F G H J K L M N P 121 160 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1 120 SAF7118H SAF7118H 80 81 41 40 001aae326 SAF7118EH SAF7118EH 001aab338 Transparent top view Fig 2. Pin configuration (QFP160 QFP160) Table 3. Fig 3. Pin configuration (HBGA156 HBGA156) Pin allocation table Pin Symbol Pin Symbol Pin Symbol Pin Symbol A2 XTOUT A3 XTALO A4 VSS(xtal) A5 TDO A6 XRDY A7 XCLK A8 XPD0 A9 XPD2 A10 XPD4 A11 XPD6 A12 DNC5 A13 DNC3 B1 AI41 B2 DNC6 B3 VDD(xtal) B4 XTALI B5 TDI B6 TCK B7 XDQ B8 XPD1 B9 XPD3 B10 XPD5 B11 XTRI B12 DNC4 B13 DNC7 B14 DNC8 C1 VSSA4 C2 AGND C3 DNC9 C4 DNC10 DNC10 C5 VDDD13 VDDD13 C6 TRST C7 XRH C8 VDDD12 VDDD12 C9 VDDD11 VDDD11 C10 VDDD10 VDDD10 C11 XPD7 C12 DNC11 DNC11 C13 DNC12 DNC12 C14 DNC2 D1 AI43 D2 AI42 D3 AI4D D4 VDDA4 D5 VSSD13 VSSD13 D6 TMS D7 VSSD12 VSSD12 D8 XRV D9 VSSD11 VSSD11 D10 VSSD10 VSSD10 D11 VSSD9 D12 VDDD9 D13 DNC1 D14 HPD0 E1 E2 E3 E4 E11 HPD1 E12 HPD3 F2 AI31 VSSA3 AI44 E13 HPD2 E14 HPD4 F1 F3 F4 F11 VSSD8 F12 VDDD8 G2 AI33 VDDA3 AI3D VDDA4A F13 HPD5 F14 HPD6 G1 G3 G4 G11 VSSD7 G12 IPD1 H2 AI22 AI21 AI34 AI32 G13 HPD7 G14 IPD0 H1 H3 H4 H11 IPD2 VSSA2 VDDA2 SAF7118 SAF7118_4 Product data sheet AI2D VDDA3A AI23 H12 VDDD7 © NXP B.V. 2008. All rights reserved. Rev. 04 - 4 July 2008 6 of 175 SAF7118 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter Table 3. Pin Pin allocation table .continued Pin Symbol Pin Symbol H13 IPD4 Symbol H14 IPD3 Pin Symbol J1 VDDA2A J2 AI11 J3 AI24 J4 VSSA1 J11 VSSD6 J12 VDDD6 J13 IPD6 J14 IPD5 K1 AI12 K2 AI13 K3 AI1D K4 VDDA1 K11 IPD7 K12 IGPH K13 IGP1 K14 IGPV L1 VDDA1A L2 AGNDA L3 AI14 L4 VSSD1 L5 VSSD2 L6 ADP6 L7 ADP3 L8 VSSD3 L9 VSSD4 L10 RTCO L11 VSSD5 L12 ITRI L13 IDQ L14 IGP0 M1 AOUT M2 VSSA0 M3 VDDA0 M4 VDDD1 M5 VDDD2 M6 ADP7 M7 ADP2 M8 VDDD3 M9 VDDD4 M10 RTS0 M11 VDDD5 M12 AMXCLK M13 FSW M14 ICLK N1 DNC13 DNC13 N2 DNC14 DNC14 N3 DNC15 DNC15 N4 CE N5 LLC2 N6 CLKEXT N7 ADP5 N8 ADP0 N9 SCL N10 RTS1 N11 ASCLK N12 ITRDY N13 DNC16 DNC16 N14 DNC17 DNC17 P2 DNC18 DNC18 P3 EXMCLR P4 LLC P5 RES P6 ADP8 P7 ADP4 P8 ADP1 P9 INT_A P10 SDA P11 AMCLK P12 ALRCLK P13 DNC0 7.2 Pin description Table 4. Symbol Pin description Type[1] Pin Description QFP160 QFP160 HBGA156 HBGA156 DNC6 1 B2 O do not connect, reserved for future extensions and for testing AI41 2 B1 I analog input 41 AGND 3 C2 P analog ground VSSA4 4 C1 P ground for analog inputs AI4x AI42 5 D2 I analog input 42 AI4D 6 D3 I differential input for ADC channel 4 (pins AI41 to AI44) AI43 7 D1 I analog input 43 VDDA4 8 D4 P analog supply voltage for analog inputs AI4x (3.3 V) VDDA4A 9 E2 P analog supply voltage for analog inputs AI4x (3.3 V) AI44 10 E1 I analog input 44 AI31 11 E3 I analog input 31 VSSA3 12 E4 P ground for analog inputs AI3x AI32 13 F2 I analog input 32 AI3D 14 F1 I differential input for ADC channel 3 (pins AI31 to AI34) AI33 15 F3 I analog input 33 VDDA3 16 F4 P analog supply voltage for analog inputs AI3x (3.3 V) VDDA3A 17 G2 P analog supply voltage for analog inputs AI3x (3.3 V) SAF7118 SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 - 4 July 2008 7 of 175 SAF7118 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter Table 4. Symbol Pin description .continued Type[1] Pin Description QFP160 QFP160 HBGA156 HBGA156 AI34 18 G1 I analog input 34 AI21 19 G4 I analog input 21 VSSA2 20 H3 P ground for analog inputs AI2x AI22 21 G3 I analog input 22 AI2D 22 H1 I differential input for ADC channel 2 (pins AI24 to AI21) AI23 23 H2 I analog input 23 VDDA2 24 H4 P analog supply voltage for analog inputs AI2x (3.3 V) VDDA2A 25 J1 P analog supply voltage for analog inputs AI2x (3.3 V) AI24 26 J3 I analog input 24 AI11 27 J2 I analog input 11 VSSA1 28 J4 P ground for analog inputs AI1x AI12 29 K1 I analog input 12 AI1D 30 K3 I differential input for ADC channel 1 (pins AI14 to AI11) AI13 31 K2 I analog input 13 VDDA1 32 K4 P analog supply voltage for analog inputs AI1x (3.3 V) VDDA1A 33 L1 P analog supply voltage for analog inputs AI1x (3.3 V) AI14 34 L3 I analog input 14 AGNDA 35 L2 P analog signal ground AOUT 36 M1 O analog test output (do not connect) VDDA0 37 M3 P analog supply voltage (3.3 V) for internal clock generation circuit VSSA0 38 M2 P ground for internal Clock Generation Circuit (CGC) DNC13 DNC13 39 N1 NC do not connect, reserved for future extensions and for testing DNC14 DNC14 40 N2 I/pu do not connect, reserved for future extensions and for testing DNC18 DNC18 41 P2 I/O do not connect, reserved for future extensions and for testing DNC15 DNC15 42 N3 I/pd do not connect, reserved for future extensions and for testing EXMCLR 43 P3 I/pd external mode clear (with internal pull-down) CE 44 N4 I/pu Chip Enable (CE) or reset input (with internal pull-up) VDDD1 45 M4 P digital supply voltage 1 (peripheral cells) LLC 46 P4 O line-locked system clock output (27 MHz nominal) VSSD1 47 L4 P digital ground 1 (peripheral cells) LLC2 48 N5 O line-locked 1/2 clock output (13.5 MHz nominal) RES 49 P5 O reset output (active LOW) VDDD2 50 M5 P digital supply voltage 2 (core) VSSD2 51 L5 P digital ground 2 (core; substrate connection) CLKEXT 52 N6 I external clock input intended for analog-to-digital conversion of VSB signals (36 MHz) ADP8 53 P6 O MSB of direct analog-to-digital converted output data (VSB) ADP7 54 M6 O MSB - 1 of direct analog-to-digital converted output data (VSB) ADP6 55 L6 O MSB - 2 of direct analog-to-digital converted output data (VSB) ADP5 56 N7 O MSB - 3 of direct analog-to-digital converted output data (VSB) SAF7118 SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 - 4 July 2008 8 of 175 SAF7118 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter Table 4. Symbol Pin description .continued Type[1] Pin Description QFP160 QFP160 HBGA156 HBGA156 ADP4 57 P7 O MSB - 4 of direct analog-to-digital converted output data (VSB) ADP3 58 L7 O MSB - 5 of direct analog-to-digital converted output data (VSB) VDDD3 59 M8 P digital supply voltage 3 (peripheral cells) ADP2 60 M7 O MSB - 6 of direct analog-to-digital converted output data (VSB) ADP1 61 P8 O MSB - 7 of direct analog-to-digital converted output data (VSB) ADP0 62 N8 O LSB of direct analog-to-digital converted output data (VSB) VSSD3 63 L8 P digital ground 3 (peripheral cells) INT_A 64 P9 O/od I2C-bus interrupt flag (LOW if any enabled status bit has changed) VDDD4 65 M9 P digital supply voltage 4 (core) SCL 66 N9 I(/O) serial clock input (I2C-bus) with inactive output path VSSD4 67 L9 P digital ground 4 (core) SDA 68 P10 I/O/od serial data input/output (I2C-bus) RTS0 69 M10 O real-time status or sync information, controlled by subaddresses 11h and 12h; see Section 10.2.18 and Section 10.2.19 RTS1 70 N10 O real-time status or sync information, controlled by subaddresses 11h and 12h; see Section 10.2.18 and Section 10.2.19 RTCO 71 L10 O/st/pd real-time control output; contains information about actual system clock frequency, field rate, odd/even sequence, decoder status, subcarrier frequency and phase and PAL sequence (see document "RTC Functional Description", available on request); the RTCO pin is enabled via I2C-bus bit RTCE; see Table 35[2][3] AMCLK 72 P11 O audio master clock output, up to 50 % of crystal clock VDDD5 73 M11 P digital supply voltage 5 (peripheral cells) ASCLK 74 N11 O audio serial clock output ALRCLK 75 P12 O/st/pd audio left/right clock output; can be strapped to supply via a 3.3 k resistor to indicate that the default 24.576 MHz crystal (pin ALRCLK = LOW; internal pull-down) has been replaced by a 32.110 MHz crystal (pin ALRCLK = HIGH)[2][4] AMXCLK 76 M12 I audio master external clock input ITRDY 77 N12 I/pu target ready input for image port data DNC0 78 P13 I/pu do not connect, reserved for future extensions and for testing: scan input DNC16 DNC16 79 N13 NC do not connect, reserved for future extensions and for testing DNC17 DNC17 80 N14 NC do not connect, reserved for future extensions and for testing DNC19 DNC19 81 - NC do not connect, reserved for future extensions and for testing DNC20 DNC20 82 - NC do not connect, reserved for future extensions and for testing FSW 83 M13 I/pd fast switch (blanking) with internal pull-down inserts component inputs into CVBS signal ICLK 84 M14 I/O clock output signal for image port, or optional asynchronous back-end clock input IDQ 85 L13 O output data qualifier for image port (optional: gated clock output) ITRI 86 L12 I(/O) image port output control signal, affects all input port pins inclusive ICLK, enable and active polarity is under software control (bits IPE in subaddress 87h); output path used for testing: scan output SAF7118 SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 - 4 July 2008 9 of 175 SAF7118 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter Table 4. Symbol Pin description .continued Type[1] Pin QFP160 QFP160 IGP0 87 L14 Description O general purpose output signal 0; image port (controlled by subaddresses 84h and 85h) HBGA156 HBGA156 VSSD5 88 L11 P digital ground 5 (peripheral cells) IGP1 89 K13 O general purpose output signal 1; image port (controlled by subaddresses 84h and 85h) IGPV 90 K14 O multi purpose vertical reference output signal; image port (controlled by subaddresses 84h and 85h) IGPH 91 K12 O multi purpose horizontal reference output signal; image port (controlled by subaddresses 84h and 85h) IPD7 92 K11 O MSB of image port data output IPD6 93 J13 O MSB - 1 of image port data output IPD5 94 J14 O MSB - 2 of image port data output VDDD6 95 J12 P digital supply voltage 6 (core) VSSD6 96 J11 P digital ground 6 (core) IPD4 97 H13 O MSB - 3 of image port data output IPD3 98 H14 O MSB - 4 of image port data output IPD2 99 H11 O MSB - 5 of image port data output IPD1 100 G12 O MSB - 6 of image port data output VDDD7 101 H12 P digital supply voltage 7 (peripheral cells) IPD0 102 G14 O LSB of image port data output HPD7 103 G13 I/O MSB of host port data I/O, extended CB-CR input for expansion port, extended CB-CR output for image port VSSD7 104 G11 P digital ground 7 (peripheral cells) HPD6 105 F14 I/O MSB - 1 of host port data I/O, extended CB-CR input for expansion port, extended CB-CR output for image port VDDD8 106 F12 P digital supply voltage 8 (core) HPD5 107 F13 I/O MSB - 2 of host port data I/O, extended CB-CR input for expansion port, extended CB-CR output for image port VSSD8 108 F11 P digital ground 8 (core) HPD4 109 E14 I/O MSB - 3 of host port data I/O, extended CB-CR input for expansion port, extended CB-CR output for image port HPD3 110 E12 I/O MSB - 4 of host port data I/O, extended CB-CR input for expansion port, extended CB-CR output for image port HPD2 111 E13 I/O MSB - 5 of host port data I/O, extended CB-CR input for expansion port, extended CB-CR output for image port HPD1 112 E11 I/O MSB - 6 of host port data I/O, extended CB-CR input for expansion port, extended CB-CR output for image port HPD0 113 D14 I/O LSB of host port data I/O, extended CB-CR input for expansion port, extended CB-CR output for image port VDDD9 114 D12 P digital supply voltage 9 (peripheral cells) DNC1 115 D13 I/pu do not connect, reserved for future extensions and for testing: scan input DNC2 116 C14 I/pu do not connect, reserved for future extensions and for testing: scan input SAF7118 SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 - 4 July 2008 10 of 175 SAF7118 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter Table 4. Symbol Pin description .continued Type[1] Pin Description QFP160 QFP160 HBGA156 HBGA156 DNC7 117 B13 NC do not connect, reserved for future extensions and for testing DNC8 118 B14 NC do not connect, reserved for future extensions and for testing DNC11 DNC11 119 C12 NC do not connect, reserved for future extensions and for testing DNC12 DNC12 120 C13 NC do not connect, reserved for future extensions and for testing DNC21 DNC21 121 - NC do not connect, reserved for future extensions and for testing DNC22 DNC22 122 - NC do not connect, reserved for future extensions and for testing DNC3 123 A13 I/pu do not connect, reserved for future extensions and for testing: scan input DNC4 124 B12 O do not connect, reserved for future extensions and for testing: scan output DNC5 125 A12 I/pu do not connect, reserved for future extensions and for testing: scan input XTRI 126 B11 I X port output control signal, affects all X port pins (XPD7 to XPD0, XRH, XRV, XDQ and XCLK), enable and active polarity is under software control (bits XPE in subaddress 83h) XPD7 127 C11 I/O MSB of expansion port data XPD6 128 A11 I/O MSB - 1 of expansion port data VSSD9 129 D11 P digital ground 9 (peripheral cells) XPD5 130 B10 I/O MSB - 2 of expansion port data XPD4 131 A10 I/O MSB - 3 of expansion port data VDDD10 VDDD10 132 C10 P digital supply voltage 10 (core) VSSD10 VSSD10 133 D10 P digital ground 10 (core) XPD3 134 B9 I/O MSB - 4 of expansion port data XPD2 135 A9 I/O MSB - 5 of expansion port data VDDD11 VDDD11 136 C9 P digital supply voltage 11 (peripheral cells) VSSD11 VSSD11 137 D9 P digital ground 11 (peripheral cells) XPD1 138 B8 I/O MSB - 6 of expansion port data XPD0 139 A8 I/O LSB of expansion port data XRV 140 D8 I/O vertical reference I/O expansion port XRH 141 C7 I/O horizontal reference I/O expansion port VDDD12 VDDD12 142 C8 P digital supply voltage 12 (core) XCLK 143 A7 I/O clock I/O expansion port XDQ 144 B7 I/O data qualifier for expansion port VSSD12 VSSD12 145 D7 P digital ground 12 (core) XRDY 146 A6 O task flag or ready signal from scaler, controlled by XRQT TRST 147 C6 I/pu test reset input (active LOW), for boundary scan test (with internal pull-up)[5][6][7] TCK 148 B6 I/pu test clock for boundary scan test[5] TMS 149 D6 I/pu test mode select input for boundary scan test or scan test[5] TDO 150 A5 O test data output for boundary scan test[5] VDDD13 VDDD13 151 C5 P digital supply voltage 13 (peripheral cells) SAF7118 SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 - 4 July 2008 11 of 175 SAF7118 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter Table 4. Symbol Pin description .continued Type[1] Pin Description QFP160 QFP160 HBGA156 HBGA156 TDI 152 B5 I/pu test data input for boundary scan test[5] VSSD13 VSSD13 153 D5 P digital ground 13 (peripheral cells) VSS(xtal) 154 A4 P ground for crystal oscillator XTALI 155 B4 I input terminal for 24.576 MHz (32.11 MHz) crystal oscillator or connection of external oscillator with TTL compatible square wave clock signal XTALO 156 A3 O 24.576 MHz (32.11 MHz) crystal oscillator output; not connected if TTL clock input of XTALI is used VDD(xtal) 157 B3 P supply voltage for crystal oscillator XTOUT 158 A2 O crystal oscillator output signal; auxiliary signal DNC9 159 C3 NC do not connect, reserved for future extensions and for testing DNC10 DNC10 160 C4 NC do not connect, reserved for future extensions and for testing [1] I = input, O = output, P = power, NC = not connected, st = strapping, pu = pull-up, pd = pull-down, od = open-drain. [2] Pin strapping is done by connecting the pin to the supply via a 3.3 k resistor. During the power-up reset sequence the corresponding pins are switched to input mode to read the strapping level. For the default setting no strapping resistor is necessary (internal pull-down). [3] Pin RTCO operates as I2C-bus slave address pin; RTCO = 0 slave address 42h/43h (default); RTCO = 1 slave address 40h/41h. [4] Pin ALRCLK = LOW for 24.576 MHz crystal (default); pin ALRCLK = HIGH for 32.110 MHz crystal. [5] In accordance with the "IEEE1149 IEEE1149.1" standard the pads TDI, TMS, TCK and TRST are input pads with an internal pull-up transistor and TDO is a 3-state output pad. [6] For board design without boundary scan implementation connect the TRST pin to ground. [7] This pin provides easy initialization of the Boundary Scan Test (BST) circuit. TRST can be used to force the Test Access Port (TAP) controller to the TEST_LOGIC_RESET state (normal operation) at once. SAF7118 SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 - 4 July 2008 12 of 175 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Pin[1] NXP Semiconductors SAF7118 SAF7118_4 Product data sheet Table 5. 8-bit/16-bit and alternative pin function configurations Symbol Input 8-bit input modes Output I/O configuration programming bits Y data input - D1 decoder output - - XCODE[92h[3]], XPE[1:0] 83h[1:0] + pin XTRI XCLK clock input - gated clock input decoder clock output - - XPE[1:0] 83h[1:0] + pin XTRI, XPCK[1:0] 83h[5:4], XCKS[92h[0]] XDQ data qualifier input - data qualifier output (HREF and VREF gate) - XDQ[92h[1]], XPE[1:0] 83h[1:0] + pin XTRI A6 (146) XRDY input ready output - active task A/B flag - - - XRQT[83h[2]], XPE[1:0] 83h[1:0] + pin XTRI C7 (141) XRH horizontal reference input - - decoder horizontal reference output - XDH[92h[2]], XPE[1:0] 83h[1:0] + pin XTRI D8 (140) XRV vertical reference input - - decoder vertical reference output - XDV[1:0] 92h[5:4], XPE[1:0] 83h[1:0] + pin XTRI B11 (126) XTRI output enable input - - - - - XPE[1:0] 83h[1:0] HPD7 to G13, F14, F13, HPD0 E14, E12, E13, E11, D14 (103, 105, 107, 109 to 113) CB-CR data input - - CB-CR scaler output - ICODE[93h[7]], ISWP[1:0] 85h[7:6], I8_16[93h[6]], IPE[1:0] 87h[1:0] + pin ITRI K11, J13, J14, H13, IPD7 to IPD0 H14, H11, G12, G14 (92 to 94, 97 to 99, 100, 102) - - - D1 scaler output Y scaler output - ICODE[93h[7]], ISWP[1:0] 85h[7:6], I8_16[93h[6]], IPE[1:0] 87h[1:0] + pin ITRI M14 (84) ICLK - - - clock output - clock input ICKS[1:0] 80h[1:0], IPE[1:0] 87h[1:0] + pin ITRI L13 (85) IDQ - - - data qualifier output - gated clock output ICKS[3:2] 80h[3:2], IDQP[85h[0]], IPE[1:0] 87h[1:0] + pin ITRI SAF7118 SAF7118 Alternative output functions Multistandard video decoder with adaptive comb filter 16-bit output modes (only for I2C-bus programming) B7 (144) 13 of 175 8-bit output modes A7 (143) © NXP B.V. 2008. All rights reserved. Alternative input functions XPD7 to D1 data C11, A11, B10, input A10, B9, A9, B8, A8 XPD0 (127, 128, 130, 131, 134, 135, 138, 139) Rev. 04 - 4 July 2008 16-bit input modes (only for I2C-bus programming) xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Pin[1] 8-bit/16-bit and alternative pin function configurations .continued Symbol Input Output 8-bit input modes 16-bit input modes (only for I2C-bus programming) Alternative input functions 8-bit output modes 16-bit output modes (only for I2C-bus programming) Alternative output functions NXP Semiconductors SAF7118 SAF7118_4 Product data sheet Table 5. I/O configuration programming bits - - - target ready input - - - IGPH - - - H gate output - extended H gate, horizontal pulses IDH[1:0] 84h[1:0], IRHP[85h[1]], IPE[1:0] 87h[1:0] + pin ITRI K14 (90) IGPV - - - V gate output - V-sync, IDV[1:0] 84h[3:2], vertical pulses IRVP[85h[2]], IPE[1:0] 87h[1:0] + pin ITRI K13 (89) IGP1 - - - general purpose - - IDG1[1:0] 84h[5:4], IG1P[85h[3]], IPE[1:0] 87h[1:0] + pin ITRI L14 (87) IGP0 - - - general purpose - - IDG0[1:0] 84h[7:6], IG0P[85h[4]], IPE[1:0] 87h[1:0] + pin ITRI L12 (86) ITRI - - - output enable input - - [1] Pin numbers for QFP160 QFP160 in parenthesis. - SAF7118 SAF7118 14 of 175 © NXP B.V. 2008. All rights reserved. Multistandard video decoder with adaptive comb filter ITRDY K12 (91) Rev. 04 - 4 July 2008 N12 (77) SAF7118 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter 8. Functional description 8.1 Decoder 8.1.1 Analog input processing The SAF7118 SAF7118 offers sixteen analog signal inputs, four analog main channels with source switch, clamp circuit, analog amplifier, anti-alias filter and video 9-bit CMOS ADC with a Decimation Filter (DF); see Figure 5 and Figure 6. The anti-alias filters are adapted to the line-locked clock frequency via a filter control circuit. The characteristic is shown in Figure 4. During the vertical blanking period gain and clamping control are frozen. mgd138 6 V 0 (dB) -6 -12 -18 -24 -30 -36 -42 0 2 4 6 8 10 12 14 f (MHz) Fig 4. Anti-alias filter mbl753 6 G (dB) 0 -6 -12 -18 -24 -30 -36 -42 -48 0 2 4 6 8 10 12 14 f (MHz) Fig 5. Decimation filter SAF7118 SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 - 4 July 2008 15 of 175 SAF7118 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter TEST SELECTOR AND BUFFER AOUT DIGITAL TEST SELECTOR AOSL[2:0] AI44 AI43 AI42 AI41 AI4D SOURCE SWITCH ANALOG AMPLIFIER DAC9 CLAMP CIRCUIT ANTI-ALIAS FILTER ADP[8:0] DOSL[1:0] ADPE BYPASS SWITCH ADC4 FUSE[1:0] AI34 AI33 AI32 AI31 AI3D SOURCE SWITCH ANALOG AMPLIFIER DAC9 CLAMP CIRCUIT ANTI-ALIAS FILTER BYPASS SWITCH ADC3 FUSE[1:0] AI24 AI23 AI22 AI21 AI2D SOURCE SWITCH ANALOG AMPLIFIER DAC9 CLAMP CIRCUIT ANTI-ALIAS FILTER BYPASS SWITCH ADC2 FUSE[1:0] AI14 AI13 AI12 AI11 AI1D ANALOG AMPLIFIER DAC9 CLAMP CIRCUIT SOURCE SWITCH ANTI-ALIAS FILTER BYPASS SWITCH ADC1 FUSE[1:0] MODE CONTROL CLAMP CONTROL GAIN CONTROL GLIMB HSY GLIMT WIPA SLTCA MODE[5:0] ANTI-ALIAS CONTROL HOLDG GAFIX WPOFF GUDL[1:0] GAI[48:40] GAI[38:30] HLNRS UPTCV REFA VERTICAL BLANKING CONTROL VBSL 9 9 9 9 DF DF DF DF ANALOG CONTROL CROSS MULTIPLEXER 9 CVBS/Y Fig 6. 9 CHROMA 9 R/R - Y 9 G/Y 9 B/B - Y 9 9 AD2/4BYP AD1/3BYP mbl758 Analog input processing using the SAF7118 SAF7118 as differential front-end with 9-bit ADC 8.1.1.1 Clamping The clamp control circuit controls the correct clamping of the analog input signals. The coupling capacitor is also used to store and filter the clamping voltage. An internal digital clamp comparator generates the information with respect to clamp-up or clamp-down. The clamping levels for the four ADC channels are fixed for luminance (120), chrominance (256) and for component inputs as component Y (32), components PB and PR (256) or components RGB (32). Clamping time in normal use is set with the HCL pulse on the back porch of the video signal. SAF7118 SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 - 4 July 2008 16 of 175 SAF7118 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter 8.1.1.2 Gain control The gain control circuit receives (via the I2C-bus) the static gain levels for the four analog amplifiers or controls one of these amplifiers automatically via a built-in Automatic Gain Control (AGC) as part of the Analog Input COntrol (AICO). The AGC for luminance is used to amplify a CVBS or Y signal to the required signal amplitude, matched to the ADCs input voltage range. Component inputs are gain adjusted manually at a fixed gain. The AGC active time is the sync bottom of the video signal. Signal (white) peak control limits the gain at signal overshoots. The flow charts (see Figure 9 and Figure 10) show more details of the AGC. The influence of supply voltage variation within the specified range is automatically eliminated by clamp and automatic gain control. TV line analog line blanking 511 GAIN CLAMP 120 1 HCL HSY Fig 7. mhb726 Analog line with clamp (HCL) and gain range (HSY) analog input level +3 dB 0 dB controlled ADC input level maximum range 9 dB 0 dB (1 V (p-p) 18/56 ) -6 dB minimum mhb325 Fig 8. Automatic gain range SAF7118 SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 - 4 July 2008 17 of 175 SAF7118 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter ANALOG INPUT gain AMPLIFIER 9 DAC ANTI-ALIAS FILTER ADC 9 1 NO ACTION 0 VBLK 1 LUMA/CHROMA DECODER 0 HOLDG 1 0 X 1 0 0 510 1 1 1 0 496 +1 / F > 510 X=1 X=0 1 0 HSY +1 / L +/- 0 +1 / LLC2 -1 / LLC2 -1 / LLC2 GAIN ACCUMULATOR (18 BITS) STOP ACTUAL GAIN VALUE 9-BIT (AGV) [-3/+6 dB] 1 0 X 1 0 HSY 1 AGV Y UPDATE 0 FGV GAIN VALUE 9-BIT mhb728 X = system variable Y = |AGV - FGV| > GUDL GUDL = gain update level (adjustable) VBLK = vertical blanking pulse HSY = horizontal sync pulse AGV = actual gain value FGV = frozen gain value Fig 9. Gain flow chart SAF7118 SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 - 4 July 2008 18 of 175 SAF7118 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter ANALOG INPUT ADC 1 NO BLANKING ACTIVE VBLK 0 0 HCL 1 0 0 - CLAMP NO CLAMP + GAIN < SBOT HSY 1 - GAIN 0 1 > WIPE 0 slow + GAIN fast - GAIN mgc647 WIPE = white peak level (510) SBOT = sync bottom level (1) CLL = clamp level [120 for CVBS, Y(C), S; 256 for C(Y), PB-PR; 32 for RGB, Y] HSY = horizontal sync pulse HCL = horizontal clamp pulse Fig 10. Clamp and gain flow chart SAF7118 SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 - 4 July 2008 19 of 175 xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x xxxxxxxxxxxxxx xxxxxxxxxx xxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x x Y DELAY COMPENSATION SUBTRACTOR CHR QUADRATURE MODULATOR CB-CR INTERPOLATION LOW-PASS 3 LUBW CVBS-IN or CHR-IN QUADRATURE DEMODULATOR LOW-PASS 1 DOWNSAMPLING CB-CR ADAPTIVE COMB FILTER CB-CR SET_RAW CCOMB SET_VBI YCOMB LDEL BYPS LDEL YCOMB CHROMINANCE INCREMENT DELAY SET_RAW SET_VBI LUFI[3:0] CSTD[2:0] YDEL[2:0] LOW-PASS 2 CHBW SECAM PROCESSING Y/CVBS DBRI[7:0] DCON[7:0] DSAT[7:0] RAWG[7:0] RAWO[7:0] COLO BRIGHTNESS CONTRAST SATURATION CONTROL RAW DATA GAIN AND OFFSET CONTROL CB-CR CHROMINANCE INCREMENT DTO RESET SUBCARRIER INCREMENT GENERATION AND DIVIDER SUBCARRIER GENERATION 1 HUEC[7:0] CDTO CSTD[2:0] 20 of 175 © NXP B.V. 2008. All rights reserved. Fig 11. Chrominance and luminance processing FCTC ACGC CGAIN[6:0] IDEL[3:0] CODE CHROMA GAIN CONTROL CB-CR ADJUSTMENT BRIG[7:0] CONT[7:0] SATN[7:0] PAL DELAY LINE SECAM RECOMBINATION SET_RAW SET_VBI DCVF mhb729 fH / 2 switch signal CB-CR-OUT HREF-OUT SAF7118 SAF7118 RTCO PHASE DEMODULATOR AMPLITUDE DETECTOR BURST GATE ACCUMULATOR LOOP FILTER SET_RAW SET_VBI Y-OUT/ CVBS OUT Multistandard video decoder with adaptive comb filter Rev. 04 - 4 July 2008 LCBW[2:0] SUBCARRIER GENERATION 2 LUMINANCE-PEAKING OR LOW-PASS, Y-DELAY ADJUSTMENT 8.1.2 Chrominance and luminance processing LDEL YCOMB NXP Semiconductors SAF7118 SAF7118_4 Product data sheet CVBS-IN or Y-IN SAF7118 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter 8.1.2.1 Chrominance path The 9-bit CVBS or chrominance input signal is fed to the input of a quadrature demodulator, where it is multiplied by two time-multiplexed subcarrier signals from the subcarrier generation block 1 (0° and 90° phase relationship to the demodulator axis). The frequency is dependent on the chosen color standard. The time-multiplexed output signals of the multipliers are low-pass filtered (low-pass 1). Eight characteristics are programmable via LCBW2 to LCBW0 to achieve the desired bandwidth for the color difference signals (PAL and NTSC) or the 0° and 90° FM signals (SECAM). The chrominance low-pass 1 characteristic also influences the grade of cross luminance reduction during horizontal color transients (large chrominance bandwidth means strong suppression of cross luminance). If the Y-comb filter is disabled by YCOMB = 0 the filter influences directly the width of the chrominance notch within the luminance path (a large chrominance bandwidth means wide chrominance notch resulting in a lower luminance bandwidth). The low-pass filtered signals are fed to the adaptive comb filter block. The chrominance components are separated from the luminance via a two-line vertical stage (four lines for PAL standards) and a decision logic between the filtered and the non-filtered output signals. This block is bypassed for SECAM signals. The comb filter logic can be enabled independently for the succeeding luminance and chrominance processing by YCOMB (subaddress 09h, bit D6) and/or CCOMB (subaddress 0Eh, bit D0). It is always bypassed during VBI or raw data lines programmable by the LCRn registers (subaddresses 41h to 57h); see Section 8.3. The separated CB-CR components are further processed by a second filter stage (low-pass 2) to modify the chrominance bandwidth without influencing the luminance path. Its characteristic is controlled by CHBW (subaddress 10h, bit D3). For the complete transfer characteristic of low-passes 1 and 2, see Figure 12 and Figure 13. The SECAM processing (bypassed for QAM standards) contains the following blocks: · Baseband `bell' filters to reconstruct the amplitude and phase equalized 0° and 90° FM signals · Phase demodulator and differentiator (FM-demodulation) · De-emphasis filter to compensate the pre-emphasized input signal, including frequency offset compensation (DB or DR white carrier values are subtracted from the signal, controlled by the SECAM switch signal) The succeeding chrominance gain control block amplifies or attenuates the CB-CR signal according to the required ITU 601/656 levels. It is controlled by the output signal from the amplitude detection circuit within the burst processing block. The burst processing block provides the feedback loop of the chrominance PLL and contains the following: · · · · Burst gate accumulator Color identification and color killer Comparison nominal/actual burst amplitude (PAL/NTSC standards only) Loop filter chrominance gain control (PAL/NTSC standards only) SAF7118 SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 - 4 July 2008 21 of 175 SAF7118 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter · Loop filter chrominance PLL (only active for PAL/NTSC standards) · PAL/SECAM sequence detection, H / 2-switch generation The increment generation circuit produces the Discrete Time Oscillator (DTO) increment for both subcarrier generation blocks. It contains a division by the increment of the line-locked clock generator to create a stable phase-locked sine signal under all conditions (e.g. for non-standard signals). The PAL delay line block eliminates crosstalk between the chrominance channels in accordance with the PAL standard requirements. For NTSC color standards the delay line can be used as an additional vertical filter. If desired, it can be switched off by DCVF = 1. It is always disabled during VBI or raw data lines programmable by the LCRn registers (subaddresses 41h to 57h); see Section 8.3. The embedded line delay is also used for SECAM recombination (cross-over switches). SAF7118 SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 - 4 July 2008 22 of 175 SAF7118 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter mhb533 3 V (dB) 0 -3 -6 -9 -12 (1) -15 (2) -18 (3) -21 (4) -24 -27 -30 -33 -36 -39 -42 -45 (1) LCBW[2:0] = 000. (2) LCBW[2:0] = 010. (3) LCBW[2:0] = 100. (4) LCBW[2:0] = 110. -48 -51 -54 -57 -60 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 f (MHz) 3 V (dB) 0 -3 -6 -9 -12 -15 (5) -18 (6) -21 (7) -24 (8) -27 -30 -33 -36 -39 -42 -45 (5) LCBW[2:0] = 001. (6) LCBW[2:0] = 011. (7) LCBW[2:0] = 101. (8) LCBW[2:0] = 111. -48 -51 -54 -57 -60 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 f (MHz) Fig 12. Transfer characteristics of the chrominance low-pass at CHBW = 0 SAF7118 SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 - 4 July 2008 23 of 175 SAF7118 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter mhb534 3 V (dB) 0 -3 -6 -9 -12 (1) -15 (2) -18 (3) -21 (4) -24 -27 -30 -33 -36 -39 -42 -45 (1) LCBW[2:0] = 000. (2) LCBW[2:0] = 010. (3) LCBW[2:0] = 100. (4) LCBW[2:0] = 110. -48 -51 -54 -57 -60 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 f (MHz) 3 V (dB) 0 -3 -6 -9 -12 -15 (5) -18 (6) -21 (7) -24 (8) -27 -30 -33 -36 -39 -42 -45 (5) LCBW[2:0] = 001. (6) LCBW[2:0] = 011. (7) LCBW[2:0] = 101. (8) LCBW[2:0] = 111. -48 -51 -54 -57 -60 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 f (MHz) Fig 13. Transfer characteristics of the chrominance low-pass at CHBW = 1 SAF7118 SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 - 4 July 2008 24 of 175 SAF7118 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter 8.1.2.2 Luminance path The rejection of the chrominance components within the 9-bit CVBS or Y input signal is achieved by subtracting the remodulated chrominance signal from the CVBS input. The comb filtered CB-CR components are interpolated (upsampled) by the low-pass 3 block. Its characteristic is controlled by LUBW (subaddress 09h, bit D4) to modify the width of the chrominance `notch' without influencing the chrominance path. The programmable frequency characteristics available, in conjunction with the LCBW2 to LCBW0 settings, can be seen in Figure 14 to Figure 17. It should be noted that these frequency curves are only valid for Y-comb disabled filter mode (YCOMB = 0). In comb filter mode the frequency response is flat. The center frequency of the notch is automatically adapted to the chosen color standard. The interpolated CB-CR samples are multiplied by two time-multiplexed subcarrier signals from the subcarrier generation block 2. This second DTO is locked to the first subcarrier generator by an increment delay circuit matched to the processing delay, which is different for PAL and NTSC standards according to the chosen comb filter algorithm. The two modulated signals are finally added to build the remodulated chrominance signal. The frequency characteristic of the separated luminance signal can be further modified by the succeeding luminance filter block. It can be configured as peaking (resolution enhancement) or low-pass block by LUFI3 to LUFI0 (subaddress 09h, bits D3 to D0). The 16 resulting frequency characteristics can be seen in Figure 18. The LUFI3 to LUFI0 settings can be used as a user programmable sharpness control. The luminance filter block also contains the adjustable Y-delay part; programmable by YDEL2 to YDEL0 (subaddress 11h, bits D2 to D0). SAF7118 SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 - 4 July 2008 25 of 175 SAF7118 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter mhb535 3 V (dB) 0 -3 -6 -9 -12 -15 -18 -21 (1) (2) (3) (4) -24 -27 -30 -33 -36 -39 -42 -45 (1) LCBW[2:0] = 000. (2) LCBW[2:0] = 010. (3) LCBW[2:0] = 100. (4) LCBW[2:0] = 110. -48 -51 -54 -57 -60 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 f (MHz) 3 V (dB) 0 -3 -6 -9 -12 -15 -18 -21 -24 (5) (6) (7) (8) -27 -30 -33 -36 -39 -42 -45 (5) LCBW[2:0] = 001. (6) LCBW[2:0] = 011. (7) LCBW[2:0] = 101. (8) LCBW[2:0] = 111. -48 -51 -54 -57 -60 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 f (MHz) Fig 14. Transfer characteristics of the luminance notch filter in 3.58 MHz mode (Y-comb filter disabled) at LUBW = 0 SAF7118 SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 - 4 July 2008 26 of 175 SAF7118 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter mhb536 3 V (dB) 0 -3 -6 -9 (1) -12 (2) -15 (3) -18 (4) -21 -24 -27 -30 -33 -36 -39 -42 -45 (1) LCBW[2:0] = 000. (2) LCBW[2:0] = 010. (3) LCBW[2:0] = 100. (4) LCBW[2:0] = 110. -48 -51 -54 -57 -60 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 f (MHz) 3 V (dB) 0 -3 -6 -9 -12 -15 -18 -21 -24 (5) (6) (7) (8) -27 -30 -33 -36 -39 -42 -45 (5) LCBW[2:0] = 001. (6) LCBW[2:0] = 011. (7) LCBW[2:0] = 101. (8) LCBW[2:0] = 111. -48 -51 -54 -57 -60 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 f (MHz) Fig 15. Transfer characteristics of the luminance notch filter in 3.58 MHz mode (Y-comb filter disabled) at LUBW = 1 SAF7118 SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 - 4 July 2008 27 of 175 SAF7118 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter mhb537 3 V (dB) 0 -3 -6 -9 -12 (1) -15 (2) -18 (3) -21 (4) -24 -27 -30 -33 -36 -39 -42 -45 (1) LCBW[2:0] = 000. (2) LCBW[2:0] = 010. (3) LCBW[2:0] = 100. (4) LCBW[2:0] = 110. -48 -51 -54 -57 -60 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 f (MHz) 3 V (dB) 0 -3 -6 -9 -12 (5) -15 (6) -18 (7) -21 (8) -24 -27 -30 -33 -36 -39 -42 -45 (5) LCBW[2:0] = 001. (6) LCBW[2:0] = 011. (7) LCBW[2:0] = 101. (8) LCBW[2:0] = 111. -48 -51 -54 -57 -60 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 f (MHz) Fig 16. Transfer characteristics of the luminance notch filter in 4.43 MHz mode (Y-comb filter disabled) at LUBW = 0 SAF7118 SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 - 4 July 2008 28 of 175 SAF7118 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter mhb538 3 V (dB) 0 -3 -6 -9 -12 (1) -15 (2) -18 (3) -21 (4) -24 -27 -30 -33 -36 -39 -42 -45 (1) LCBW[2:0] = 000. (2) LCBW[2:0] = 010. (3) LCBW[2:0] = 100. (4) LCBW[2:0] = 110. -48 -51 -54 -57 -60 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 f (MHz) 3 V (dB) 0 -3 -6 -9 -12 (5) -15 (6) -18 (7) -21 (8) -24 -27 -30 -33 -36 -39 -42 -45 (5) LCBW[2:0] = 001. (6) LCBW[2:0] = 011. (7) LCBW[2:0] = 101. (8) LCBW[2:0] = 111. -48 -51 -54 -57 -60 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 f (MHz) Fig 17. Transfer characteristics of the luminance notch filter in 4.43 MHz mode (Y-comb filter disabled) at LUBW = 1 SAF7118 SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 - 4 July 2008 29 of 175 SAF7118 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter mhb539 9 V (dB) 8 (1) (2) (3) (4) (5) (6) (7) (8) 7 6 5 4 3 (1) LUFI[3:0] = 0001. (2) LUFI[3:0] = 0010. (3) LUFI[3:0] = 0011. (4) LUFI[3:0] = 0100. (5) LUFI[3:0] = 0101. (6) LUFI[3:0] = 0110. (7) LUFI[3:0] = 0111. (8) LUFI[3:0] = 0000. 2 1 0 -1 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 f (MHz) 6.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 f (MHz) 6.0 3 V (dB) 0 -3 -6 (9) (10) (11) (12) (13) (14) (15) (16) -9 -12 -15 -18 -21 -24 (9) LUFI[3:0] = 1000. (10) LUFI[3:0] = 1001. (11) LUFI[3:0] = 1010. (12) LUFI[3:0] = 1011. (13) LUFI[3:0] = 1100. (14) LUFI[3:0] = 1101. (15) LUFI[3:0] = 1110. (16) LUFI[3:0] = 1111. -27 -30 -33 -36 -39 0 0.5 1.0 1.5 Fig 18. Transfer characteristics of the luminance peaking/low-pass filter (sharpness) SAF7118 SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 - 4 July 2008 30 of 175 SAF7118 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter 8.1.2.3 Brightness Contrast Saturation (BCS) control and decoder output levels The resulting Y (CVBS) and CB-CR signals are fed to the BCS block, which contains the following functions: · Chrominance saturation control by DSAT7 to DSAT0 · Luminance contrast and brightness control by DCON7 to DCON0 and DBRI7 to DBRI0 · Raw data (CVBS) gain and offset adjustment by RAWG7 to RAWG0 and RAWO7 to RAWO0 · Limiting Y-CB-CR or CVBS to the values 1 (minimum) and 254 (maximum) to fulfil "ITU Recommendation 601/656". +255 +235 +255 +240 red 100 % blue 75 % +212 red 75 % +128 LUMINANCE 100 % blue 100 % +212 +128 +255 +240 white colorless +128 colorless CB-COMPONENT CR-COMPONENT +44 +16 0 yellow 75 % +44 cyan 75 % +16 0 black yellow 100 % +16 0 cyan 100 % 001aac241 001aac480 001aac481 "ITU Recommendation 601/656" digital levels with default BCS (decoder) settings DCON[7:0] = 44h, DBRI[7:0] = 80h and DSAT[7:0] = 40h. Equations for modification to the Y-CB-CR levels via BCS control I2C-bus bytes DBRI, DCON and DSAT. DCON Luminance: Y OUT = Int - × ( Y ­ 128 ) + DBRI 68 DSAT Chrominance: ( C R C B ) OUT = Int - × (C R,C B ­ 128) + 128 64 It should be noted that the resulting levels are limited to 1 to 254 in accordance with "ITU Recommendation 601/656". a. Y output range. b. CB output range. c. CR output range. Fig 19. Y-CB-CR range for scaler input and X port output SAF7118 SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 - 4 July 2008 31 of 175 SAF7118 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter +255 +255 +209 white +199 LUMINANCE +71 +60 white LUMINANCE black black shoulder +60 SYNC 1 black shoulder = black SYNC sync bottom 1 sync bottom 001aac245 001aac244 CVBS levels with default settings RAWG[7:0] = 64 and RAWO[7:0] = 128. Equation for modification of the raw data levels via bytes RAWG and RAWO: RAWG CVBS OUT = Int - × ( CVBS nom ­ 128 ) + RAWO 64 It should be noted that the resulting levels are limited to 1 to 254 in accordance with "ITU Recommendation 601/656". a. Sources containing 7.5 IRE black level offset (e.g. NTSC M). b. Sources not containing black level offset. Fig 20. CVBS (raw data) range for scaler input, data slicer and X port output 8.1.3 Synchronization The prefiltered luminance signal is fed to the synchronization stage. Its bandwidth is further reduced to 1 MHz in a low-pass filter. The sync pulses are sliced and fed to the phase detectors where they are compared with the sub-divided clock frequency. The resulting output signal is applied to the loop filter to accumulate all phase deviations. Internal signals (e.g. HCL and HSY) are generated in accordance with analog front-end requirements. The loop filter signal drives an oscillator to generate the Line Frequency COntrol (LFCO) signal; see Figure 21. The detection of `pseudo syncs' as part of the Macrovision copy protection standard is also achieved within the synchronization circuit. The result is reported as flag COPRO within the decoder status byte at subaddress 1Fh. 8.1.4 Clock generation circuit The internal CGC generates all clock signals required for the video input processor. The internal signal LFCO is a digital-to-analog converted signal provided by the horizontal PLL. It is the multiple of the line frequency: · 6.75 MHz = 429 × fH (50 Hz), or · 6.75 MHz = 432 × fH (60 Hz) The LFCO signal is multiplied by a factor of 2 and 4 in the internal PLL circuit (including phase detector, loop filtering, VCO and frequency divider) to obtain the output clock signals. The rectangular output clocks have a 50 % duty factor. SAF7118 SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 - 4 July 2008 32 of 175 SAF7118 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter Table 6. Decoder clock frequencies Clock Frequency (MHz) XTALO 24.576 or 32.110 LLC 27 LLC2 13.5 LLC4 (internal) 6.75 LLC8 (virtual) 3.375 BAND-PASS FC = LLC / 4 ZERO CROSS DETECTION PHASE DETECTION LOOP FILTER OSCILLATOR DIVIDER 1/2 LFCO DIVIDER 1/2 LLC LLC2 mhb330 Fig 21. Block diagram of the clock generation circuit 8.1.5 Power-on reset and CE input A missing clock, insufficient digital or analog VDDA0 supply voltages (below 2.8 V) will start the reset sequence; all outputs are forced to 3-state (see Figure 22). The indicator output RES is LOW for approximately 128 LLC after the internal reset and can be applied to reset other circuits of the digital TV system. It is possible to force a reset by pulling the CE input to ground. After the rising edge of CE and sufficient power supply voltage, the outputs LLC, LLC2 and SDA return from 3-state to active, while the other signals have to be activated via programming. SAF7118 SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 - 4 July 2008 33 of 175 SAF7118 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter POC VDDA POC VDDD ANALOG DIGITAL POC LOGIC POC DELAY CLOCK PLL LLC CE RES RESINT CLK0 CE XTALO LLCINT RESINT LLC RES (internal reset) some ms 20 µs to 200 µs PLL delay < 1 ms 896 LLC digital delay 128 LLC 001aad709 POC = Power-on control CE = chip enable input XTALO = crystal oscillator output LLCINT = internal system clock RESINT = internal reset LLC = line-locked clock output RES = reset output Fig 22. Power-on control circuit SAF7118 SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 - 4 July 2008 34 of 175 SAF7118 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter VDDD = 3.3 V VDDA = 3.3 V CE(1) > 5 ms > 1 µs(3) > 1 ms start I2C-bus initialization all supplies stable(2) 001aag748 (1) CE raises with digital 3.3 V supply voltage (pulled up to this supply voltage) (2) The order of the supplies has no meaning (3) Optional reset pulse can be applied any time after minimum 5 ms when all supplies are stable Fig 23. CE raises with digital 3.3 V supply voltage VDDD = 3.3 V VDDA = 3.3 V > 5 ms CE(1) > 1 µs(3) > 1 ms start I2C-bus initialization all supplies stable(2) 001aag749 (1) CE keeps LOW during power-up (e.g. pulled down by external reset circuitry) (2) The order of the supplies has no meaning (3) A reset pulse has to be applied after minimum 5 ms subsequent to CE LOW-to-HIGH transition Fig 24. CE keeps LOW during power-up 8.2 Component video processing FSW DELAY FSW Y G/Y B/CB RGB/Y-CB-CR CB MATRIX CR R/CR DOWNFORMATTER and Y BCS and COMPONENT CB-CR DELAY bypass BCS Y to X-port MIXER CB-CR Y-CB-CR decoder mhb731 Fig 25. Component video processing SAF7118 SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 - 4 July 2008 35 of 175 SAF7118 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter 8.2.1 RGB-to-(Y-CB-CR) matrix The matrix converts the RGB signals from the analog-to-digital converters/downsamplers to the Y-CB-CR representation. The input and output word widths are 9 bits. The matrix has a gain factor of 1. The block provides a delay compensated bypass for component input signals. The matrix is represented by the following equations: · Y = 0.299 × R + 0.587 × G + 0.114 × B · CB = 0.5772 × (B - Y) · CR = 0.7296 × (R - Y) 8.2.2 Downformatter The block mainly consists of 2 parts: the color difference signal downsampler and the Y-path. The color difference signals are first passed through low-pass filters which reduce alias effects due to the lower data rate. The ITU sampling scheme requires that both color difference samples fit to the first Y sample of the current time slot. Thus the CR signal is delayed by 1 clock before it is fed to the multiplexer. The switch signal defines the data multiplex phase at the output: a `0' marks the first clock of a time slot, this is a CB sample. The output is fed through a register, so that the multiplexer runs with the opposite phase. The delay compensation for the Y signal already provides most of the registers required for a small high-pass filter. It can be used to compensate high frequency losses in the analog part. It provides 2 dB gain at 6.75 MHz. The Y high-pass filter frequency response is shown in Figure 28. The DC gain of the filter is 1, so a limiter is required at the filter output. The current implementation clips at the maximum values of 0 and 511. The entire filter can be controlled by the I2C-bus bit CMFI in subaddress 29h. LOW-PASS CR D Q 0 D Q (CR-CB)OUT 1 LOW-PASS CB switch delay compensation n HIGH-PASS Y D bypass Q YOUT mhb732 CMFI Fig 26. Downformatter block diagram SAF7118 SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 - 4 July 2008 36 of 175 SAF7118 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter mhb788 4 Z (dB) 3 2 1 0 -1 0 2 4 6 8 f (MHz) Fig 27. CB-CR low-pass filter frequency response mhb787 2 Z (dB) 0 -20 -40 -60 0 2 4 6 f (MHz) 8 Fig 28. Y high-pass filter frequency response 8.2.3 Component video BCS control The resulting Y and CB-CR signals are fed to the Component BCS (CBCS) block, which contains the following functions: · Chrominance saturation control by CSAT7 to CSAT0 · Luminance contrast and brightness control by CCON7 to CCON0 and CBRI7 to CBRI0 · Limiting Y-CB-CR or CVBS to the values 1 (minimum) and 254 (maximum) to fulfil "ITU Recommendation 601/656". SAF7118 SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 - 4 July 2008 37 of 175 SAF7118 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter +255 +235 +255 +240 red 100 % blue 75 % +212 red 75 % +128 LUMINANCE 100 % blue 100 % +212 +128 +255 +240 white colorless +128 colorless CB-COMPONENT CR-COMPONENT +44 +16 0 yellow 75 % +44 cyan 75 % +16 0 black yellow 100 % +16 0 cyan 100 % 001aac241 001aac480 001aac481 "ITU Recommendation 601/656" digital levels with default CBCS (decoder) settings CCON[7:0] = 44h, CBRI[7:0] = 80h and CSAT[7:0] = 40h. Equations for modification to the Y-CB-CR levels via CBCS control I2C-bus bytes CBRI, CCON and CSAT. CCON 68 Luminance: Y OUT = Int - × ( Y ­ 128 ) + CBRI - CSAT Chrominance: ( C B C R ) OUT = Int - × (C B,C R ­ 128) + 128 64 It should be noted that the resulting levels are limited to 1 to 254 in accordance with "ITU Recommendation 601/656". a. Y output range. b. CB output range. c. CR output range. Fig 29. Components Y-CB-CR range 8.3 Decoder output formatter The output interface block of the decoder part contains the ITU 656 formatter for the expansion port data output XPD7 to XPD0 (for a detailed description see Section 9.5.1) and the control circuit for the signals needed for the internal paths to the scaler and data slicer part. It also controls the selection of the reference signals for the RT port (RTCO, RTS0 and RTS1) and the expansion port (XRH, XRV and XDQ). The generation of the decoder data type control signals SET_RAW and SET VBI is also done within this block. These signals are decoded from the requested data type for the scaler input and/or the data slicer, selectable by the control registers LCR2 to LCR24 LCR24 (see Section 10; subaddresses 41h to 57h). For each LCR value from 2 to 23 the data type can be programmed individually; LCR2 to LCR23 LCR23 refer to line numbers. The selection in LCR24 LCR24 values is valid for the rest of the corresponding field. The upper nibble contains the value for field 1 (odd), the lower nibble for field 2 (even). The relationship between LCR values and line numbers can be adjusted via VOFF8 to VOFF0, located in subaddresses 5Bh (bit D4) and 5Ah (bits D7 to D0) and FOFF subaddress 5Bh (bit D7). The recommended values are VOFF[8:0] = 03h for 50 Hz sources (with FOFF = 0) and VOFF[8:0] = 06h for 60 Hz sources (with FOFF = 1), to accommodate line number conventions as used for PAL, SECAM and NTSC standards; see Figure 30 and Figure 31. SAF7118 SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 - 4 July 2008 38 of 175 SAF7118 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter Table 7. Data formats at decoder output Data type number Data type Decoder output data format 0 teletext EuroWST, CCST raw 1 European closed caption raw 2 Video Programming Service (VPS) raw 3 wide screen signalling bits raw 4 US teletext (WST) raw 5 US closed caption (line 21) raw 6 video component signal, VBI region Y-CB-CR 4 : 2 : 2 7 CVBS data raw 8 teletext raw 9 VITC/EBU time codes (Europe) raw 10 VITC/SMPTE time codes (USA) raw 11 reserved raw 12 US NABTS raw 13 MOJI (Japanese) raw 14 Japanese format switch (L20/22 L20/22) raw 15 video component signal, active video region Y-CB-CR 4 : 2 : 2 SAF7118 SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 - 4 July 2008 39 of 175 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx 521 LINE NUMBER (2nd FIELD) 522 259 523 524 525 1 2 active video 260 261 262 263 264 active video LINE NUMBER (1st FIELD) 10 LINE NUMBER (2nd FIELD) 273 LCR 11 10 12 4 5 265 2 13 14 15 16 17 6 7 8 serration pulses 266 267 equalization pulses 24 LCR 3 equalization pulses 268 4 18 269 270 20 271 6 21 7 8 22 23 nominal VBI lines F1 274 275 276 277 278 279 12 13 14 15 9 24 25 active video 280 281 282 283 284 285 286 nominal VBI lines F2 11 272 equalization pulses 5 19 9 equalization pulses serration pulses 3 NXP Semiconductors SAF7118 SAF7118_4 Product data sheet LINE NUMBER (1st FIELD) 287 288 active video 16 17 18 19 20 21 22 23 24 001aad425 Rev. 04 - 4 July 2008 Vertical line offset, VOFF[8:0] = 06h (subaddresses 5Bh[4] and 5Ah[7:0]); horizontal pixel offset, HOFF[10:0] = 347h (subaddresses 5Bh[2:0] and 59h[7:0]); FOFF = 1 (subaddress 5Bh[7]) Fig 30. Relationship of LCR to line numbers in 525 lines/60 Hz systems 621 LINE NUMBER (2nd FIELD) 622 309 623 624 active video 625 1 equalization pulses 310 311 active video 312 2 313 314 equalization pulses 319 LCR 6 7 8 9 10 11 12 315 316 14 15 16 17 18 317 318 equalization pulses 2 13 5 3 19 20 4 21 22 5 23 nominal VBI lines F1 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 nominal VBI lines F2 7 8 9 10 11 12 13 14 15 24 25 active video 337 338 active video 16 17 18 19 20 21 22 23 24 001aad426 40 of 175 Vertical line offset, VOFF[8:0] = 03h (subaddresses 5Bh[4] and 5Ah[7:0]); horizontal pixel offset, HOFF[10:0] = 347h (subaddresses 5Bh[2:0] and 59h[7:0]); FOFF = 0 (subaddress 5Bh[7]) Fig 31. Relationship of LCR to line numbers in 625 lines/50 Hz systems SAF7118 SAF7118 6 LINE NUMBER (2nd FIELD) © NXP B.V. 2008. All rights reserved. LINE NUMBER (1st FIELD) 4 equalization pulses serration pulses 24 LCR 3 serration pulses Multistandard video decoder with adaptive comb filter LINE NUMBER (1st FIELD) SAF7118 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter 622 309 ITU counting single field counting 623 310 624 311 625 312 1 1 2 2 3 3 4 4 5 5 6 6 7 7 22 22 . . 23 23 CVBS HREF F_ITU656 ITU656 V123 (1) VSTO [8:0] = 134h VGATE FID VSTA [8:0] = 15h (a) 1st field ITU counting single field counting 309 309 310 310 311 311 312 312 313 313 314 1 315 2 316 3 317 4 318 5 319 6 335 22 . . 336 23 CVBS HREF F_ITU656 ITU656 V123 (1) VSTO [8:0] = 134h VGATE FID (b) 2nd field VSTA [8:0] = 15h mhb540 (1) The inactive going edge of the V123 signal indicates whether the field is odd or even. If HREF is active during the falling edge of V123, the field is ODD (field 1). If HREF is inactive during the falling edge of V123, the field is EVEN. The specific position of the slope is dependent on the internal processing delay and may change a few clock cycles from version to version. The control signals listed above are available on pins RTS0, RTS1, XRH and XRV according to Table 8. For further information see Table 56, Table 57 and Table 58. Fig 32. Vertical timing diagram for 50 Hz/625 line systems Table 8. Control signals Name RTS0 RTS1 XRH XRV HREF X X X - F_ITU656 ITU656 - - - X V123 X X - X VGATE X X - - FID X X - - SAF7118 SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 - 4 July 2008 41 of 175 SAF7118 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter ITU counting single field counting 525 262 1 1 3 3 2 2 4 4 5 5 6 6 7 7 8 8 9 9 10 10 21 21 . . 22 22 CVBS HREF F_ITU656 ITU656 V123 (1) VSTO [8:0] = 101h VGATE FID VSTA [8:0] = 011h (a) 1st field ITU counting single field counting 262 262 263 263 264 1 265 2 266 3 267 4 268 5 269 6 270 7 271 8 272 9 284 21 . . 285 22 CVBS HREF F_ITU656 ITU656 V123 (1) VSTO [8:0] = 101h VGATE FID (b) 2nd field VSTA [8:0] = 011h mhb541 (1) The inactive going edge of the V123 signal indicates whether the field is odd or even. If HREF is active during the falling edge of V123, the field is ODD (field 1). If HREF is inactive during the falling edge of V123, the field is EVEN. The specific position of the slope is dependent on the internal processing delay and may change a few clock cycles from version to version. The control signals listed above are available on pins RTS0, RTS1, XRH and XRV according to Table 8. For further information see Table 56, Table 57 and Table 58. Fig 33. Vertical timing diagram for 60 Hz/525 line systems SAF7118 SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 - 4 July 2008 42 of 175 SAF7118 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter burst CVBS input processing delay ADC to expansion port: 140 × 1 / LLC expansion port data output sync clipped HREF (50 Hz) 12 × 2 / LLC 144 × 2 / LLC 720 × 2 / LLC CREF 50 Hz CREF2 5 × 2 / LLC 2 × 2 / LLC HS (50 Hz) programming range 108 (step size: 8 / LLC) -107 0 HREF (60 Hz) 16 × 2 / LLC 720 × 2 / LLC 138 × 2 / LLC CREF 60 Hz CREF2 1 × 2 / LLC 2 × 2 / LLC HS (60 Hz) programming range (step size: 8 / LLC) 107 0 -106 mhb542 The signals HREF, HS, CREF2 and CREF are available on pins RTS0 and/or RTS1 (see Table 56 and Table 57); their polarity can be inverted via RTP0 and/or RTP1. The signals HREF and HS are available on pin XRH (see Table 58). Fig 34. Horizontal timing diagram (50/60 Hz) 8.4 Scaler The High Performance video Scaler (HPS) is based on the system as implemented in previous products, but with some aspects enhanced. Vertical upsampling is supported and the processing pipeline buffer capacity is enhanced, to allow more flexible video stream timing at the image port, discontinuous transfers, and handshake. The internal data flow from block to block is discontinuous dynamically, due to the scaling process. SAF7118 SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 - 4 July 2008 43 of 175 SAF7118 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter The flow is controlled by internal data valid and data request flags (internal handshake signalling) between the sub-blocks; therefore the entire scaler acts as a pipeline buffer. Depending on the actual programmed scaling parameters the effective buffer can exceed to an entire line. The access/bandwidth requirements to the VGA frame buffer are reduced significantly. The high performance video scaler in the SAF7118 SAF7118 has the following major blocks: · Acquisition control (horizontal and vertical timer) and task handling (the region/field/frame based processing) · Prescaler, for horizontal downscaling by an integer factor, combined with appropriate band limiting filters, especially anti-aliasing for CIF format · Brightness, saturation, contrast control for scaled output data · Line buffer, with asynchronous read and write, to support vertical upscaling (e.g. for videophone application, converting 240 into 288 lines, Y-CB-CR 4 : 2 : 2) · Vertical scaling, with phase accurate Linear Phase Interpolation (LPI) for zoom and downscale, or phase accurate ACcumulation Mode (ACM) for large downscaling ratios and better alias suppression · Variable Phase Delay (VPD), operates as horizontal phase accurate interpolation for arbitrary non-integer scaling ratios, supporting conversion between square and rectangular pixel sampling · Output formatter for scaled Y-CB-CR 4 : 2 : 2, Y-CB-CR 4 : 1 : 1 and Y only (format also used for raw data) · FIFO, 32-bit wide, with 64 pixel capacity in Y-CB-CR formats · Output interface, 8-bit or 16-bit (only if extended by H port) data pins wide, synchronous or asynchronous operation, with stream events on discrete pins, or coded in the data stream The overall H and V zooming (HV_zoom) is restricted by the input/output data rate relationships. With a safety margin of 2 % for running in and running out, the maximum T_input_field - T_v_blanking HV_zoom is equal to: 0.98 × -in_pixel × in_lines × out_cycle_per_pix × T_out_clk For example: 1. Input from decoder: 50 Hz, 720 pixel, 288 lines, 16-bit data at 13.5 MHz data rate, 1 cycle per pixel; output: 8-bit data at 27 MHz, 2 cycles per pixel; the maximum 20 ms ­ 24 × 64 µs HV_zoom is equal to: 0.98 × - = 1.18 720 × 288 × 2 × 37 ns 2. Input from X port: 60 Hz, 720 pixel, 240 lines, 8-bit data at 27 MHz data rate (ITU 656), 2 cycles per pixel; output via I + H port: 16-bit data at 27 MHz clock, 1 cycle per pixel; the maximum HV_zoom is equal to: 16.666 ms ­ 22 × 64 µs 0.98 × - = 2.34 720 × 240 × 1 × 37 ns SAF7118 SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 - 4 July 2008 44 of 175 SAF7118 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter The video scaler receives its input signal from the video decoder or from the expansion port (X port). It gets 16-bit Y-CB-CR 4 : 2 : 2 input data at a continuous rate of 13.5 MHz from the decoder. Discontinuous data stream can be accepted from the expansion port (X port), normally 8-bit wide ITU 656 such as Y-CB-CR data, accompanied by a pixel qualifier on XDQ. The input data stream is sorted into two data paths, one for luminance (or raw samples) and one for time-multiplexed chrominance CB and CR samples. An Y-CB-CR 4 : 1 : 1 input format is converted to 4 : 2 : 2 for the horizontal prescaling and vertical filter scaling operation. The scaler operation is defined by two programming pages A and B, representing two different tasks, that can be applied field alternating or to define two regions in a field (e.g. with different scaling range, factors and signal source during odd and even fields). Each programming page contains control: · · · · For signal source selection and formats For task handling and trigger conditions For input and output acquisition window definition For H-prescaler, V-scaler and H-phase scaling Raw VBI data is handled as a specific input format and needs its own programming page (equals own task). In VBI pass through operation the processing of prescaler and vertical scaling has to be set to no-processing, however, the horizontal fine scaling VPD can be activated. Upscaling (oversampling, zooming), free of frequency folding, up to a factor of 3.5 can be achieved, as required by some software data slicing algorithms. These raw samples are transported through the image port as valid data and can be output as Y only format. The lines are framed by SAV and EAV codes. 8.4.1 Acquisition control and task handling (subaddresses 80h, 90h, 91h, 94h to 9Fh and C4h to CFh) The acquisition control receives horizontal and vertical synchronization signals from the decoder section or from the X port. The acquisition window is generated via pixel and line counters at the appropriate places in the data path. From X port only qualified pixels and lines (lines with qualified pixel) are counted. The acquisition window parameters are as follows: · Signal source selection regarding input video stream and formats from the decoder, or from X port (programming bits SCSRC[1:0] 91h[5:4] and FSC[2:0] 91h[2:0]) Remark: The input of raw VBI data from the internal decoder should be controlled via the decoder output formatter and the LCR registers; see Section 8.3 · Vertical offset defined in lines of the video source, parameter YO[11:0] 99h[3:0] 98h[7:0] · Vertical length defined in lines of the video source, parameter YS[11:0] 9Bh[3:0] 9Ah[7:0] SAF7118 SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 - 4 July 2008 45 of 175 SAF7118 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter · Vertical length defined in number of target lines, as a result of vertical scaling, parameter YD[11:0] 9Fh[3:0] 9Eh[7:0] · Horizontal offset defined in number of pixels of the video source, parameter XO[11:0] 95h[3:0] 94h[7:0] · Horizontal length defined in number of pixels of the video source, parameter XS[11:0] 97h[3:0] 96h[7:0] · Horizontal destination size, defined in target pixels after fine scaling, parameter XD[11:0] 9Dh[3:0] 9Ch[7:0] The source start offset (XO11 to XO0 and YO11 to YO0) opens the acquisition window, and the target size (XD11 to XD0 and YD11 to YD0) closes the window, however the window is cut vertically if there are less output lines than expected. The trigger events for the pixel and line counts are the horizontal and vertical reference edges as defined in subaddress 92h. The task handling is controlled by subaddress 90h; see Section 8.4.1.2. 8.4.1.1 Input field processing The trigger event for the field sequence detection from external signals (X port) are defined in subaddress 92h. From the X port the state of the scalers H reference signal at the time of the V reference edge is taken as field sequence identifier FID. For example, if the falling edge of the XRV input signal is the reference and the state of XRH input is logic 0 at that time, the detected field ID is logic 0. The bits XFDV[92h[7]] and XFDH[92h[6]] define the detection event and state of the flag from the X port. For the default setting of XFDV and XFDH at `00' the state of the H-input at the falling edge of the V-input is taken. The scaler directly gets a corresponding field ID information from the SAF7118 SAF7118 decoder path. The FID flag is used to determine whether the first or second field of a frame is going to be processed within the scaler and it is used as trigger condition for the task handling (see bits STRC[1:0] 90h[1:0]). According to ITU 656, when FID is at logic 0 means first field of a frame. To ease the application, the polarities of the detection results on the X port signals and the internal decoder ID can be changed via XFDH. As the V-sync from the decoder path has a half line timing (due to the interlaced video signal), but the scaler processing only knows about full lines, during 1st fields from the decoder the line count of the scaler possibly shifts by one line, compared to the 2nd field. This can be compensated for by switching the V-trigger event, as defined by XDV0, to the opposite V-sync edge or by using the vertical scalers phase offsets. The vertical timing of the decoder can be seen in Figure 32 and Figure 33. As the H and V reference events inside the ITU 656 data stream (from X port) and the real-time reference signals from the decoder path are processed differently, the trigger events for the input acquisition also have to be programmed differently. SAF7118 SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 - 4 July 2008 46 of 175 SAF7118 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter Table 9. XDV1 92h[5] Processing trigger and start XDV0 92h[4] XDH 92h[2] Description Internal decoder: The processing triggers at the falling edge of the V123 pulse [see Figure 32 (50 Hz) and Figure 33 (60 Hz)], and starts earliest with the rising edge of the decoder HREF at line number: 0 0 4/7 (50/60 Hz, 1st field), respectively 3/6 (50/60 Hz, 2nd field) (decoder count) 0 0 0 2/5 (50/60 Hz, 1st field), respectively 2/5 (50/60 Hz, 2nd field) (decoder count) 0 8.4.1.2 1 0 0 External ITU 656 stream: The processing starts earliest with SAV at line number 23 (50 Hz system), respectively line 20 (60 Hz system) (according to ITU 656 count) Task handling The task handler controls the switching between the two programming register sets. It is controlled by subaddresses 90h and C0h. A task is enabled via the global control bits TEA[80h[4]] and TEB[80h[5]]. The handler is then triggered by events, which can be defined for each register set. In the event of a programming error the task handling and the complete scaler can be reset to the initial states by setting the software reset bit SWRST[88h[5]] to logic 0. Especially if the programming registers, related acquisition window and scale are reprogrammed while a task is active, a software reset must be performed after programming. Contrary to the disabling/enabling of a task, which is evaluated at the end of a running task, when SWRST is at logic 0 it sets the internal state machines directly to their idle states. The start condition for the handler is defined by bits STRC[1:0] 90h[1:0] and means: start immediately, wait for next V-sync, next FID at logic 0 or next FID at logic 1. The FID is evaluated, if the vertical and horizontal offsets are reached. When RPTSK[90h[2]] is at logic 1 the actual running task is repeated (under the defined trigger conditions), before handing control over to the alternate task. To support field rate reduction, the handler is also enabled to skip fields (bits FSKP[2:0] 90h[5:3]) before executing the task. A TOGGLE flag is generated (used for the correct output field processing), which changes state at the beginning of a task, every time a task is activated; examples are given in Section 8.4.1.3. Remarks: · To activate a task the start condition must be fulfilled and the acquisition window offsets must be reached. For example, in case of `start immediately', and two regions are defined for one field, the offset of the lower region must be greater than (offset + length) of the upper region, if not, the actual counted H and V position at the end of the upper task is beyond the programmed offsets and the processing will `wait for next V'. SAF7118 SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 - 4 July 2008 47 of 175 SAF7118 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter · Basically the trigger conditions are checked, when a task is activated. It is important to realize, that they are not checked while a task is inactive. So you can not trigger to next logic 0 or logic 1 with overlapping offset and active video ranges between the tasks (e.g. task A STRC[1:0] = 2, YO[11:0] = 310 and task B STRC[1:0] = 3, YO[11:0] = 310 results in output field rate of 50/3 Hz). · After power-on or software reset (via SWRST[88h[5]]) task B gets priority over task A. 8.4.1.3 Output field processing As a reference for the output field processing, two signals are available for the back-end hardware. These signals are the input field ID from the scaler source and a TOGGLE flag, which shows that an active task is used an odd (1, 3, 5.) or even (2, 4, 6.) number of times. Using a single or both tasks and reducing the field or frame rate with the task handling function, the TOGGLE information can be used to reconstruct an interlaced scaled picture at a reduced frame rate. The TOGGLE flag isn't synchronized to the input field detection, as it is only dependent on the interpretation of this information by the external hardware, whether the output of the scaler is processed correctly; see Section 8.4.3. With OFIDC = 0, the scalers input field ID is available as output field ID on bit D6 of SAV and EAV, respectively on pin IGP0 (IGP1), if FID output is selected. When OFIDC[90h[6]] = 1, the TOGGLE information is available as output field ID on bit D6 of SAV and EAV, respectively on pin IGP0 (IGP1), if FID output is selected. Additionally the bit D7 of SAV and EAV can be defined via CONLH[90h[7]]. CONLH[90h[7]] = 0 (default) sets D7 to logic 1, a logic 1 inverts the SAV/EAV bit D7. So it is possible to mark the output of both tasks by different SAV/EAV codes. This bit can also be seen as `task flag' on pins IGP0 (IGP1), if TASK output is selected. SAF7118 SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 - 4 July 2008 48 of 175 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx NXP Semiconductors SAF7118 SAF7118_4 Product data sheet Table 10. Examples for field processing Subject Field sequence frame/field Example 1[1] Example 2[2][3] Example 3[2][4][5] Example 4[2][4][6] 1/1 1/2 2/1 1/1 1/2 2/1 2/2 1/1 1/2 2/1 2/2 3/1 3/2 1/1 1/2 2/1 2/2 3/1 3/2 Processed by task A A A B A B A B B A B B A B B A B B A State of detected ITU 656 FID 0 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 TOGGLE flag 1 0 1 1 1 0 0 1 0 1 1 0 0 0[7] 1 1 1[7] 0 0 1 1 1[7] 0 0 Bit D6 of SAV/EAV byte 0 1 0 0 1 0 1 1 0 1 1 0 0 0[7] Required sequence conversion at the vertical scaler[8] UP UP LO LO UP UP UP UP LO LO UP UP LO LO UP LO LO UP UP LO LO LO UP UP LO UP UP UP LO LO UP LO LO LO UP UP LO UP Output[9] O O O O O O O O O O O O O NO O O NO O O Tasks are used to scale to different output windows, priority on task B after SWRST. [3] Both tasks at 1/2 frame rate; OFIDC = 0; subaddresses 90h at 43h and C0h at 42h. [4] In examples 3 and 4 the association between input FID and tasks can be flipped, dependent on which time the SWRST is de-asserted. [5] Task B at 2/3 frame rate constructed from neighboring motion phases; task A at 1/3 frame rate of equidistant motion phases; OFIDC = 1; subaddresses 90h at 41h and C0h at 45h. [6] Task A and B at 1/3 frame rate of equidistant motion phases; OFIDC = 1; subaddresses 90h at 41h and C0h at 49h. [7] State of prior field. [8] It is assumed that input/output FID = 0 (= upper lines); UP = upper lines; LO = lower lines. [9] O = data output; NO = no output. SAF7118 SAF7118 49 of 175 © NXP B.V. 2008. All rights reserved. Multistandard video decoder with adaptive comb filter Single task every field; OFIDC = 0; subaddress 90h at 40h; TEB[80h[5]] = 0. [2] Rev. 04 - 4 July 2008 [1] SAF7118 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter 8.4.2 Horizontal scaling The overall horizontal required scaling factor has to be split into a binary and a rational value according to the equation: output pixel H-scale ratio = -input pixel 1 1024 H-scale ratio = - × -XPSC[5:0] XSCY[12:0] where the parameter of prescaler XPSC[5:0] = 1 to 63 and the parameter of VPD phase interpolation XSCY[12:0] = 300 to 8191 (0 to 299 are only theoretical values). For example, 1/3.5 is to split in 1/4 × 1.14286. The binary factor is processed by the prescaler, the arbitrary non-integer ratio is achieved via the variable phase delay VPD circuitry, called horizontal fine scaling. The latter calculates horizontally interpolated new samples with a 6-bit phase accuracy, which relates to less than 1 ns jitter for regular sampling scheme. Prescaler and fine scaler create the horizontal scaler of the SAF7118 SAF7118. Using the accumulation length function of the prescaler (XACL[5:0] A1h[5:0]), application and destination dependent (e.g. scale for display or for a compression machine), a compromise between visible bandwidth and alias suppression can be determined. 8.4.2.1 Horizontal prescaler (subaddresses A0h to A7h and D0h to D7h) The prescaling function consists of an FIR anti-alias filter stage and an integer prescaler, which creates an adaptive prescale dependent low-pass filter to balance sharpness and aliasing effects. The FIR prefilter stage implements different low-pass characteristics to reduce alias for downscales in the range of 1 to 1/2. A CIF optimized filter is built-in, which reduces artefacts for CIF output formats (to be used in combination with the prescaler set to 1/ scale); see Table 11. 2 The function of the prescaler is defined by: · An integer prescaling ratio XPSC[5:0] A0h[5:0] (equals 1 to 63), which covers the integer downscale range 1 to 1/63 · An averaging sequence length XACL[5:0] A1h[5:0] (equals 0 to 63); range 1 to 64 · A DC gain renormalization XDCG[2:0] A2h[2:0]; 1 down to 1/128 · The bit XC2_1[A2h[3]], which defines the weighting of the incoming pixels during the averaging process: ­ XC2_1 = 0 1 + 1.+ 1 + 1 ­ XC2_1 = 1 1 + 2.+ 2 + 1 The prescaler creates a prescale dependent FIR low-pass, with up to (64 + 7) filter taps. The parameter XACL[5:0] can be used to vary the low-pass characteristic for a given integer prescale of 1/XPSC[5:0]. The user can therefore decide between signal bandwidth (sharpness impression) and alias. Npix_in Equation for XPSC[5:0] calculation is: XPSC[5:0] = lower integer of -Npix_out SAF7118 SAF7118_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 - 4 July 2008 50 of 175 SAF7118 SAF7118 NXP Semiconductors Multistandard video decoder with adaptive comb filter Where: · The range is 1 to 63 (value 0 is not allowed) · Npix_in = number of input pixel, and · Npix_out = number of desired output pixel over the complete horizontal scaler The use of the prescaler results in a XACL[5:0] and XC2_1 dependent gain amplification. The amplification can be calculated according to the equation: DC gain = (XC2_1 + 1) × XACL[5:0] + (1 - XC2_1) It is recommended to use sequence lengths and weights, which results in a 2N DC gain 1 amplification, as these amplitudes can be renormalized by the XDCG[2:0] controlled -N 2 shifter of the prescaler. The renormalization range of XDCG[2:0] is 1, 1/2 down to 1/128. Other amplifications have to be normalized by using the following BCS control circuitry. In these cases the prescaler has to be set to an overall gain of 1, e.g. for an accumulation sequence of `1 + 1 + 1' (XACL[5:0] = 2 and XC2_1 = 0), XDCG[2:0] must be set to `010', this equals 1/4 and the BCS has to amplify the signal to 4/3 (SATN[7:0] and CONT[7:0] value = lower integer of 4/3 × 64). The use of XACL[5:0] is XPSC[5:0] dependent. XACL[5:0] must be < 2 × XPSC[5:0]. XACL[5:0] can be used to find a compromise between bandwidth (sharpness) and alias effects. Remark: Due to bandwidth considerations XPSC[5:0] and XACL[5:0] can be chosen differently to the previously mentioned equations or Table 12, as the H-phase scaling is able to scale in the range from zooming up by factor 3 to downscaling by a factor of 1024/ 8191. Figure 37 and Figure 38 show some resulting frequency characteristics of the prescaler. Table 12 shows the recommended prescaler programming. Other programmings, other than given in Table 12, may result in better alias suppression, but the resulting DC gain amplification needs to be compensated by the BCS control, according to the equation: XDCG[2:0]