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DATA SHEET SAB9080 NTSC Picture-In-Picture (PIP) controller Preliminary specification File under Integrated Circuits, IC02 1999

 

INTEGRATED CIRCUITS DATA SHEET SAB9080 SAB9080 NTSC Picture-In-Picture (PIP) controller Preliminary specification File under Integrated Circuits, IC02 1999 Jan 05 Philips Semiconductors Preliminary specification NTSC Picture-In-Picture (PIP) controller SAB9080 SAB9080 FEATURES · Double window PIP in interlaced mode at 8-bit resolution · Internal DRAM of 1 Mbit · Three 8-bit Analog-to-Digital Converters (ADCs) (7-bit performance) with clamp circuit for each acquisition channel It inserts one or two live video signals with reduced size into another live video signal. The incoming video signals are expected to be analog baseband signals. The conversion into the digital environment is done on chip with ADCs. Processing and storage of the video data is done entirely in the digital domain. The conversion back to the analog domain is done by means of DACs. Internal clocks are generated by PLLs which lock on to the applied horizontal and vertical syncs. · One PLL which generates the line-locked clocks for the subchannel · One PLL which generates the line-locked clocks for the main and display channel · Three 8-bit Digital-to-Analog Converters (DACs) · Linear zoom in both horizontal and vertical direction for the subchannel The main input channel is compressed horizontally with a factor of 2 and directly fed to the output. After compressing a horizontal expansion of 2 is possible for the main channel. · Linear zoom in horizontal direction for the main channel. GENERAL DESCRIPTION The subchannel is also compressed horizontally with a factor of 2 but stored in memory before it is fed to the outputs. The SAB9080 SAB9080 is an NTSC Picture-in-Picture controller which can be used in double window applications. QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supply VDDD digital supply voltage 3.0 3.3 3.6 V VDDA analog supply voltage 3.0 3.3 3.6 V IDDD digital supply current tbf 65 tbf mA IDDA analog supply current tbf 185 tbf mA - 28 - MHz - 4 - kHz - - 4 ns - 0.7 - PLL fsys system frequency Bloop loop bandwidth tjitter short term stability 1792 × HSYNC damping factor jitter during 64 µs ORDERING INFORMATION TYPE NUMBER SAB9080 SAB9080 1999 Jan 05 PACKAGE NAME QFP100 QFP100 DESCRIPTION plastic quad flat package; 100 leads (lead length 1.95 mm); body 14 × 20 × 2.8 mm 2 VERSION SOT317-2 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be . 3 SU SV SY Vbias(SA) Vref(T)(SA) Vref(B)(SA) SHSYNC SVSYNC MU 3 MY MV Vbias(MA) Vref(T)(MA) Vref(B)(MA) DHSYNC DVSYNC 4 5 6 7 14 15 16 17 20 39 40 41 42 61 64 65 66 67 76 77 78 85 86 79 8 81 10 HORIZONTAL AND VERTICAL FILTER 83 CLAMP AND ADC 84 82 12 DAC AND BUFFER 9 11 80 13 69 87 PLL AND CLOCK GENERATOR 72 LINE MEMORY DISPLAY CONTROL INTERNAL DRAM 68 DY DV DU Vbias(DA) Vref(T)(DA) Vref(B)(DA) PKOFF FBL 2 18, 19 98 30 100 HORIZONTAL FILTER CLAMP AND ADC 97 SAB9080 SAB9080 48 to 51 62, 63 99 VSSD(T1, T2) VSSD(T3) Philips Semiconductors VDDA(MF) VDDA(MA) VSSA(DA) VSSD(DA) VDDD(P1) VDDD(RL) VSSD(RM) VSSD(RP) VSSD(P2) VDDD(D) VSSA(SA) VSSD(SA) NTSC Picture-In-Picture (PIP) controller BLOCK DIAGRAM dbook, full pagewidth 1999 Jan 05 VSSA(MA) VDDA(DA) VDDD(DA) VSSD(P1) VDDD(RP) VSSD(RL) VDDD(RM) VDDD(P2) VSSD(D) VDDA(SA) VDDA(SF) VDDD(SA) VSSD(T4 to T7) VSSD(T8, T9) 1 71 94 PLL AND CLOCK GENERATOR 70 89 90 91 92 I2C-BUS TEST CONTROL CONTROL 95 96 21 to 29, 31, 52 to 60 75 74 38 73 88 93 44 43 45 32 to 37 46 DCLK TC T5 to T0 47 VSSA(DP) VSSA(SP) VDDD(MA) VDDA(DP) VSSD(MA) n.c. T6 SDA POR TM TCBD TCLK TCBR TCBC SAB9080 SAB9080 Fig.1 Block diagram. SCL T7 Preliminary specification MGM808 MGM808 VDDA(SP) Philips Semiconductors Preliminary specification NTSC Picture-In-Picture (PIP) controller SAB9080 SAB9080 PINNING SYMBOL PIN I/O DESCRIPTION Vref(B)(MA) 1 I/O MU 2 I analog U input for main channel VDDA(MF) 3 S analog supply voltage for main channel front-end buffers VSSA(MA) 4 S analog ground for main channel ADCs VDDA(MA) 5 S analog supply voltage for main channel ADCs VDDA(DA) 6 S analog supply voltage for DACs VSSA(DA) 7 S analog ground for DACs DY 8 O analog Y output of DAC Vbias(DA) 9 I/O input/output analog bias voltage reference for DACs DV 10 O analog V output of DAC analog bottom reference voltage for main channel ADCs Vref(T)(DA) 11 I/O input/output analog top reference voltage for DACs DU 12 O analog U output of DAC Vref(B)(DA) 13 I/O analog bottom reference voltage for DACs VDDD(DA) 14 S digital supply voltage for DACs VSSD(DA) 15 S digital ground for DACs VSSD(P1) 16 S digital ground for periphery VDDD(P1) 17 S digital supply voltage for periphery VSSD(T1) 18 - digital ground for test VSSD(T2) 19 - digital ground for test VDDD(RP) 20 S digital supply voltage for memory periphery 21 to 29 - not connected VSSD(T3) 30 - digital ground for test n.c. 31 - not connected T5 32 I/O test data input/output bit 5 (CMOS levels) T4 33 I/O test data input/output bit 4 (CMOS levels) T3 34 I/O test data input/output bit 3 (CMOS levels) T2 35 I/O test data input/output bit 2 (CMOS levels) T1 36 I/O test data input/output bit 1 (CMOS levels) T0 37 I/O test data input/output bit 0 (CMOS levels) TC 38 I test control input (CMOS levels) VDDD(RL) 39 S digital supply voltage for memory logic VSSD(RL) 40 S digital ground for memory logic VSSD(RM) 41 S digital ground for memory core VDDD(RM) 42 S digital supply voltage for memory core TCLK 43 I test clock input (CMOS levels) TM 44 I test mode input (CMOS levels) TCBD 45 I test control block data input (CMOS levels) TCBC 46 I test control block clock input (CMOS levels) TCBR 47 I test control block reset input (CMOS levels) 48 to 51 - digital ground for test n.c. VSSD(T4-T7) 1999 Jan 05 4 Philips Semiconductors Preliminary specification NTSC Picture-In-Picture (PIP) controller SYMBOL n.c. VSSD(RP) PIN I/O 52 to 60 - SAB9080 SAB9080 DESCRIPTION not connected 61 S digital ground for memory periphery 62 and 63 - digital ground for test VDDD(P2) 64 S digital supply voltage for periphery VSSD(P2) 65 S digital ground for periphery VSSD(D) 66 S digital ground for digital core VDDD(D) 67 S digital supply voltage for digital core FBL 68 O fast blanking control signal output (CMOS levels; +5 V tolerant) PKOFF 69 O peak off control signal output (CMOS levels; +5 V tolerant) DVSYNC 70 I vertical sync display channel input (CMOS levels; +5 V tolerant) DCLK 71 I test clock input (28 MHz) (CMOS levels) VSSD(T8,T9) SVSYNC 72 I vertical sync for subchannel input (CMOS levels; +5 V tolerant) SCL 73 I/O input/output serial clock (I2C-bus) (CMOS levels; +5 V tolerant) SDA 74 I/O input/output serial data/acknowledge output (I2C-bus) (+5 V tolerant) POR 75 I power-on reset input (CMOS levels; pull-up resistor connected to VDD) VDDA(SA) 76 S analog supply voltage for subchannel ADCs VSSA(SA) 77 S analog ground for subchannel ADCs VDDA(SF) 78 S analog supply voltage for subchannel front-end buffers and clamps SU 79 I analog U input for subchannel Vref(B)(SA) 80 I/O SV 81 I Vref(T)(SA) 82 I/O SY 83 I Vbias(SA) 84 I/O VSSD(SA) 85 S digital ground for subchannel ADCs VDDD(SA) 86 S digital supply voltage for subchannel ADCs SHSYNC 87 I horizontal sync input for subchannel (Vi < VSHSYNC) T6 88 I/O test data input/output bit 7 (CMOS levels) VDDA(SP) 89 S analog supply voltage for subchannel PLL VSSA(SP) 90 S analog ground for subchannel PLL VSSA(DP) 91 S analog ground for display channel PLL VDDA(DP) 92 S analog supply voltage for display channel PLL T7 93 I/O input/output analog bottom reference voltage for subchannel ADCs analog V input for subchannel input/output analog top reference voltage for subchannel ADCs analog Y input for subchannel analog bias reference voltage for subchannel ADCs test data input/output bit 6 (CMOS levels) DHSYNC 94 I horizontal sync display input for channel (Vi < VDHSYNC) VDDD(MA) 95 S digital supply voltage for main channel ADCs VSSD(MA) 96 S digital ground for main channel ADCs Vbias(MA) 97 I/O MY 98 I Vref(T)(MA) 99 I/O MV 100 I 1999 Jan 05 analog bias reference voltage for main channel ADCs analog Y input for main channel analog top reference voltage for main channel ADCs analog V input for main channel 5 Philips Semiconductors Preliminary specification 81 SV 82 Vref(T)(SA) 83 SY 84 Vbias(SA) 86 VDDD(SA) 85 VSSD(SA) 87 SHSYNC SAB9080 SAB9080 88 T6 90 VSSA(SP) 89 VDDA(SP) 92 VDDA(DP) 91 VSSA(DP) 93 T7 94 DHSYNC 95 VDDD(MA) 97 Vbias(MA) 96 VSSD(MA) 98 MY 100 MV handbook, full pagewidth 99 Vref(T)(MA) NTSC Picture-In-Picture (PIP) controller Vref(B)(MA) 1 80 Vref(B)(SA) MU 2 79 SU VDDA(MF) 3 78 VDDA(SF) VSSA(MA) 4 77 VSSA(SA) VDDA(MA) 5 76 VDDA(SA) VDDA(DA) 6 75 POR VSSA(DA) 7 74 SDA DY 8 73 SCL Vbias(DA) 9 72 SVSYNC DV 10 71 DCLK Vref(T)(DA) 11 70 DVSYNC DU 12 69 PKOFF Vref(B)(DA) 13 VDDD(DA) 14 68 FBL VSSD(DA) 15 VSSD(P1) 16 67 VDDD(D) 66 VSSD(D) SAB9080 SAB9080 VDDD(P1) 17 65 VSSD(P2) 64 VDDD(P2) VSSD(T1) 18 63 VSSD(T9) VSSD(T2) 19 62 VSSD(T8) 61 VSSD(RP) VDDD(RP) 20 n.c. 21 60 n.c. n.c. 22 59 n.c. n.c. 23 58 n.c. n.c. 24 57 n.c. n.c. 25 56 n.c. n.c. 26 55 n.c. n.c. 27 54 n.c. n.c. 28 53 n.c. n.c. 29 52 n.c. 51 VSSD(T7) Fig.2 Pin configuration. 1999 Jan 05 6 VSSD(T6) 50 VSSD(T5) 49 TCBR 47 VSSD(T4) 48 TCBC 46 TCBD 45 TM 44 TCLK 43 VSSD(RM) 41 VDDD(RM) 42 VSSD(RL) 40 VDDD(RL) 39 T0 37 TC 38 T1 36 T2 35 T3 34 T4 33 T5 32 n.c. 31 VSSD(T3) 30 MGM809 MGM809 Philips Semiconductors Preliminary specification NTSC Picture-In-Picture (PIP) controller SAB9080 SAB9080 FUNCTIONAL DESCRIPTION Acquisition The internal pixel rate is 28 MHz for the Y, U and V channels. It is expected that the bandwidth of the input signals is limited to 4.5 MHz for the Y input and 1.125 MHz for the U and V input. Inset synchronization is achieved via the acquisition SHSYNC and SVSYNC pins. With the acquisition fine positioning added to a system constant the starting point of the acquisition can be controlled. With a nominal input SHSYNC frequency of 1792 × HSYNC (approximately 28 MHz) clock and standard NTSC signals 1408 samples are acquired and processed by the SAB9080 SAB9080. PIP modes handbook, full pagewidth SUB MAIN SUB SUB MAIN MGM810 MGM810 MAIN REPLAY Fig.3 PIP modes. 1999 Jan 05 7 Table 1 Overview of I2C-bus addresses DATA BYTES SUB ADD BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 S1FLD SFreeze DNonint PipMode2 PipMode1 PipMode0 SHBlow0 SHRed5 SHRed4 SHRed3 SHRed2 SHRed1 SHRed0 02H SVBlow SVRed6 SVRed5 SVRed4 SVRed3 SVRed2 SVRed1 SVRed0 03H BGVfp3 BGVfp2 BGVfp1 BGVfp0 BGHfp3 BGHfp2 BGHfp1 BGHfp0 04H SDHfp7 SDHfp6 SDHfp5 SDHfp4 SDHfp3 SDHfp2 SDHfp1 SDHfp0 05H SDVfp7 SDVfp6 SDVfp5 SDVfp4 SDVfp3 SDVfp2 SDVfp1 SDVfp0 06H - - - - - - - - 07H - - - - - - - - 08H MAHfp3 MAHfp2 MAHfp1 MAHfp0 SAHfp3 SAHfp2 SAHfp1 SAHfp0 09H SAVfp7 SAVfp6 SAVfp5 SAVfp4 SAVfp3 SAVfp2 SAVfp1 SAVfp0 0AH DUVPol DVSPol DFPol DHsync SUVPol SVSPol SFPol SHsync 0BH MainFidPos7 MainFidPos6 MainFidPos5 MainFidPos4 MainFidPos3 MainFidPos2 MainFidPos1 MainFidPos0 0CH SubFidPos7 SubFidPos6 SubFidPos5 SubFidPos4 SubFidPos3 SubFidPos2 SubFidPos1 SubFidPos0 0DH BGon Bon MFidPOn SFidPOn Prio AlgOff SFblkPkff1 SFblkPkff0 0EH BSel1 BSel0 SBBrt1 SBBrt0 - SBCol2 SBCol1 SBCol0 0FH - - SLSel5 SLSel4 SLSel3 SLSel2 SLSel1 SLSel0 10H I2CHold SV SDSel5 SDSel4 SDSel3 SDSel2 SDSel1 SDSel0 11H MDHfp7 MDHfp6 MDHfp5 MDHfp4 MDHfp3 MDHfp2 MDHfp1 MDHfp0 12H MDVfp7 MDVfp6 MDVfp5 MDVfp4 MDVfp3 MDVfp2 MDVfp1 MDVfp0 13H MHBlow - MHRED5 MHRED4 MHRED3 MHRED2 MHRED1 MHRED0 14H - VBwidth2 VBwidth1 VBwidth0 - HBwidth2 HBwidth1 HBwidth0 15H to 18H all bits are reserved Preliminary specification SPIPON SHBlow1 SAB9080 SAB9080 MPIPON 01H 8 00H Philips Semiconductors The I2C-bus provides bidirectional 2-line communication between different ICs. The SDA line is the serial data line and the SCL serves as serial clock line. Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy. The SAB9080 SAB9080 has the I2C-bus addresses 2C. Valid subaddresses are 00H to 18H, registers 15H to 18H are reserved for future extensions. I2C-bus control is according to the I2C-bus protocol: First a START sequence must be put on the I2C-bus, then the I2C-bus address of the circuit must be sent, then a subaddress. After this sequence the data of the subaddresses must be sent. An auto increment function gives the option to send data of the incremented subaddresses until a STOP sequence is sent. Table 1 gives an overview of the I2C-bus addresses. The data bits which are not used should be set to zero. NTSC Picture-In-Picture (PIP) controller 1999 Jan 05 I2C-bus description Philips Semiconductors Preliminary specification NTSC Picture-In-Picture (PIP) controller SAB9080 SAB9080 MPIPON (DOUBLE WINDOW) SHRED AND SVRED (DOUBLE WINDOW) With MPIPON the main channel PIP is switched on (logic 1) or off (logic 0). SHRed and SVRed determine the reduction factor in the double window mode. The horizontal reduction is equal to SHRed/96 and the vertical reduction is equal to SVRed/96. SHRed should lie in the range from 0 to 48, if set to logic 0 the PIP is off. SVRed should lie in the range from 0 to 96, if set to logic 0 the PIP is off. SPIPON With SPIPON the sub PIPs are switched on (logic 1) or off (logic 0). S1FLD For the horizontal reduction factor, when the reduction factor is 48/96, 704 samples are processed. The HRed is linear so when HRed is e.g 24/96 352 samples are processed. For the vertical reduction factor the same holds but then with the number of lines. For NTSC the number of processed lines can be calculated from VRed/96 × 228 lines. If S1FLD is set to logic 0 two fields are used for the live PIP. When a 50/60 Hz or a 60/50 Hz mode is detected the SAB908x automatically switches to the 1 Field mode (1 Field resolution vertically). If S1FLD is set to logic 1 only one field is used. This causes joint line errors but saves memory. In normal modes this bit should not be set. BGHFP AND BGVFP These bits control the horizontal and vertical positioning of the PIP configuration on the screen. The horizontal range is adjustable in 16 steps of four 28 MHz clocks. The vertical range is 16 steps of 1 line/field. The background colour can be adjusted with bits Bsel, SBBrt and SBCol. SFREEZE With SFreeze set to logic 1 the current live sub PIP will be frozen. If set to logic 0 it is unfrozen. ALGOFF In double window mode precautions are taken to prevent a joint line error. Under some conditions this feature should be switched off. This can be realized by setting this bit to logic 1. AlgOff should be set to logic 0. SDHFP AND SDVFP These bytes control the horizontal and vertical positioning of the sub PIPs on the screen. The horizontal range is 256 steps of eight 28 MHz clocks. The vertical range is 256 steps of 1 line/field. DNONINT In normal mode (this bit is logic 0) the SAB9080 SAB9080 calculates whether a signal is non-interlaced or not and reacts accordingly. With the DNonint bit set to logic 1 the display channel is forced into the non-interlaced mode. In the non-interlaced mode only one field is used during processing of the PIPs. MAHFP, SAHFP AND SAVFP These bytes control the horizontal and vertical inset starting point of the acquired data. The horizontal range is 16 steps of eight 28 MHz clocks. The vertical range is 256 steps of 1 line/field. PIP MODE AND REPLAY DUVPOL, DVSPOL, DFPOL AND DHSYNC The PIP modes for the SAB9080 SAB9080 are shown in Table 2. Table 2 These bits control the PLL/deflection settings. With DUVPol the polarity of the border UV signals can be inverted in case the deflection circuit behind the SAB9080 SAB9080 expects inverted signals. With DVSPol set to logic 0 the SAB9080 SAB9080 triggers on positive edges of the DVSYNC. If it is set to logic 1 it triggers on negative edges. DHSYNC determines the timing of the DHSYNC pulse. If it is set to logic 0 a burstkey is expected and if it is set to logic 1 a H-sync is expected. DFPol can invert the field ID of the incoming fields. PIP modes BITS MODE 000 double window mode 001 replay mode 1999 Jan 05 9 Philips Semiconductors Preliminary specification NTSC Picture-In-Picture (PIP) controller SAB9080 SAB9080 SUVPOL, SVSPOL, SFPOL AND SHSYNC MHRED These bits control the PLL/Decoder settings. With SUVPol the polarity of the video UV signals can be inverted in case the decoder circuit before the SAB9080 SAB9080 gives inverted signals out. MHRed can set the horizontal reduction factor, equal to MHRed/96, in a range from 0 to 48. If it is set to logic 0 the PIP is off, if it is set to 48 (the maximum value of MHRed) the horizontal reduction factor is 0.5. With SVSPol set to logic 0 the SAB9080 SAB9080 triggers on positive edges of the SVSYNC. If it is set to logic 1 it triggers on the negative edges. SHSYNC determines the timing of the SHSYNC pulse. If it is set to logic 0 a burstkey is expected and if it is set to logic 1 a H-sync is expected. SFPol can invert the field ID of the incoming fields. SHBLOW AND SVBLOW (REPLAY MODE) SHBlow and SVBlow are used in the replay mode. These bits can expand a pixel on the display side by a factor two (01) or four (11) in the horizontal direction (SHBlow) and a factor of two (1) in the vertical direction (SVBlow). Zero values indicate no expansion. MAIN, SUB FID POS ON (MFIDPON AND SFIDPON) MHBLOW MFidPon (main) and SFidPon (sub) enable the field identification position fine tuning. The default value is off (logic 0), no fine positioning; when on (logic 1) the field identification position is determined by the value of M/S FIDPos. MHBlow can expand the main picture by a factor of two in the horizontal direction. SLSEL (REPLAY MODE) In the replay PIP mode SLSel determines at which memory location the PIP data is written, the range depends on the memory usage for each PIP. The maximum number of PIPs that can be stored in NTSC mode is 42. BGON BGOn determines whether a the background is visible. The background has a size of 720 pixels and 240 lines for NTSC. The background colour can be adjusted with bits Bsel, SBBrt and SBCol. SDSEL (REPLAY MODE) BON, SBBRT, SBCOL AND BSEL SDSel selects which PIP is read from memory. Valid numbers are dependent on the maximum value of SLSel. Bon can switch the sub-borders on (logic 1) or off (logic 0). SBBrt and SBCol set the brightness and colour type of the selected border. The brightness is set in 4 levels of 30%, 50%, 70% and 100% IRE. The colour type is one of black (grey), blue, red, magenta, green, cyan, yellow or white (gray). Bsel selects which colour is set, background or border. Table 3 SFBLKPKOFF 1 : 0 SFBlkPkoff shifts the signals Fblk and Pkoff with respect to the YUV output, by half pixels. Table 4 Bsel modes Shifts of FBLK and PKOff SFBLKPKOFF SHIFT OF FBLK AND PKOff BORDER COLOUR SET 00 +0.5 pixel 00 main 01 no shift 01 sub 10 -0.5 pixel 10 background 11 -1 pixel 11 sub-border select BSEL MDHFP AND MDVFP These bytes control the horizontal and vertical positioning of the main PIP on the screen. The horizontal range is 256 steps size of eight 28 MHz clocks. The vertical range is 256 steps of 1 line/field. 1999 Jan 05 10 Philips Semiconductors Preliminary specification NTSC Picture-In-Picture (PIP) controller I2CHOLD Acquisition channel ADCs and clamping I2C-bus I2CHOLD controls the updating of the controlled function towards the PIP. If set to logic 1 some register updates are on hold until the bit is set to logic 0. At the next main Vsync all settings are passed to the PIP functions. The analog input signals are converted to digital signals by means of three ADCs. The resolution of the ADCs is 8-bit (DNL is 7-bit and INL is 6-bit) and the sampling is performed at the system frequency of 28 MHz for the Y input. A bias voltage (Vbias) is used for decoupling the AC components on internal references. The registers which are on hold when the I2CHold bit is set to logic 1 are: 1. MPIPON and SPIPON. 2. SHBlow and SVBlow. 3. SHRed and SVRed. 4. BGHfp and BGVfp. 5. BGOn and Bon. 6. SBBrt and SBCol. 7. MDHfp and MDVfp. 8. HBWidth and VBWidth. 9. DNonint. 10. BSel. The inputs should be AC-coupled and an internal clamp circuit, using external clamp capacitors, will clamp the input to Vref(B)(DA) for the luminance channels and to (Vref(T)(DA) - Vref(B)(DA)/2 + LSB/2 for the chrominance channels. The clamping starts at the active edge of the burst key. Internal video buffers amplify the standard input signals Y, U and V to the correct ADC levels. PLL The PLL generates an internal system clock of 1792 × HSYNC, from the HSYNC, which is approximately 28 MHz. SV SV controls the internal horizontal offset of the background. When set to logic 0 the offset is 0.86 µs, when set to logic 1 the offset is 4.56 µs. DACs and video buffers The 28 MHz digital video signals are fed to the 8-bit DACs which produce the required analog video signals. The video buffers amplify these signals prior to being fed to the output to drive another device. HBWIDTH AND VBWIDTH These bits control the horizontal and vertical border size in steps of 2 pixels and 1 line. The default horizontal border size is 4 pixels and the vertical border size is 2 lines. Default means after power-up and no I2C-bus data sent to the Picture-in-Picture controller. NOTES 1. When the SAB9080 SAB9080 is set in the 1 field mode, joint line errors can occur. The SAB9080 SAB9080 is set in the 1 field mode by setting the 1Fld bit to logic 1. 2. When the SAB9080 SAB9080 is set in the non-interlace mode, joint line errors can occur. The SAB9080 SAB9080 is set in the non-interlace mode by setting the NonInt bit to logic 1. 3. When the input signals for the main and/or subchannel are non-interlaced signals, joint line errors can occur. When non-interlaced signals are input the SAB9080 SAB9080 switches automatically to the non-interlaced mode. 4. When the prevent joint line error algorithm is switched off (AlgOff is set to logic 1) joint line errors can still occur in the 2 field mode. 1999 Jan 05 SAB9080 SAB9080 11 Philips Semiconductors Preliminary specification NTSC Picture-In-Picture (PIP) controller SAB9080 SAB9080 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER MIN. MAX. UNIT VDD supply voltage range -0.5 tbf V Tstg storage temperature -25 +150 °C Tamb operating ambient temperature 0 70 °C Vesd electrostatic discharge handling - 3 kV Rthj-a thermal resistance - 45 K/W Pmax maximum power dissipation - 1.0 W QUALITY SPECIFICATION In accordance with "SNW-FQ-611 SNW-FQ-611, Part E", dated 14 december 1992. 1999 Jan 05 12 Philips Semiconductors Preliminary specification NTSC Picture-In-Picture (PIP) controller SAB9080 SAB9080 ESD LEVELS Table 5 ESD performance PIN SYMBOL HUMAN BODY MODEL (V) MACHINE MODEL (V) 20 VDD(RP) > 500 > 150 32 T5 400 > 150 33 T4 400 < 150 (estimated 50) 34 T3 400 < 150 (estimated 50) 35 T2 400 > 150 36 T1 400 > 150 37 T0 400 > 150 38 TC > 500 > 150 39 VDDD(RL) > 500 > 150 40 VSSD(RL) > 500 > 150 41 VSSD(RM) > 500 > 150 42 VDDD(RM) > 500 > 150 43 TCLK > 500 < 150 (estimated 50) 44 TM > 500 > 150 45 TCBD > 500 > 150 46 TCBC > 500 > 150 47 TCBR > 500 < 150 (estimated 50) 61 VSSD(RP) > 500 > 150 68 FBL 1000 standard specification 69 PKOFF 1000 standard specification 70 DVSYNC 1000 standard specification 72 SVSYNC 1000 standard specification 73 SCL 1000 standard specification 81 SV > 3000 150 93 T7 > 3000 > 325 rest in range 1 to 17 all other pins > 3000 > 325 rest in range 64 to 100 all other pins > 3000 > 325 1999 Jan 05 13 Philips Semiconductors Preliminary specification NTSC Picture-In-Picture (PIP) controller SAB9080 SAB9080 ANALOG CHARACTERISTICS VDDA = 3.3 V; Tamb = 25 °C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supplies VDD positive supply voltage 3.0 3.3 3.6 V VSS ground voltage - 0 - V VDD(max) maximum DC difference between supply voltages - 0 100 mV VSS(max) maximum DC difference between ground voltages - 0 100 mV IDDD(q) quiescent current of digital supply voltages - 0 50 µA IDDA(DP) display PLL supply current - 1 - mA IDDA(SP sub PLL supply current - 1 - mA IDDA(MA) main ADCs supply current note 2 - 65 - mA IDDA(SA) sub ADCs supply current note 2 - 65 - mA IDDA(DA) DACs supply current - tbf - mA IDDA(tot) total analog supply current - tbf - mA IDDD(tot) total digital supply current - tbf - mA note 1 note 2 Analog-to-digital converter and clamping Vref(T) top reference voltage note 3 tbf 2.90 tbf V Vref(B) bottom reference voltage note 3 tbf 1.10 tbf V ViY(p-p) Y input signal amplitude (peak-to-peak value) note 4 tbf 1.00 tbf V Vi(V)(p-p) V input signal amplitude (peak-to-peak value) note 4 tbf 1.05 tbf V Vi(U)(p-p) U input signal amplitude (peak-to-peak value) note 4 tbf 1.33 tbf V Ii input current clamping off - 0.1 - µA clamping on - tbf - µA - 5 - pF Ci input capacitance fs sample frequency - 1792 × HSYNC - kHz RES resolution 8 8 8 bit DNL differential non-linearity -1.1 - +1.1 LSB INL integral non-linearity -2.0 - +2.0 LSB cs channel separation - 48 - dB PSRR power supply rejection ratio - 48 - dB Vclamp(Y) Y clamping voltage level note 6 - 1.28 - V Vclamp(U,V) U/V clamping voltage level note 6 - 2.00 - V 1999 Jan 05 note 5 14 Philips Semiconductors Preliminary specification NTSC Picture-In-Picture (PIP) controller SYMBOL PARAMETER SAB9080 SAB9080 CONDITIONS MIN. TYP. MAX. UNIT Digital-to-analog converter and output stage Vref(T) top reference voltage tbf 1.19 tbf V Vref(B) bottom reference voltage note 2 tbf 0.19 tbf V RL load resistance 1 - 1000 k CL load capacitance 0 - 5 pF fs sample frequency - 1792 × HSYNC - kHz RES resolution 8 8 8 bit DNL differential non-linearity -1.0 - +1.0 LSB INL integral non-linearity -1.0 - +1.0 LSB cs channel separation - 48 - dB PSRR power supply rejection ratio - 48 - dB note 1 14 15.75 (NTSC) 17 kHz note 1 14 15.75 (NTSC) 17 kHz 1FH, note 5 Display PLL and clock generation fi(PLL) input frequency Sub PLL and clock generation fi(subPLL) input frequency Notes 1. Digital clocks are silent, POR and TM are connected to VDDA. 2. This value is measured with an external bias resistor of 39 k resulting in a bias current of 50 µA. 3. The Vref(T) and Vref(B) are made by a resistor division of the VDD. They can be calculated with the formulas: 2.90 1.10 V ref(T) = V DDA × - V and V ref(B) = V DDA × - V V DDA(nom) V DDA(nom) 4. The input signal are amplified to meet an internal peak-to-peak voltage level of 0.8 × [Vref(T) - Vref(B)]. 5. The internal system frequency is 1792 times the HSYNC input frequency for the subchannel. 6. The clamp level is not necessarily equal to the Vref(B) of the ADCs. ( V ref(B) + V ref(T) + V LSB ) 7. The UV-channels are clamped to: -2 1999 Jan 05 15 Philips Semiconductors Preliminary specification NTSC Picture-In-Picture (PIP) controller SAB9080 SAB9080 DIGITAL CHARACTERISTICS VDDD = 3.0 to 3.6 V; Tamb = 0 to 70 °C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT DC characteristics 0.8VDDD - VDDD + 0.5 V 0.8VDDD - tbf V 5 V tolerant pins 68, 69, 70, 72, 73 HIGH-level input voltage default pin 74 VIH 0.8VDDD - tbf V LOW-level input voltage default -0.5 - 0.2VDDD V pins tbf VIL -0.5 - 0.2VDDD V 0.8 - - V Vhys hysteresis voltage VOH HIGH-level output voltage IOL = -X mA; 0.85VDDD 85VDDD - VDDD = 3.0 V; note 1 - V VOL LOW-level output voltage - IOL =X mA; VDDD = 3.0 V; note 1 - 0.4 V - - 0.4 V IOL = 2 mA; VDDD = 3.0 V input leakage current VI = 0 - - 1 µA VI = VDDD |ILI| - - 1 µA |IOZ| 3-state output leakage current VO = 0 V or VO = VDDD - - 1 µA Ilu(I/O) I/O latch-up current V < 0V; V > VDDD 200 - - mA Rpu internal pull-up resistor 16 33 78 k AC characteristics fsys system frequency - 1792 × HSYNC - kHz tr rise time - 6 25 ns tf fall time - 6 25 ns note 2 Note 1. X is the source/sink current under worst case conditions. X is reflected in the name of the I/O cell according to the drive capability. Minimum value of X is 1 mA. 2. The internal system frequency is 1792 times the HSYNC input frequency for the subchannel. 1999 Jan 05 16 Philips Semiconductors Preliminary specification NTSC Picture-In-Picture (PIP) controller SAB9080 SAB9080 TEST AND APPLICATION INFORMATION The application diagram in a standard configuration is shown in Figure 4. The input signals main CVBS and sub CVBS of different video sources are processed by the SAB9080 SAB9080 and inserted by the YUV/RGB switch. HS/VS handbook, full pagewidth FBL sub CVBS SUB DECODER YUV TDA8310 TDA8310 YUV SAB9080 SAB9080 PIP CONTROLLER TDA4780 TDA4780 HS/VS HS/VS RGB YUV to RGB YUV/RGB PROCESSING AND DEFLECTION CIRCUIT HS/VS RGB main CVBS MAIN DECODER YUV YUV TDA8310 TDA8310 MGM811 MGM811 Fig.4 Application diagram. 1999 Jan 05 17 Philips Semiconductors Preliminary specification NTSC Picture-In-Picture (PIP) controller SAB9080 SAB9080 PACKAGE OUTLINE QFP100 QFP100: plastic quad flat package; 100 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm SOT317-2 c y X 80 A 51 81 50 ZE e E HE A A2 (A 3) A1 wM pin 1 index Lp bp L 31 100 detail X 30 1 wM bp e ZD v M A D B HD v M B 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HD HE L Lp v w y mm 3.20 0.25 0.05 2.90 2.65 0.25 0.40 0.25 0.25 0.14 20.1 19.9 14.1 13.9 0.65 24.2 23.6 18.2 17.6 1.95 1.0 0.6 0.2 0.15 0.1 Z D (1) Z E(1) 0.8 0.4 1.0 0.6 o 7 0o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC EIAJ ISSUE DATE 95-02-04 97-08-01 SOT317-2 1999 Jan 05 EUROPEAN PROJECTION 18 Philips Semiconductors Preliminary specification NTSC Picture-In-Picture (PIP) controller · Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. SOLDERING Introduction to soldering surface mount packages · For packages with leads on two sides and a pitch (e): This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). ­ larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. ­ smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. · For packages with leads on four sides, the footprint must be placed at a 45° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Typical reflow peak temperatures range from 215 to 250 °C. The top-surface temperature of the packages should preferable be kept below 230 °C. Manual soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results: 1999 Jan 05 SAB9080 SAB9080 19 Philips Semiconductors Preliminary specification NTSC Picture-In-Picture (PIP) controller SAB9080 SAB9080 Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE REFLOW(1) WAVE BGA, SQFP not suitable HLQFP, HSQFP, HSOP, HTSSOP, SMS not PLCC(3), SO, SOJ suitable suitable(2) suitable suitable suitable LQFP, QFP, TQFP not recommended(3)(4) suitable SSOP, TSSOP, VSO not recommended(5) suitable Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 1999 Jan 05 20 Philips Semiconductors Preliminary specification NTSC Picture-In-Picture (PIP) controller SAB9080 SAB9080 DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. PURCHASE OF PHILIPS I2C COMPONENTS Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011. 1999 Jan 05 21 Philips Semiconductors Preliminary specification NTSC Picture-In-Picture (PIP) controller NOTES 1999 Jan 05 22 SAB9080 SAB9080 Philips Semiconductors Preliminary specification NTSC Picture-In-Picture (PIP) controller NOTES 1999 Jan 05 23 SAB9080 SAB9080 Philips Semiconductors ­ a worldwide company Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 545104/750/01/pp24 Date of release: 1999 Jan 05 Document order number: 9397 750 03293