SAA7750-N1D ARM720T SAA7750 17PURCHASE LFBGA208 SAA7750EL/N1 SAA7750EL CLK01 - Datasheet Archive

 

DATA SHEET Generic device for portable multimedia applications SAA7750-N1D Preliminary Specification version 1.3 File under

 

INTEGRATED CIRCUITS DATA SHEET Generic device for portable multimedia applications SAA7750-N1D SAA7750-N1D Preliminary Specification version 1.3 File under Integrated Circuits, 2002 Jan 21 Philips Semiconductors Preliminary Specification version 1.3 Generic device for portable multimedia applications SAA7750-N1D SAA7750-N1D CONTENTS 1 1.1 1.2 1.3 Hardware Features General Features Software features 2 GENERAL DESCRIPTION 3 APPLICATIONS 4 BLOCK DIAGRAM 5 PINNING 6 HARDWARE DESCRIPTION SSA 6.1 6.1.1 6.1.2 6.1.3 6.2 6.2.1 6.2.2 6.3 6.3.1 6.3.2 6.3.3 6.3.4 6.3.5 6.3.5.1 6.3.5.2 6.3.5.3 6.3.5.4 6.4 6.4.1 6.4.2 6.5 6.5.1 6.5.2 6.5.3 6.5.4 6.5.5 6.5.5.1 6.5.5.2 6.6 6.6.1 6.6.2 6.7 6.7.1 6.8 6.8.1 6.8.2 6.8.3 6.8.4 6.8.5 6.9 6.9.1 6.9.2 6.9.3 6.10 6.10.1 6.10.2 6.11 6.11.1 6.11.2 6.11.3 6.12 6.12.1 6.12.2 6.13 6.13.1 6.13.2 6.14 6.14.1 6.14.2 6.15 6.15.1 6.15.2 6.16 6.16.1 6.16.2 6.16.3 6.16.4 6.16.5 6.16.6 6.16.7 6.16.8 6.16.9 6.17 6.17.1 6.18 6.19 6.19.1 6.19.1.1 6.19.1.2 6.19.1.3 6.19.1.4 6.20 6.20.1 6.20.1.1 6.20.2 6.20.3 6.20.4 6.20.5 6.20.6 6.20.7 6.20.8 6.20.9 6.21 FEATURES ARM720T ARM720T microcontroller Overview BLOCK DIAGRAM The THUMB Concept Internal busses Advanced High-performance Bus (AHB) AHB Address Decoder Memory controllers Overview Static Memory Controller SDRAM Interface Controller Internal Memory Controller FLASH memory controller FLASH reads Erasing the FLASH block Programming the FLASH block Operating conditions Interrupt Controller Overview Functional Description Power Management Unit (PMU) Functional Description Wake-up behaviour Watchdog behaviour Pause behaviour Power down behaviour Power down Request Power down Acknowledge Oscillators and clock generation Overview clock generation module Functional Description Multi Media Card Interface (MMC) Choice of flash memory cards 10-bit ADC Overview Functional description Multi channel A/D conversion scan ADC resolution Interrupts UART 2002 Jan 21 2 Functional Description UART Pin Description BaudRate Generator General Purpose I/O Functional Description Interrupts Real Time Clock (RTC) Functional Description Interrupts Power Down operation Timers Functional description Interrupts Watchdog Timer Functional description Interrupts IIC master Interface Functional Description Interrupt IIC slave Interface Functional description Interrupt LCD Interface Functional Description Interface System Interface Resetting the LCD controller Serial mode: Using wait states Checking the busy flag of the LCD controller Loopback mode Interrupt Remote Control Interface Functional Description Parallel Port Interface (PPI) USB Interface Interrupts USB_int_req_FIQ USB_int_req_IRQ Interrupt handling Zero overhead operation CD Block Decoder Functional Description Features Input/Output Pin Function I2C Interface Standard Serial Interface UART Subcode Interface Serial Data Interface Minimal Block Decoder CD TEXT Mode Q-subcode Frame Format Digital Signal Processor (EPICS7a) Philips Semiconductors Preliminary Specification version 1.3 Generic device for portable multimedia applications SAA7750-N1D SAA7750-N1D 6.22 Digital Audio input and output 7 HARDWARE DESCRIPTION SSA CODEC 7.1 7.2 7.3 7.4 7.5 7.6 General Multiple format data INPUT interface Multiple format data OUTPUT interface DAC digital sound processing Block diagram Connections to SAA7750 SAA7750 8 HARDWARE DESCRIPTION FLASH 9 LIMITING VALUES 10 THERMAL CHARACTERISTICS 11 DC CHARACTERISTICS 12 AC CHARACTERISTICS 13 PACKAGE OUTLINE 14 SOLDERING 15 DEFINITIONS 16 DISCLAIMERS 17PURCHASE 17PURCHASE OF PHILIPS I2C COMPONENTS 2002 Jan 21 3 Philips Semiconductors Preliminary Specification version 1.3 Generic device for portable multimedia applications SAA7750-N1D SAA7750-N1D 1 FEATURES NOTE: this datasheet is for SAA7750El version N1D onwards!! 1.1 Hardware Features · Integrated ARM720T ARM720T 32 bit RISC processor, capable of running at 72MHz. · High performance 32-bits bus (AHB) · Centralized address decoding for all AHB devices · Four possible memory maps: ­ external boot ­ internal flash boot ­ internal ROM boot ­ normal operation · Supports USB 1.1 compliant interface for down loading data from PC · Support for flash-card applications: ­ Supports the Multi Media Card (MMC) ­ Supports Smart Media Card (EBI) ­ NAND FLASH (EBI) · Memory interface (EBI) supporting a number of memory types like Static RAM, SDRAM, external Flash. The maximum bus frequency can be up to 48MHz. · Integrated CD block decoder for CD-DA and MP3 CD applications · UART + IrDA (IrDA is a new block on the N1D version) · Integrated Master and Slave IIC interface · Real-Time Clock (RTC) · General-Purpose IO pins (28 pins) · Integrated Remote Control interface · Integrated LCD interface with 6800 / 8080 type interface · Integrated 10 bits ADC with 8 selectable inputs (via analog multiplexer). · Integrated SPDIF output interface · Integrated IIS input and output interface · Integrated stereo Audio Codec ­ Stereo Line input with Programmable Gain Amplifier (PGA) ­ Mono Microphone input with embedded Low Noise Amplifier (LNA) and Variable Gain Amplifier (VGA ­ stereo analog input with analog volume control (e.g. for tuner applications) ­ stereo line output ­ integrated stereo headphone driver which can be used in DC coupling (short circuit protection and detection build in). 1.2 General Features · Integrated ARM720T ARM720T 32 bit RISC processor · Programmable architecture enables support of multiple audio decompression algorithms. · Designed for applications that require long battery life 2002 Jan 21 4 PHILIPS CONFIDENTIAL Philips Semiconductors Preliminary Specification version 1.3 Generic device for portable multimedia applications SAA7750-N1D SAA7750-N1D · Embedded 3Mbit (384kbyte) flash for Field upgradibility · Embedded Audio Codec with headphone driver · small footprint LFBGA208 LFBGA208 package 1.3 Software features · Audio Decoder support: ­ Supports MPEG 1 layer 3 and MPEG 2 layer 2.5 and layer 3 audio decoding (MP3), up to 320kbit/s , fixed and variable bitrate. ­ Supports Microsoft WMTA 4.0 decoding ­ Supports AAC-LC decoding · Features on the audio codec: ­ Digital Automatic Gain Control (AGC) on the microphone input. ­ Programmable Gain Amplifier (PGA) for analog stereo line input ­ Volume control (incl. balance) ­ Bass-boost and Treble (left/right) · DSP features: ­ UltraBass II ­ Incredible headphone ­ Infrapitch 2 GENERAL DESCRIPTION The SAA7750 SAA7750 is an IC based on an embedded RISC processor in combination with a simple embedded DSP core for audio post-processing. The device is designed for hand-held applications like portable CD-DA/ MP3 players, memory card applications or other portable applications. The high level of integration, low power consumption and high processor performances make the SAA7750 SAA7750 very suitable for portable hand-held devices. The SAA7750 SAA7750 is based on the powerful ARM720T ARM720T CPU core, which is a full 32-bit RISC processor featuring the 16-bit Thumb instruction set for effective memory usage. The audio streaming and post-processing for the SAA7750 SAA7750 is handled by a separate audio co-processor DSP, which is a small, fast and powerful 24-bit Epics7A DSP core. 3 APPLICATIONS · Portable Solid State Audio player · Portable MP3 CD player · Home audio applications · Non-automotive Car applications · Other portable applications like PDA 4 ORDERING INFORMATION PACKAGE TYPE NUMBER NAME SAA7750EL/N1 SAA7750EL/N1 2002 Jan 21 LFBGA208 LFBGA208 DESCRIPTION low profile fine-pitch ball grid array package; 208 balls; body 15 x 15 x 1.2 mm. 5 VERSION SOT631-1 PHILIPS CONFIDENTIAL JTAG/TCB 5 supplies (8C + 4P) AHB Arbiter ROM AHB wrapper SMC SRAM AHB wrapper TIC 12 mode selection pins 3 external bus interface + tic EBI 49 AHB Decoder Philips Semiconductors BLOCK DIAGRAM SAA7750-N1D SAA7750-N1D 2002 Jan 21 5 SDRAM Controller FLASH memory FLASH Controller 3Mbit FLASH 2 52 AHB wrapper ARM720T ARM720T ETU 3 DSP EPICS7a AHB to APB bridge 4 TCB Interrupt Controller 6 10 2 3 IIS Output Stereo IIS Input Stereo 3 General Purpose I/O Timers Remote Control Watchdog 3 Real-Time Clock 1 Slave IIC Interface Clock Shop Audio Codec IrDA UART ATX PHILIPS CONFIDENTIAL USB 1.1 Interface OSCs 10 PLLs 5 DAC 4 3 Headphone Driver 5 10-bits ADC 9 4 ADC 12 LCD Interface 12 SSA PMU Clock Shop 2 1 3 Fig. 1 Block diagram Solid State Audio 1 Preliminary Specification version 1.3 3 PGA CTU MCI 4 Generic device for portable multimedia applications 2 Interface IIS/SPDIF Output Master IIC Interface 3 28 bus CD-Block Decoder 1 L3/IIC IIS Input Philips Semiconductors Preliminary Specification version 1.3 Generic device for portable multimedia applications SAA7750-N1D SAA7750-N1D 6 PINNING Table 1 Pin list SAA7750EL SAA7750EL SYMBOL(1) LFBGA 208 PIN DIGITAL I/O LEVEL APPL. FUNC PIN STATE AFTER RESET DESCRIPTION General Purpose Pins (fixed: 16 pins) GPIO A13 0-5 VDC tolerant I/O 0 General Purpose IO pin GPIO A12 0-5 VDC tolerant I/O 0 General Purpose IO pin GPIO B12 0-5 VDC tolerant I/O 0 General Purpose IO pin GPIO A11 0-5 VDC tolerant I/O 0 General Purpose IO pin GPIO B11 0-5 VDC tolerant I/O 0 General Purpose IO pin GPIO A10 0-5 VDC tolerant I/O 0 General Purpose IO pin GPIO B10 0-5 VDC tolerant I/O 0 General Purpose IO pin GPIO A9 0-5 VDC tolerant I/O 0 General Purpose IO pin GPIO B9 0-5 VDC tolerant I/O 0 General Purpose IO pin GPIO A8 0-5 VDC tolerant I/O 0 General Purpose IO pin GPIO B8 0-5 VDC tolerant I/O 0 General Purpose IO pin GPIO A7 0-5 VDC tolerant I/O 0 General Purpose IO pin GPIO F4 0-5 VDC tolerant I/O 0 General Purpose IO pin GPIO G2 0-5 VDC tolerant I/O 0 General Purpose IO pin GPIO F3 0-5 VDC tolerant I/O 0 General Purpose IO pin GPIO G1 0-5 VDC tolerant I/O 0 General Purpose IO pin GPIO F2 0-5 VDC tolerant I/O 0 General Purpose IO pin GPIO F1 0-5 VDC tolerant I/O 0 General Purpose IO pin GPIO D3 0-5 VDC tolerant I/O 0 General Purpose IO pin GPIO E2 0-5 VDC tolerant I/O 0 General Purpose IO pin GPIO D4 0-5 VDC tolerant I/O 0 General Purpose IO pin GPIO E1 0-5 VDC tolerant I/O 0 General Purpose IO pin GPIO D2 0-5 VDC tolerant I/O 0 General Purpose IO pin GPIO D1 0-5 VDC tolerant I/O 0 General Purpose IO pin GPIO C2 0-5 VDC tolerant I/O 0 General Purpose IO pin GPIO C1 0-5 VDC tolerant I/O 0 General Purpose IO pin GPIO B1 0-5 VDC tolerant I/O 0 General Purpose IO pin GPIO A1 0-5 VDC tolerant I/O 0 General Purpose IO pin Memory Card Interface (fixed: 3 pins) MCI_DAT A4 MCI_CLK A2 MCI_CMD B2 0-5 VDC tolerant Data input/Data output O 0-5 VDC tolerant I/O MCI clock output I/O Command input/Command output USB Interface (fixed: 4 pins) USB_DP C17 A USB_DM D17 A Negative USB data line USB_CONNECT_N D16 O Soft connect output USB_VUSB C15 I USB supply detection input 0-5 VDC tolerant Positive USB data line 6 MHz oscillator (fixed: 4 pins) XTAL1I P4 A 6MHz clock input XTAL1O R3 A 6MHz clock output 2002 Jan 21 7 PHILIPS CONFIDENTIAL Philips Semiconductors Preliminary Specification version 1.3 Generic device for portable multimedia applications SAA7750-N1D SAA7750-N1D SYMBOL(1) LFBGA 208 PIN DIGITAL I/O LEVEL APPL. FUNC PIN STATE AFTER RESET DESCRIPTION VDDA1 R2 Analog supply Oscillator 1 VSSA1 R1 Analog ground Oscillator 1 32.768 kHz oscillator (fixed: 4 pins) XTAL2I N4 A XTAL2O P3 A 32.768 kHz clock input VDDA2 P2 Analog supply Oscillator 2 VSSA2 P1 Analog ground Oscillator 2 32.768 kHz clock output Voltage Supply PLLs (fixed: 2 pins) VDDA3 N2 Analog supply PLLs VSSA3 N1 Analog ground PLLs PLL (fixed: 1 pin) CLKO1 F15 O toggling 256fs clock output LCD Interface (fixed: 13 pins) LCD_WE K3 O Write Enable LCD_RW_WR A16 O 6800 read/write select 8080 active `high' write enable LCD_E_RD B15 O 6800 active `low' enable 8080 active `high' write enable LCD_DB D14 0-5 VDC tolerant I/O Data input 0/Data output 0 LCD_DB B17 0-5 VDC tolerant I/O Data input 1/Data output 1 LCD_DB C14 0-5 VDC tolerant I/O Data input 2/Data output 2 LCD_DB C16 0-5 VDC tolerant I/O Data input 3/Data output 3 LCD_DB D13 0-5 VDC tolerant I/O Data input 4/Data output 4 LCD_DB A17 0-5 VDC tolerant I/O Data input 5/Data output 5/serial clock LCD_DB C13 0-5 VDC tolerant I/O Data input 6/Data output 6/Serial data input LCD_DB B16 0-5 VDC tolerant I/O Data input 7/Data output 7/Serial data output LCD_CSB C12 O Chip Select (active low) LCD_RS D12 O `high' Data register select `low' Instruction register select Parallel Port Interface (fixed: 18 pins) . THIS FUNCTIONALITY HAS BEEN REMOVED!! 10-bit ADC (fixed: 12pins) GPA B7 A Analog General Purpose pin 7 GPA A6 A Analog General Purpose pin 6 GPA B6 A Analog General Purpose pin 5 GPA A5 A Analog General Purpose pin 4 GPA B5 A Analog General Purpose pin 3 GPA J3 A Analog General Purpose pin 2 GPA M4 A Analog General Purpose pin 1 GPA N3 A Analog General Purpose pin 0 VREFP M3 A 10-bit ADC Reference voltage 1 VREFP L2 A VDDA4 M2 Analog supply 10-bit ADC VSSA4 M1 Analog ground 10-bit ADC 10-bit ADC Reference voltage 0 Remote Control (fixed: 2 pins) DO K1 O Remote Control Data Output 0 DI K2 0-5 VDC tolerant I Remote Control Data Input 0 J15 0-5 VDC tolerant I Bitclock input (external) IIS input (fixed: 3 pins) BCKI1 2002 Jan 21 8 PHILIPS CONFIDENTIAL Philips Semiconductors Preliminary Specification version 1.3 Generic device for portable multimedia applications SAA7750-N1D SAA7750-N1D SYMBOL(1) LFBGA 208 PIN APPL. FUNC DIGITAL I/O LEVEL WSI1 H15 0-5 VDC tolerant DATAI1 G15 0-5 VDC tolerant PIN STATE AFTER RESET I DESCRIPTION Wordselect input (external) I Serial data input (external) IIS output (fixed: 3 pins) BCKO1 M14 O Tri-state Bitclock output (external) WSO1 F16 O Tri-state Wordselect output (external) DATAO1 E16 O Output/Low Serial data output (external) SPDIF output (fixed: 1 pin) DATAO2_SPDIFO E15 O Serial data output (internal), SPDIF output JTAG Reset Input JTAG (fixed: 5 pins) JTAG_NTRST K15 0-5 VDC tolerant I JTAG_TCK U12 0-5 VDC tolerant I JTAG Clock Input JTAG_TMS K16 0-5 VDC tolerant I JTAG Mode Select Input JTAG_TDI T13 0-5 VDC tolerant JTAG_TDO U13 I JTAG Data Input O JTAG Data Output Serial clock IIC Slave IIC slave Interface (fixed: 3 pins) SCL_SLAVE P12 0-5 VDC tolerant I SDA_SLAVE R12 0-5 VDC tolerant I/O A0_SLAVE T12 0-5 VDC tolerant I Serial data IIC Slave Address selection Slave IIC master interface (fixed: 2 pins) SDA_MASTER R13 0-5 VDC tolerant I/O IIC data I/O line (open drain output)/ UART Serial Data Input SCL_MASTER P13 0-5 VDC tolerant I/O IIC clock line output/ UART Serial Data Output 0-5 VDC tolerant I Communication request line/CD engine is ready to receive the next frame CD Block Decoder (fixed: 10 pins) CDB_CRQ_NERDY C5 CDB_NCRST_NHRDY D5 O CD engine reset line/Host is ready to receive the next frame CDB_CLAB C9 0-5 VDC tolerant I IIS/EIAJ input bit clock CDB_DAAB C7 0-5 VDC tolerant I IIS/EIAJ serial data CDB_WSAB C8 0-5 VDC tolerant I IIS/EIAJ word clock CDB_EFAB D9 0-5 VDC tolerant I IIS/EIAJ error flags CDB_V4_SUB D8 0-5 VDC tolerant I Versatile pin 4:single wire subcode/EIAJ subcode data bits CDB_CFLAG_SBSY D6 0-5 VDC tolerant I Absolute time sync/EIAJ subcode block sync CDB_SFSY D7 0-5 VDC tolerant I EIAJ subcode frame sync CDB_RCK C6 O EIAJ subcode clock output EBI_NCS G16 O Chip Selected 2 EBI_NCS T10 O Chip Selected 1 EBI_NCS U10 O Chip Selected 0 EBI_SDNCS H3 O External SDRAM selection1 and SDRAM selection0 EBI_WEN J2 O Write enable not EBI (fixed: 49 pins) EBI_A J16 O EBI address EBI_A H16 O EBI address EBI_A F14 O EBI address EBI_A G14 O EBI address EBI_A H14 O EBI address EBI_A J14 O EBI address EBI_A R9 O EBI address 2002 Jan 21 9 PHILIPS CONFIDENTIAL Philips Semiconductors Preliminary Specification version 1.3 Generic device for portable multimedia applications SAA7750-N1D SAA7750-N1D SYMBOL(1) LFBGA 208 PIN DIGITAL I/O LEVEL APPL. FUNC PIN STATE AFTER RESET DESCRIPTION EBI_A T9 O EBI address EBI_A U9 O EBI address EBI_A R8 O EBI address EBI_A T8 O EBI address EBI_A U8 O EBI address EBI_A P11 O EBI address EBI_A R7 O EBI address EBI_A P10 O EBI address EBI_A U7 O EBI address EBI_A P9 O EBI address EBI_A T7 O EBI address EBI_A P8 O EBI address EBI_A R6 O EBI address EBI_A U6 O EBI address EBI_D T6 0-5 VDC tolerant I/O EBI data EBI_D U5 0-5 VDC tolerant I/O EBI data EBI_D T5 0-5 VDC tolerant I/O EBI data EBI_D U4 0-5 VDC tolerant I/O EBI data EBI_D T4 0-5 VDC tolerant I/O EBI data EBI_D U3 0-5 VDC tolerant I/O EBI data EBI_D T3 0-5 VDC tolerant I/O EBI data EBI_D P7 0-5 VDC tolerant I/O EBI data EBI_D U2 0-5 VDC tolerant I/O EBI data EBI_D P6 0-5 VDC tolerant I/O EBI data EBI_D U1 0-5 VDC tolerant I/O EBI data EBI_D R5 0-5 VDC tolerant I/O EBI data EBI_D T2 0-5 VDC tolerant I/O EBI data EBI_D P5 0-5 VDC tolerant I/O EBI data EBI_D T1 0-5 VDC tolerant I/O EBI data EBI_D R4 0-5 VDC tolerant I/O EBI data EBI_SDCLKOUT J1 O SDRAM clock EBI_CKE H4 O SDRAM clock enable EBI_DQM T11 O SDRAM data mask 1 EBI_DQM U11 O SDRAM data mask 0 EBI_NRAS R10 O SDRAM row address strobe EBI_NCAS R11 O SDRAM column address strobe EBI_NOE H2 O EBI output enable Test pins (3 pins) TEST_DAT B3 0-5 VDC tolerant I/O Data input/Data output TEST_DAT A3 0-5 VDC tolerant I/O Data input/Data output TEST_DAT B4 0-5 VDC tolerant I/O Data input/Data output UART_IO_NRI E14 0-5 VDC tolerant UART_DIR_TX D10 UART (fixed: 9 pins) UART_REQ_RX C10 UART_RST_NRTS C11 UART_CLK D11 2002 Jan 21 I O 0-5 VDC tolerant I O 0-5 VDC tolerant I/O 10 PHILIPS CONFIDENTIAL Philips Semiconductors Preliminary Specification version 1.3 Generic device for portable multimedia applications SAA7750-N1D SAA7750-N1D SYMBOL(1) LFBGA 208 PIN DIGITAL I/O LEVEL APPL. FUNC UART_NCTS B14 0-5 VDC tolerant A15 0-5 VDC tolerant I UART_NDSR B13 0-5 VDC tolerant UART_NDTR A14 DESCRIPTION I UART_NDCD PIN STATE AFTER RESET I O Mode Selection pins SAA7750 SAA7750 (fixed: 3 pins) MODE L16 0-5 VDC tolerant I MODE M15 0-5 VDC tolerant I MODE M16 0-5 VDC tolerant I Wake-up input pin SAA7750 SAA7750 (fixed: 1 pin) WAKE_UP L1 0-5 VDC tolerant I Wake up input pin I System Reset Input O Reset output I Reset input pin with pull-down for creating Power-On-Reset Reset input pin SAA7750 SAA7750 (fixed: 1 pin) NRESET_IN L15 0-5 VDC tolerant Reset output pin SAA7750 SAA7750 (fixed: 1 pin) RESET_OUT N16 Reset input pin SSA Audio Codec (fixed: 1 pin) RESET N15 0-5 VDC tolerant DAC SSA Audio Codec (fixed: 4 pins) VOUTL P15 A Analog left output pin VOUTR R16 A Analog right output pin VDDA(DA) R17 Analog supply DAC VSSA(DA) P16 Analog ground DAC Headphone Amplifier SSA Audio Codec (fixed: 5 pins) VOUTL(HP) T17 A Analog left output pin VOUTR(HP) U17 A Analog right output pin VREF(HP) T16 A Analog reference output pin VDDA(HP) R15 Analog supply Headphone Driver VSSA(HP) U16 Analog ground Headphone Driver ADC SSA Audio Codec (fixed: 8 pins) VINL M17 A Left line input VINR K17 A Right line input VINM H17 A Microphone input VADCP G17 A Positive Reference voltage ADC VADCN J17 A Negative Reference voltage ADC VREF P17 A Reference voltages ADC VDDA(AD) L17 Analog supply ADC VSSA(AD) N17 Analog ground ADC Control pins SSA Audio Codec (fixed: 4 pins) L3CLOCK_SCL P14 0-5 VDC tolerant I L3DATA_SDA R14 0-5 VDC tolerant I L3 Clock/IIC clock input L3 Data/IIC data input L3MODE_A0 U15 0-5 VDC tolerant I L3 Mode/IIC address selection SELECT_L3_IIC T15 0-5 VDC tolerant I Select pin for L3 (LOW) or IIC control (HIGH) I Test control pin Test pin SSA Audio Codec (fixed: 1 pin) TEST1 T14 0-5 VDC tolerant Supplies SSA Audio Codec (fixed: 2 pins) VDDD(CODEC) N14 Digital supply Audio Codec VSSD (CODEC) U14 Digital ground Audio Codec Supplies SSA Flash memory (fixed: 2 pins) 2002 Jan 21 11 PHILIPS CONFIDENTIAL Philips Semiconductors Preliminary Specification version 1.3 Generic device for portable multimedia applications SAA7750-N1D SAA7750-N1D SYMBOL(1) LFBGA 208 PIN DIGITAL I/O LEVEL APPL. FUNC PIN STATE AFTER RESET DESCRIPTION VDDD(FLASH) E17 Digital supply Flash VSSD (FLASH) F17 Digital ground Flash Digital supplies SAA7750 SAA7750 (fixed: 8 pins) VDDI1 L4 Core supply SAA7750 SAA7750 VSSIS1 L3 Core ground and substrate SAA7750 SAA7750 VDDI2 G4 Core supply SAA7750 SAA7750 VSSI2 G3 Core ground SAA7750 SAA7750 VDDI3 E4 Core supply SAA7750 SAA7750 VSSI3 E3 Core ground SAA7750 SAA7750 VDDI4 C4 Core supply SAA7750 SAA7750 VSSI4 C3 Core ground SAA7750 SAA7750 Peripheral supplies SAA7750 SAA7750 (fixed: 4 pins) VDDE3V3 J4 Peripheral (I/O) supply SAA7750 SAA7750 (3.3V) VSSE3V3 K4 Peripheral (I/O) ground SAA7750 SAA7750 VSSE3V3 H1 Peripheral (I/O) ground SAA7750 SAA7750 VDDE2V5 K14 Peripheral (I/O) supply SAA7750 SAA7750 (2.5V) VSSE2V5 L14 Peripheral (I/O) ground SAA7750 SAA7750 Not connected pins (fixed: 2 pins) NC 1. D15 Not connected Pin positions are fixed. 2002 Jan 21 12 PHILIPS CONFIDENTIAL 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 A GPIO MCI_CLK TEST_DA T MCI_DAT< 0> GPA GPA GPIO GPIO GPIO GPIO GPIO GPIO GPIO UART_nD TR UART_nD CD RW_WR DB B GPIO MCI_CMD TEST_DA T TEST_DA T GPA GPA GPA GPIO GPIO GPIO GPIO GPIO UART_nD SR UART_nC TS E_RD DB DB C GPIO GPIO VSSI4 VDDI4 CRQ_nER D RCK DAAB WSAB CLAB REQ_RX RTRST_n F CSB DB DB VUSB DB USB_DPL US D GPIO GPIO GPIO GPIO CRST_nH RQ CFLAG_S BSF SFSY V4_SUB EFAB UART_DI R_T UART_CL K RS DB DB N.C. USB_CO NNECT USB_DMI N E GPIO GPIO VSSI3 VDDI3 UART_IO_ nF SPDIFO DATAO1 Philips Semiconductors : pinning diagram 1 SAA7750-N1D SAA7750-N1D 2002 Jan 21 Table 2 VDD(F) VSS(F) F GPIO GPIO GPIO GPIO A CLK01 CLK01 WSO1 G GPIO GPIO VSSI2 VDDI2 A DATAI1 nCS_2 VADCP H VSSE nOE SDnCS0 CKE0 A WSI1 A VINM WEN GPA VDDE3V3 A BCKI1 A VADCN DO DI WE WSSE3V3 VDDE2V5 JTAG_nT RST JTAG_TM S VINR WAKE_U P VREFP VSSI1 VDDI1 VSSE2V5 nRESET_I N MODE VDDA(AD) M VSSA4 VDDA4 VREFP GPA BCK01 BCK01 MODE JTAG_MO DE VINL N VSSA3 VDDA3 GPA XTAL2i VDDD RESET RESET_O UT VSSA(AD) P VSSA2 VDDA2 XTAL2O XTAL1I D D D A A A A SCL_SLA VE SCL_M L3CLOCK VOUTL VSSA(DA) VREF R VSSA1 VDDA1 XTAL1O D D A A A A nRAS nCAS SDA_SLA VE SDA_M L3DATA VDD(HP) VOUTR VDDA(DA) T D D D D D D A A A nCS DQM AO_SLAV E JTAG_TDI TEST1 SEL_L3_II C VREFHP VOUTL-H P U D D D D D A A A A nCS DQM JTAG_TC K JTAG_TD O VSSD L3MODE VSS(HP) VOUTR-H P 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 PHILIPS CONFIDENTIAL There is one pin (pin D15) which is left open. Preliminary Specification version 1.3 Note: the pins which which have been changed between the version N1A, N1B, N1C and the final version N1D of the IC have been marked with RED. The pins which were changed and changed from digital to analog are marked with BLUE. Generic device for portable multimedia applications DCLKO L 13 J K Philips Semiconductors Preliminary Specification version 1.3 Generic device for portable multimedia applications SAA7750-N1D SAA7750-N1D 7 HARDWARE DESCRIPTION SAA7750 SAA7750 7.1 ARM720T ARM720T microcontroller Quick reference: · High performance low power ARM7TDMI based 32-bit RISC processor · ARM 16-bit Thumb instruction set · 8 KByte Unified Cache · Memory Management Unit (MMU) giving full virtual memory and fast context switching support · 32-bit register bank · 32-bit ALU for RISC performance · 32-bit shifter · 32-bit addressing (no paging required above 64KByte) · 32 x 8 DSP multiplier for signal processing · Embedded ICE logic for debug · Maximum ARM core clock frequency is 72MHz. 7.1.1 OVERVIEW ARM720T ARM720T is a general-purpose 32-bit microprocessor with 8KB cache, enlarged write buffer and Memory Management Unit (MMU) combined in a single core. The CPU within ARM720T ARM720T is the ARM7TDMI. The ARM720T ARM720T is software compatible with the ARM processor family. ARM720T ARM720T is a fully static part and has been designed to minimize power requirements. This makes it ideal for portable applications, where both these features are essential. The ARM720T ARM720T architecture is based on Reduced Instruction Set Computer (RISC) principles, and the instruction set and related decode mechanism are greatly simplified compared with micro programmed Complex Instruction Set Computers (CISC). The MMU's mixed data and instruction cache, together with the write buffer, substantially raise the average execution speed and reduce the average amount of memory bandwidth required by the processor. This means that there is a minimal performance loss, when using `slow' DRAM and `slow' internal flash memory. The memory interface has been designed to allow the performance potential to be realized without incurring high costs in the memory system. Speed-critical control signals are pipelined to allow system control functions to be implemented in standard low-power logic, and these control signals permit the exploitation of paged mode access offered by industry standard DRAMs. 2002 Jan 21 14 PHILIPS CONFIDENTIAL Philips Semiconductors Preliminary Specification version 1.3 Generic device for portable multimedia applications SAA7750-N1D SAA7750-N1D 7.1.2 BLOCK DIAGRAM Virtual Address Bus MMU 8 KB Cache ARM7TDMI CPU Coprocessor Interface Internal Data Bus Data and Address Buffers Control and Clocking Logic JTAG Debug Interface System Control Coprocessor AMBA Interface AMBA Bus Interface Fig. 2 ARM720T ARM720T Block Diagram 7.1.3 THE THUMB CONCEPT The THUMB instruction set is a subset of the ARM instruction set. The THUMB is designed to increase the performance of ARM implementations that uses a 16-bit memory data bus, and may allow better code density than ARM instruction set. The THUMB set's 16-bit instruction length allows it to approach twice the density of standard ARM code while retaining most of the ARM's performance advantage over a traditional 16-bit processor using 16-bit registers. This is possible because THUMB code operates on the same 32-bit register set as ARM code. THUMB code is able to provide up to 65% of the code size of ARM, and 160% of the performance of an equivalent ARM processor connected to a 16-bit memory system. Note: in standard operation accesses are 32-bit, only when executing via EBI the accesses are 16-bit. 2002 Jan 21 15 PHILIPS CONFIDENTIAL Philips Semiconductors Preliminary Specification version 1.3 Generic device for portable multimedia applications SAA7750-N1D SAA7750-N1D 7.2 Memory controllers TThe SAA7750 SAA7750 offers transparent memory-mapped access for the processor to static memory and SDRAM devices. Refer to the application notes on the memory controller. 7.2.1 OVERVIEW The memory interface consists of an external bus interface (EBI) that handles all data and address interfacing from the SAA7750 SAA7750 to the outside world, and consists of two memory controllers. The first memory controller handles SRAM / ROM. This controller is also known as Static Memory Controller (SMC). The second memory controller handles SDRAM which is located externally. In Fig.3 on page 16 a block diagram of the SAA7750 SAA7750 memory interface is depicted. AHB CD Block Decoder SDRAM Controller External Bus Interface control sel SDRAM TIC address + data SRAM sel Static Memory Controller control Fig. 3 Block diagram of SAA7750 SAA7750 memory interface Note: the SDRAM and the SMC cannot be used together in one application since there is no arbitragion in the EBI to control the priority between the two blocks and the refresh of the SDRAM in that case. 7.2.2 Static Memory Controller Within the memory interface the Static Memory Controller (SMC) is one the controllers which communicates with the External Bus Interface (EBI). This static memory controller can control up to four independent memory or expansion banks simultaneously. Those memories can be SRAM, ROM, FLASH or off-chip located peripherals. Each bank is 64 MByte, where the Static Memory Controller can handle all of the six main functions: · Memory bank selection: support of 8 memory banks (64MByte each) · Little Endian system · Programmable wait states for read and write access: ­ 1.32 wait states for standard memory access ­ 0.15 wait states for burst mode reads from ROMs · Supports sequential access burst reads of up to four consecutive locations in 8-, 16-, or 32-bit memories · byte lane write control 2002 Jan 21 16 PHILIPS CONFIDENTIAL Philips Semiconductors Preliminary Specification version 1.3 Generic device for portable multimedia applications SAA7750-N1D SAA7750-N1D · external bus interface 7.2.3 SDRAM Interface Controller The SDRAM interface also known as Dynamic Memory Controller (DMC) has one port connection which is connected to the AHB system bus. This connection interfaces to the main SDRAM control engine and the External Bus Interface. The SDRAM control engine generates an efficient sequence of commands, to issue to the SDRAMs to transfer the requested data. A block diagram of the memory interface is depicted in Fig.3 on page 16 . The SDRAM controller provides the following features: · Support for four banks of external SDRAM · The width of each SDRAM bank can be either 8 or 16 bits · Fast page-mode access support · Byte, half word and word transaction support · SDRAM refresh controller using CAS-before-RAS (CBR) refresh, hidden refresh or RAS-only refresh · Auto pre-charge SDRAM accesses · Shutdown mode where all SDRAM accesses (including refresh) are disabled. This state is compatible with self-refresh devices. · Power down mode where all SDRAM accesses are disabled and all SDRAM control lines are driven low. This mode can be used to remove supply power from the SDRAM devices. 7.2.4 Internal Memory Controller The internal memory is made up of two units, a bank of SRAM and one bank of ROM. The internal memory controller allows the wait states of the SRAM and ROM to be controlled. Embedded SRAM: · 64KByte embedded SRAM (16K x 32) · Supports byte, half-word and word access. Embedded ROM: · 256KByte embedded program ROM (64K x 32) 7.2.5 FLASH MEMORY CONTROLLER The FLASH memory controller takes care of programming, erasing and reading the internal 384 KB FLASH memory. 7.2.5.1 FLASH reads Any reads from the FLASH via the AHB will be handled automatically by the slave interface using the programmed number of wait states from the `RdWaitCycles' of the FLASHWS register. If the FLASH interface is in write mode when the AHB FLASH read is attempted then an abort will be generated. This means that the FLASH can't be programmed when the CPU is running code from FLASH. The default mode is FLASH read, with 8 wait states. Any writes to this area of the SSA memory map will generate an abort. 2002 Jan 21 17 PHILIPS CONFIDENTIAL Philips Semiconductors Preliminary Specification version 1.3 Generic device for portable multimedia applications SAA7750-N1D SAA7750-N1D 7.2.5.2 Erasing the FLASH block Erasing (part) of the flash is necessary if the FLASH already contains data on the location that needs to be written. Erasing can be done in two ways: sector erase and mass erase. 7.2.5.3 Programming the FLASH block Before writing words into the FLASH, ensure that the respective addresses are empty (erased). Writing to a non-empty address will result in invalid data on that location. 7.2.5.4 Operating conditions Reading from the FLASH ROM can be done at any AHB speed. The number of programmed wait states is: 42 ns/ , rounded upwards. The number of CPU cycles for each read is 1+ The maximum bus speed for programming and erasing the FLASH is 48 Mhz; A Mass erase takes 101 ms at this speed A Sector erase takes 21 ms at this speed Programming a word takes 41 us at this speed The minimum bus speed for programming is 24 Mhz.Programming/erasing at 24 Mhz takes twice as long as programming at 48 Mhz. The maximum time a sector can be accessed in write mode is 60 ms. If this is more, the data in this sector can be corrupted. Software must take care not to exceed this value. Using speed optimized code for FLASH-writes is recommended to keep programming time as short as possible. 7.3 Interrupt Controller Refer to the application note "Interrupt handling SAA7750 SAA7750". OVERVIEW The interrupt controller has the following features: 1. Status information about the interrupt source. 2. Separate enabling and disabling of interrupt sources. 3. Polarity and mode (edge/level) controlled interrupt source. 4. Software programmable FIQ/IRQ interrupt source. 7.3.1 FUNCTIONAL DESCRIPTION The interrupt controller provides a simple software interface to the interrupt system. Certain interrupt bits are defined for the basic functionality required in any system, while the remaining bits are available for use by other devices in any particular implementation. The ARM720T ARM720T processor within the SAA7750 SAA7750 supports two levels of interrupts: 1. FIQ (Fast Interrupt Request) for fast, low hardware latency interrupt handling. 2. IRQ (Interrupt Request) for more general interrupts. For the FIQ only a single source should be in use at any particular time. This interrupt provides a true low-latency interrupt, because a single source ensures that the interrupt service routine may be executed directly without the need to determine the source of the interrupt. It also reduces the interrupt latency because the extra banked registers within 2002 Jan 21 18 PHILIPS CONFIDENTIAL Philips Semiconductors Preliminary Specification version 1.3 Generic device for portable multimedia applications SAA7750-N1D SAA7750-N1D the ARM720T ARM720T core, which are available for FIQ interrupts, may be used to maximum efficiency by preventing the need for a context save. For SAA7750 SAA7750 a multiple FIQ will be used to have more flexibility without a great loss of latency. The IRQ interrupt controller uses a bit position for each different interrupt source. Bit positions are defined for sources like, communication channels, timers, clock, etc. shared in different IRQ registers. The interrupt controller is not based on hardware priority or does not provide any kind of interrupt vectors, because these functions can be provided in the software. 7.4 Power Management Unit (PMU) The Power Management and Reset Unit contains logic and registers used to support power management and to control the reset behaviour of SAA7750 SAA7750. The power management mode can be divided into: · Operating mode · Stand-by mode · Power down mode The Power Management Unit can take care off a proper power-up and power-down sequence under software control. All peripherals are controlled by the CPU. The CPU will request a power-down of a certain peripheral. After power-down the PMU will acknowledge the power-down request to the ARM. To power-up a device, the ARM will request this to the PMU. The PMU takes care of the sequence and as soon as the peripheral is ready to receive data, the PMU will acknowledge the ARM for having a powered up peripheral. If all peripherals are in powered down, including the ARM itself (power-down mode), the system can be wake-up via the PMU. As soon as an external interrupt occurs, a wake-up signal is asynchronously send to the PMU. This causes the PMU the enable all clocks of all peripherals and the clock of the CPU followed by generating an interrupt to the interrupt controller. The CPU will return to the last entered mode and all peripherals which aren't used in this specific mode can be disabled on request by the CPU. 7.4.1 FUNCTIONAL DESCRIPTION The Power Management Unit can be divided into 5 main modules (Fig.4), clock generation module, register module, clock block, reset module and the power down module. The clock generation module serves all the derived clocks from the two master input clocks with internal PLL modules. All the outputs are controlled by the clock register module to enable or disable clocks in the main system. After selecting the clocks, the clock block takes care of hardwired overruling (enabling/disabling) which is only needed in testmode or evaluation modes. The reset module controls the resetting of blocks in the right way. The power down module controls the request/acknowledge mechanism to the CPU and can control the clock register as well, e.g. switching modules in a certain sequence. The register module takes care that the arm can write and read to the registers. 2002 Jan 21 19 PHILIPS CONFIDENTIAL Philips Semiconductors Preliminary Specification version 1.3 Generic device for portable multimedia applications SAA7750-N1D SAA7750-N1D Clock Block EXAMPLE OF SOME OF THE CLOCKS Clock Generation OSC_6MHz HCLK PLL ARM_PWD PLL OSC_32KHz & PWD_HCLK_ARM D PLL > HCLK_ARM > 1 TST_CLK Q HCLK_* TCB_TEST_CLK_SEL CP CONTROL_DIS & TCB_DIS_HCLK_ARM 1 DIS_CLK_REG TCB_CCTM_SEL HCLK Registers *_PWD & PWD_HCLK_* 1 TST_CLK Q D APB-bus TCB_TEST_CLK_SEL CP CONTROL_DIS & TCB_DIS_HCLK_* DIS_CLK_REG 1 TCB_CCTM_SEL DSPCLK *_PWD & PWD_DSPCLK_* PowerDown module Reset module D wake-up TST_CLK Q interrupts CONTROL_DIS > 1 DSPCLK_* TCB_TEST_CLK_SEL CP & TCB_DIS_DSPCLK_* DIS_CLK_REG 1 TCB_CCTM_SEL Fig. 4 PMU Block schematic 7.4.2 WAKE-UP BEHAVIOUR If the system is setup properly, all the clocks can be shutdown. In this state the SAA7750 SAA7750 does consume minimum power. Only the RTC is running (if enabled). The asynchronous part of the GPIO can receive a wake-up signal. This will trigger the PMU to enable all clocks and to generate a wake-up interrupt to the ARM. The ARM should read the interrupt register to determine that there was a wake-up interrupt. Related to this interrupt, the ARM needs to read the GPIO interrupt register to determine who woke up the ARM and to handle the corresponding request. The following peripherals can wake-up the complete system: · GPIO pins (15:0), and GPIO pins (20,21,22,25,26) · IIC slave interface · External wake-up pad · RTC Alarm · CD-Block decoder · Uart · Remote control · USB interface 7.4.3 WATCHDOG BEHAVIOUR The watchdog has the functionality of resetting the complete system due to an external disturbance. In that case, it is unknown which peripherals caused the lock, so the complete system needs a reset. In normal mode, the ARM will rewrite 2002 Jan 21 20 PHILIPS CONFIDENTIAL Philips Semiconductors Preliminary Specification version 1.3 Generic device for portable multimedia applications SAA7750-N1D SAA7750-N1D the watchdog timer before it has timed out. As soon as the ARM is unable to rewrite the counter, the watchdog will request a reset to the PMU. The PMU will reset the complete system, including all the peripherals and switch on all the clocks. The power-on-reset (POR) bit will not be set and a watchdog request bit is set in the PMU. There is no interrupt generated, because the interrupt controller has been reset. 7.4.4 PAUSE BEHAVIOUR The pause behaviour is implemented as part of the standby mode. By enabling this bit, it is possible to keep all the peripherals running and just prevent the ARM fetching instructions out of the memory. The pause can be retrieved by either pressing the hardware reset or if any peripheral generates an interrupt (and the interrupt is enabled). The interrupt controller will generate an IRQ or FIQ interrupt which is routed to both the ARM and PMU. The PMU will release the pause bit and the ARM will start with the corresponding interrupt handler. 7.5 Reset module Using the MODE and MODE pins, the boot mode of the SAA7750 SAA7750 can be set accoring to the following settings: Table 3 MODE MODE DESCRIPTION 0 Download mode => can be used for debugging 0 1 start executing from INTERNAL FLASH memory after initialisation and Remap according to the internal ROM boot code 1 0 start executing from EXTERNAL ROM memory after initialisation and Remap according to the internal ROM boot code 1 7.6 0 1 NO Remap will be done Oscillators and clock generation Refer to the application note "Clock and PLL settings in the SAA7750 SAA7750". 7.6.1 Overview clock generation module The clock generation module contains logic for generating all clock signals required in SAA7750 SAA7750. The clock generation module consists of oscillators, PLL-based system clock synthesizers and dividers for generating several different clock signals required by the other internal modules and a clock multiplexer to select between the generated clock from the different inputs. The clock generation module is controlled by the PMU registers for enabling/disabling clocks, PLL settings and clock selection control. 7.6.2 Functional Description The clock generator contains two oscillators, one oscillator of 32.768kHz (for real time clock) and one oscillator of 6 MHz. These oscillators are the base frequency for generating the rest of the main system frequencies. Other system clocks will be generated by three PLL's: · One MASTER PLL to generate the clock frequency of 96MHz/48MHz/24MHz/12MHz and · One Audio PLL to generate the 256fs and 128fs clock with the sample frequency's 64kHzor 88.2kHz or 96 kHz. These frequency's can be divided by 1, 2, 4 or 8 to get other audio frequency(32kHz, 16kHz, 8kHz or 44.1kHz, 22.05kHz, 11.025kHz or 48kHz, 24kHz, 12kHz). 2002 Jan 21 21 PHILIPS CONFIDENTIAL Philips Semiconductors Preliminary Specification version 1.3 Generic device for portable multimedia applications SAA7750-N1D SAA7750-N1D · One DSP PLL to generate other clock frequency for the ARM core or DSP core in the range from 8.5Mhz to 133MHz The clock mux is a multiplexer which select depending on the control signals which of the input clock will be connected to the output clock. The register block takes care that the ARM can control what the frequency of the ARM, DSP and audio part will be and what will be the source of the clock signals. Note: the maximum speed of teh ARM core is 72MHz. The maximum frequency of the bus-clock and memory interface bus is up to 48MHz. 7.7 Multi Media Card Interface (MMC) The Multimedia Card Interface (MCI) is an advanced microcontroller bus architecture (AMBA) compliant peripheral. The multimedia card system provides communications and data storage, and consists of: · A multimedia card stack. This can consist of up to 30 cards on a single physical bus. · A multimedia card controller: This is the multimedia card master, and provides an interface between the system bus and the multimedia card bus. The multimedia cards are grouped into three types according to their function: · Read Only Memory(ROM) cards, containing a preprogrammed data. · Read/Write(R/W) cards, used for mass storage. · Input/Output(I/O) cards, used for communication. The multimedia card system transfers commands and data using three signal lines: · CLK: One bit transferred on both command and data lines with each clock cycle. The clock frequency varies between 0 MHz and 20 MHz. · CMD: Bidirectional command channel that initializes a card and transfers commands. CMD has two operational modes, first mode `open drain' for initialization and second mode `push-pull' for command transfer. · DAT: Bidirectional data channel, operating in push-pull mode. 7.7.1 Choice of flash memory cards There are two different types of FLASH memory: NAND FLASH and NOR FLASH. The two FLASH types lend themselves to different applications. Basically NOR FLASH is a replacement for EPROM. NAND FLASH is a magnetic media replacement, particularly suited to serial data. Today's FLASH cards are give in the table below. 2002 Jan 21 22 PHILIPS CONFIDENTIAL Philips Semiconductors Preliminary Specification version 1.3 Generic device for portable multimedia applications SAA7750-N1D SAA7750-N1D Table 4 Available FLASH Cards. INTERFACE SIZE Solid State Floppy Disk Card (SSFDC) or SmartMedia Card FLASH CARD Toshiba & Samsung VENDOR 2.7-3.6V and 5V VCC .32 MByte available 64 MByte Q2 1999 CAPACITY DOS file system ATA (22-pins) 37 x 45 x 0.76 SAA7750 SAA7750 EBI Multi Media Card (MMC) Hitachi Ltd. & Infineon Technologies (open standard) 2.7-3.6V 16 MByte available 32 MByte Q3 1999 64 MByte 2000 128 MByte 2001 SPI (7-pins) 32 x 24 x 1.40 MMC interface Memory Stick (MS) Sony (license needed) 2.7-3.6V .8 MByte available 16 MByte Q2 1999 Serial (10-pins) 50 x 21.5 x 2.8 no Compact Flash Card (CFC) SanDisk Corp. 3.3V/5V tolerant .64 MByte available DOS file system ATA (50-pins) 42 x 36 x 3.3 no The Pinning of the Multi Media Card is given in table 5 Table 5 Pinning of the Multi Media Card (3 pins) PIN SYMBOL A4 MCI_DAT Data A2 MCI_CLK Clock B2 MCI_CMD Command/Response 7.8 DESCRIPTION 10-bit ADC Refer to the apllication note "the build-in 10 bits ADC of the SAA7750 SAA7750". OVERVIEW This section specifies the ADC interface, which can be used e.g. for observing battery voltage and/or scanning resistive key's. The interface can be divided into 2 main modules, a 10 bit A/D converter and an ADC controller/multiplexer. The A/D converter is a 10 bit successive approximation analog to digital converter. The basic characteristics of the ADC interface module are: · Eight analog input channels, selected by an analog multiplexer; · Programmable ADC resolution from 2 to 10 bits; Converted digital values are stored in a 2 * 10 bits register; · Maximum conversion rate is 400Ksamples/s in 10bits accuracy and 1500Ksamples/s in 2 bits accuracy mode. · Single A/D conversion scan mode and continuous A/D conversion scan mode; · Power down mode. 7.8.1 FUNCTIONAL DESCRIPTION The ADC is able to convert on of its 8 inputs from analog to digital in 10 bits with a conversion rate of 400Ksampls/s . The resulution can be reduced till 2 bits and in that case the conversion speed can be increased to 1500Ksamples/s. The ADC is composed of an analog 8:1 multiplexer to select the input to convert. One 10 bits conversion requires 11 ADC clock cycles to complete. During the first cycle the selected input is sampled, in the next 10 cycles the sample is converted into 10 bits. 2002 Jan 21 23 PHILIPS CONFIDENTIAL Philips Semiconductors Preliminary Specification version 1.3 Generic device for portable multimedia applications SAA7750-N1D SAA7750-N1D 7.8.2 MULTI CHANNEL A/D CONVERSION SCAN Associated to each analog input channel is a set of two 10 bits result registers for storage of A/D conversion result. It is programmable which channels are included and which channels are excluded from the A/D conversion scan process. The A/D conversion scan process can be started by software. There are two scan modes, `Continuous Scan' mode and `Single Scan' mode: · In `Continuous Scan' mode, A/D conversion scans are carried out continuously: once one scan completed, the next one is started automatically. · In `Single Scan' mode, only a single conversion scan is carried out, the next scan must be started explicitly by software. 7.8.3 ADC RESOLUTION The resolution within the AD conversion process is software programmable through ADC controller variables. The resolution can be adjust between 2 and 10 bits. The conversion rate is computed as follows: clockfrequency conversionrate = -( resolution + 1 ) 7.8.4 INTERRUPTS The ADC interface implements one interrupt, a scan interrupt which indicates the completion of an A/D conversion scan process and the validity of the data in the result registers. 7.9 UART The UART can be used for connecting a Modem, Blue tooth IC or a terminal emulator to the SAA7750 SAA7750 IC. Overview: · 16 word wide transmit and receive FIFO's · Supports external modem peripheral · Optional interface to external Philips Smartcard · Build-in IrDA receiver 7.9.1 FUNCTIONAL DESCRIPTION The receiver block, Rx, monitors the serial input line, SIN, for valid input. The Rx Shift Register (RSR) accepts valid characters via SIN. After a valid character is assembled in the RSR, it is passed to the Rx Buffer Register FIFO to await access by the CPU or host via the generic host interface. The transmitter block, Tx, accepts data written by the CPU or host and buffers the data in the Tx Holding Register FIFO (THR). The Tx Shift Register (TSR) reads the data stored in the THR and assembles the data to transmit via the serial output pin, SOUT. The Baud Rate Generator block, BRG, generates the timing enables used by the Tx block. The BRG clock input source is either the APB clock, PCLK, or the UART clock, UCLK. The main clock is divided down per the divisor specified in the DLL and DLM registers. This divided down clock is a 16x oversample clock, NBAUDOUT. 2002 Jan 21 24 PHILIPS CONFIDENTIAL Philips Semiconductors Preliminary Specification version 1.3 Generic device for portable multimedia applications SAA7750-N1D SAA7750-N1D The modem interface contains registers MCR and MSR. This interface is responsible for handshaking between a modem peripheral and the UART. The interrupt interface contains registers IER and IIR and controls the interrupt output pin, INTR. The interrupt interface receives several one clock wide enables from the Tx, Rx and modem blocks. Status information from the Tx and Rx is stored in the LSR. Control information for the Tx and Rx is stored in the LCR. The build-in IrDA block can be enabled or disabled. If disabled, the UART signals pass through this block unchanged . The build-in IrDA block operates over the entire range of 2.4kb/s up to 115.2kb/s. 7.10 General Purpose I/O The General Purpose Input-Output (GPIO) module provides 16 external GPIO pins which can be independently programmed to be input or output. This means that each pin has a data input/output bit, a data direction bit and a value bit. The GPIOs can be used e.g. like push-buttons and detection switches. · A maximum of 28 General Purpose pins externally · Each General Purpose pin has an interrupt which can be dynamically configured: ­ active high or low polarity ­ edge or level sensitive ­ masked or enabled 7.10.1 FUNCTIONAL DESCRIPTION Interrupt Controller APB SelGPIO GPIO_IRQ GPIO_FIQ HclkGPIO_INT APB GPIOController SelGPIO 32 32 32 HclkGPIO 2002 Jan 21 25 GPIO_out Lines GPIO_IN Lines GPIO_Enable PHILIPS CONFIDENTIAL Philips Semiconductors Preliminary Specification version 1.3 Generic device for portable multimedia applications SAA7750-N1D SAA7750-N1D The GPIO module consists of two parts: The GPIO controller which functions as an input/output interface to the GPIO lines, and an interrupt controller which checks the GPIO-lines for level and/or edge changes and generates an interrupt to the CPU. 7.10.2 INTERRUPTS Refer to the application note "Interrupt handling SAA7750 SAA7750". Each GPIO line can be configured to generate interrupts either as an FIQ or an IRQ. They can be level or edge sensitive and either low/high active or Positive/negative edged. The interrupt controller contains a raw status register where each GPIO line can be checked for an interrupt, independent of masking. It contains a Status register, which contains the values after masking. 7.11 Real Time Clock (RTC) · Measures passage of time to maintain calendar and clock · Uses external 32.768kHz crystal · Counts seconds, minutes, hours, days, and years with leap year correction · Counter increment interrupt · Alarm clock interrupt The Real-Time Clock (RTC) module consists of a counter which increments at a frequency of typically 32.768kHz. The RTC provide a set of counters to measure time during power on and power off operation. It is designed to use little power consumption in power down mode. 7.11.1 FUNCTIONAL DESCRIPTION The RTC interfaces to a standard APB with either a unidirectional or bidirectional data bus. The data bus is 32-bits wide while the consolidated time registers are included to read all time counters with only three read operations. The RTC uses a 32.768 kHz clock, that is divided down to a 1 Hz clock using a ripple counter. A ripple counter is used to minimize power during power down mode. The counter clock consists of the exclusive-or of the 1 Hz clock and the counter write strobe. During a non-write operation the counters operate as a set of sequential counters clocked by the 1 Hz clock. During a write operation no event is allowed on the 1 Hz clock. To insure this condition is true the user should disable the 1 Hz clock by setting the clock enable bit (CR[0]) to zero before writing to the RTC. Each counter has its count enable gated so that during a counter write operation no counter is increment by the clock pulse generated by the write strobe. Two of the counters have dynamic maximum values, the Day of Month counter and the Day of Year counter. These maximum values are determined via combinational logic whose inputs are the Year counter (for leap year) and Month counter. For determining a leap year, the RTC does a simple bit comparison to see if the two lowest order bits of the year counter are zero. If true, then the RTC considers that year a leap year. A more accurate algorithm would prevent years evenly divisible by 100, but not evenly divisible by 400, from being leap years (the year 2000 is a leap year, but 2100 is not). The RTC considers all years evenly divisible by 4 as a leap year. This algorithm will be accurate until the year 2100. 2002 Jan 21 26 PHILIPS CONFIDENTIAL Philips Semiconductors Preliminary Specification version 1.3 Generic device for portable multimedia applications SAA7750-N1D SAA7750-N1D 7.11.2 INTERRUPTS Interrupt generation is controlled through the Counter Increment Interrupt Register (CIIR), the alarm registers, and the Alarm Mask register (AMR). Interrupts are generated only by the transition into the interrupt state. Each bit in CIIR corresponds to one of the time counters. If CIIR is enabled for a particular counter, then every time the counter is increment an interrupt is generated. The alarm registers allow the user to specify a date and time for an interrupt to be generated. The AMR provides a mechanism to mask alarm compares. If all non-masked alarm registers match the value in their corresponding time counter, then an interrupt is generated. 7.11.3 POWER DOWN OPERATION When the external signal pwr_up is active low the RTC goes into power down mode. In power down mode all bus interface inputs are gated. Besides the first element in the ripple counter, and the optional alarm clock sampling flip flop, all loads to the 32.768 KHz clock are gated to reduce power. The user can optionally specify that the alarm compare interrupt output should remain active in power down mode to allow for a power-on timer. If this option is selected, the alarm registers are included in the low power section of the design. When powered down, the synchronizing clock for alarm comparison will be the 1 Hz clock. When powered up, the bus clock is used to synchronize the alarm. 7.12 Timers · Two independent 32-bit timers · Can be programmed to interrupt the processor · Can operate in either free running or periodic timer mode The timer block contains two fully independant timers, where each timer has its own clock and chip-select. Each timer is a 32 bit wide down-counter with selectable pre-scale. The pre-scaler allows either the system clock to be used directly, or the clock divided by 16 or 256 may be used. This is provided by 0, 4 or 8 stages of pre-scale. Two modes of operation are available, free-running and periodic timer. In periodic timer mode the counter will generate an interrupt at a constant interval. In free-running mode the timer will overflow after reaching its zero value and continue to count down from the maximum value. Note: The timer speed depends on the system clock. The system clock can change depending the operation mode, which means that the timer can not be used as a real time clock. 7.12.1 FUNCTIONAL DESCRIPTION The timer is loaded by writing to the Load register and then, if enabled, the timer will count down to zero. On reaching a count of zero an interrupt will be generated. The interrupt may be cleared by writing to the Clear register. After reaching a zero count, if the timer is operating in free-running mode then the timer will continue to decrement from its maximum value. If periodic timer mode is selected then the timer will reload from the Load register and continue to decrement. In this mode the timer will effectively generate a periodic interrupt. The mode is selected by a bit in the Control register. At any point the current timer value may be read from the Value register. At any point the timer_load may be re-written. This will cause the timer to restart to the timer_load value. the timer is enabled by a bit in the control register. At reset the timer will be disabled, the interrupt will be cleared and the Load register will be undefined. The mode and pre-scale value will also be undefined. 2002 Jan 21 27 PHILIPS CONFIDENTIAL Philips Semiconductors Preliminary Specification version 1.3 Generic device for portable multimedia applications SAA7750-N1D SAA7750-N1D The timer clock is generated by a pre-scale unit. The timer clock may be the system clock, the system clock divided by 16, which is generated by 4 bits of pre-scale, or the system clock divided by 256, which is generated by a total of 8 bits of pre-scale. 7.12.2 INTERRUPTS The timer is loaded by writing to the Load register and then, if enabled, the timer will count down to zero. On reaching a count of zero an interrupt will be generated. The interrupt may be cleared by writing to the Clear register 7.13 Watchdog Timer The watchdog block is of similar design to the existing timer block, except that in stead of interrupting the CPU, it provides a reset request to the PMU and that it consists of only one timer. Once the watchdog is enabled, it will monitor the programmed timeout period and generate a reset request when the period expires. In normal operation the watchdog is triggered periodically, resetting the watchdog counter and ensuring that no reset is generated. In the event of a software or hardware failure preventing the CPU from triggering the watchdog, the timeout period will be exceeded and a reset requested from the PMU/reset control logic. The reset request allows the PMU to select a default set of clocks, and reset the CPU subsystem. 7.13.1 FUNCTIONAL DESCRIPTION The functional description is the same as that of the timer block. Mind that the watchdog only contains one timer! 7.13.2 INTERRUPTS The watchdog timer is loaded by writing to the Load register and then, if enabled, the timer will count down to zero. On reaching a count of zero an interrupt will be generated to the PMU. 7.14 IIC master Interface I2C The master module provides a serial interface that meets the I2C bus specification and supports all transfer modes from and to the I2C bus. It supports the following functionality: · It supports both the normal mode (100 kHz SCL) and the fast mode (400 kHz SCL). · It has word (32-bits) access from the CPU side. · Interrupt generation on received or sent byte (and some special cases). · It has two modes of operation: master transmitter and master receiver. · 16 8bits word wide transmit and receive FIFO's Important note: since 2 pins of the master IIC interface are shared with the pins of the CD-block decoder UART, the IIC master interface cannot be used in cases in which the CD-block decoder UART is used! 7.14.1 FUNCTIONAL DESCRIPTION The main features of the I2C-bus are: · Serial clock synchronization allows devices with different bit rates to communicate via one serial bus 2002 Jan 21 28 PHILIPS CONFIDENTIAL Philips Semiconductors Preliminary Specification version 1.3 Generic device for portable multimedia applications SAA7750-N1D SAA7750-N1D · Serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer · The I2C bus may be used for test and diagnostic purpose Two wires, SDA (serial data) and SCL (serial clock) carry information between devices connected to the I2C bus. Each device can operate as either a transmitter or receiver, depending on the function of the device. In addition to transmitters and receivers, devices can also be considered as masters or slaves when performing data transfers. A master is the device which initiates a data transfer on the bus and generates the clock signals to permit that transfer. Any device addressed by a master is considered a slave. Generation of clock signals on the I2C bus is always the responsibility of the master device; each master generates its own clock signals when transferring data on the bus. Bus clock signals from a master can only be altered when they are stretched by a slow-slave device holding down the clock line, or by another master when arbitration occurs. 7.14.2 INTERRUPT Active low signal indicates if an interrupt is pending. The reason for the interrupt is encoded in Status Register. There are several possible interrupt types: transfer completed, arbitration failure, missing acknowledge, need more data, Tx FIFO has room for more data, or data has been received. 7.15 IIC slave Interface I2C The Slave module provides a serial interface that meets the I2C bus specification and supports all transfer modes from and to the I2C bus. It supports the following functionality: · It supports both the normal mode (100 kHz SCL) and the fast mode (400 kHz SCL). · It has word (32-bits) access from the CPU side. · Interrupt generation on received or sent byte (and some special cases). · It has two modes of operation: slave transmitter and slave receiver. 7.15.1 FUNCTIONAL DESCRIPTION The main features of the I2C-bus are: · Serial clock synchronization allows devices with different bit rates to communicate via one serial bus · Serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer · The I2C bus may be used for test and diagnostic purpose Two wires, SDA (serial data) and SCL (serial clock) carry information between devices connected to the I2C bus. Each device can operate as either a transmitter or receiver, depending on the function of the device. In addition to transmitters and receivers, devices can also be considered as masters or slaves when performing data transfers. A master is the device which initiates a data transfer on the bus and generates the clock signals to permit that transfer. Any device addresses by a master is considered a slave. Generation of clock signals on the I2C bus is always the responsibility of the master device; each master generates its own clock signals when transferring data on the bus. Bus clock signals from a master can only be altered when they are stretched by a slow-slave device holding down the clock line, or by another master when arbitration occurs. 2002 Jan 21 29 PHILIPS CONFIDENTIAL Philips Semiconductors Preliminary Specification version 1.3 Generic device for portable multimedia applications SAA7750-N1D SAA7750-N1D 7.15.2 INTERRUPT Active low signal indicates if an interrupt is pending. The reason for the interrupt is encoded in Status Register. There are several possible interrupt types: transfer completed, arbitration failure, missing acknowledge, need more data, Tx FIFO has room for more data, or data has been received. 7.16 LCD Interface The LCD interface contains logic to interface to a 6800/8080 compatible LCD controller. The LCD interface is compatible with the 6800 bus standard and the 8080 bus standard, with one address pin (RS) for selecting the data or instruction register. The LCD interface contains a couple of options to delay the access on the 6800/8080 bus, if the specific controller requires it. 7.16.1 INTERFACE · 8/4 bit parallel interface mode: 6800-series, 8080-series · Supports multiple frequencies for the 6800/8080 bus, to support high and low speed controllers · Supports a maximum of 16 wait states on lcd-bus actions · Supports polling the busy flag from LCD controller to off-load the CPU from polling · Contains an 16 byte FIFO for sending control and data information to the LCD controller · Contains a serial interface which uses the same FIFO for serial transmissions. · Contains maskable interrupts. 7.16.2 Table 6 SYSTEM INTERFACE Various modes of the LCD interface PS Bus mode (L) MI IF CSB RS RW_W R E_RD DB0-3 DB4- DB5 DB6 DB7 6800-ser 8 bit (L) ies (H) 4 bit (H) CSB RS nR/W E DB0-3 DB4 DB5 DB6 DB7 CSB RS nR/W E * DB4 DB5 DB6 DB7 8080-ser 8 bit (L) ies (L) 4 bit (H) CSB RS nWR nRD DB0-3 DB4 DB5 DB6 DB7 CSB RS nWR nRD * DB4 DB5 DB6 DB7 CSB RS * * * * SCL SI SO Serial mode (H) * * Note: 1. * Don't care ("High", "Low" or "Open") PS = Parallel/Serial mode CSB = Chip Select. Default low active IF = 4 or 8-bit mode MI = Motorola/Intel mode RS = Register Select (also seen as A0) 2002 Jan 21 30 PHILIPS CONFIDENTIAL Philips Semiconductors Preliminary Specification version 1.3 Generic device for portable multimedia applications SAA7750-N1D SAA7750-N1D E_RD = Enable / Read. Enable in 6800 mode, Read in 8080 mode. RW_WR = ReadWrite / WRITE. Read/write in 6800 mode, Write in 8080 mode. DB(7-0) = Data Bus. SCL = Serial CLock. SI = Serial Input. SO = Serial Output. 7.16.3 RESETTING THE LCD CONTROLLER Not all LCD controllers require a reset pin to reset the controller. In some cases a simple instruction to the controller is enough to perform the reset. A GPIO pin, or maybe the system reset can be used to act as a reset signal for the LCD controller, if it requires a hardware reset pin. 7.16.4 OPERATIONAL MODES The LCD_interface has three modes for outputting data: Byte-mode, 4-bit mode and serial-mode. Byte mode: At each shift of the FIFO, the last byte from the FIFO will be put on the data pins, and pin RS will indicate if the data is an instruction or data value. In read mode the data on pins DB_IN 7-0 will be sampled by the LCD_interface. 4-bit mode: At each shift of the FIFO, the last byte from the FIFO will be split, where the order depends on the `MSB_first' from the control register. When set to `1', bit 7-4 from the FIFO byte will be put first, or read first, at the data pins, and then bit 3-0. When set to `0' bits 3-0 will be written or read first, and then bits 7-4. 7.16.5 SERIAL MODE: At each shift of the FIFO the last FIFO byte will be split in 8 separate bits and be put on data pin 7, where the order depends on the `MSB_first' from the control register. When set to `0', then first bit 0 and last bit 7 will be written or read first, else the order is from 7 downto 0. Signal RS is included for each 8 bits and indicates a instruction or data. Not all controllers require this signal in serial mode, but can be used if required. 7.16.6 LOOPBACK MODE Setting the register `LOOPBACK' of the CONTROL register to `1', will set the LCD interface in loopback-mode. Internally, the LCD data output is connected to the LCD data input. The programmer can test correct behaviour of the LCD interface, by doing the following: · Place the LCD interface in parallel, 8-bit mode · Write a single byte to the LCD_DATA_BYTE register · Write `0x01' to the LCD_READ_CMD register to request a bus read · Poll the status bit, or wait for the `valid' interrupt (if MASK is cleared) · If valid, read the byte from LCD_DATA_BYTE register · Compare this value with the written value 2002 Jan 21 31 PHILIPS CONFIDENTIAL Philips Semiconductors Preliminary Specification version 1.3 Generic device for portable multimedia applications SAA7750-N1D SAA7750-N1D 7.16.7 INTERRUPT An interrupt is generated on the following occasions: · When the FIFO is empty (LCD_FIFO_EMPTY). · When the FIFO is half empty. (LCD_FIFO_HALF_EMPTY) · When the FIFO is overrun. (LCD_FIFO_OVERRUN) · When the requested instruction/data register is valid. (LCD_READ_VALID) Any of these interrupts can be masked individually to keep them from generating an interrupt to the CPU, by using the LCD_INT_MASK register. The interrupts after masking can be read in the LCD_STATUS register. Writing a `1' in the mask register will mask the interrupt. The status of the interrupts without masking can be read in the `LCD_INT_RAW' register Clearing the interrupts: An interrupt can be cleared by writing a `1' to the respectable bit in the LCD_INT_CLR register. If the interrupt has not been solved, for instance the FIFO is still empty, this will re-set the interrupt, when not masked. 2002 Jan 21 32 PHILIPS CONFIDENTIAL Philips Semiconductors Preliminary Specification version 1.3 Generic device for portable multimedia applications SAA7750-N1D SAA7750-N1D 7.17 Remote Control Interface The remote control build into the SAA7750 SAA7750 is based on the discharge of a RC combination. Making different RC combinations, key's can be identified. Key interface - Consists of DO and DI signals. The key interface consists of an output pin, DO, which is a signal of high and low periods, similar to a clock. Output pin, DO, when low, is used to discharge an RC network. Input pin, DI, is sampled by the block to determine the time DI remains low. NOTE: A sample is the time DI pin i s low. Normally DO is used to discharge a RC network. DO going low will discharge the Capacitor and the time it takes to recharge is monitored by DI. 7.18 7.18.1 USB Interface OVERVIEW The SAA7750 SAA7750 USB interface can be used for: · Down load bulk audio data (compressed) from a PC to the application with the SAA7750 SAA7750 · Download new firmwarde from a PC into the build-in program FLASH · Up load speech or audio from a (analog) source to a PC 7.18.2 FUNCTIONAL DESCRIPTION The USB interface for SAA7750 SAA7750 is a full speed USB interface (12Mbits/s) and is USB 1.1 compliant. It consist of an analog transceiver (ATX), and a Full Speed USB module (FS22). · USB 1.1 compliant interface · Supports bus-powered or self-powered operation (programmable) · One full duplex control end points (8 bytes) · Two full duplex interrupt end points (16 bytes) · One full duplex bulk end point (64 bytes, double buffered) · One full duplex isochronous end point (294 bytes, double buffered) 2002 Jan 21 33 PHILIPS CONFIDENTIAL Philips Semiconductors Preliminary Specification version 1.3 Generic device for portable multimedia applications SAA7750-N1D SAA7750-N1D USB_Vbus USB_Vbus 3.3 Volt USB_Connect_N USB_int_Req_FIQ USB_int_Req_IRQ 1.5 kOhm APB DP ATX DM USB interface The USB_Connect_N line can be used in the situation where internal initialisation of the USB device is longer than the time needed according to USB specification: "120ms after detection by the host of a USB device, the USB device should start responding to the transaction on the USB". A USB_Connect_N line can be used to switch the external pull-up resistor of 1.5kOhm under software control. 7.18.3 INTERRUPTS There are two interrupts to the system: · USB_int_req_FIQ · USB_int_req_IRQ 7.18.3.1 USB_int_req_FIQ This is the high priority interrupt to the system. The frame interrupt, Bulk OUT interrupt or Bulk IN interrupt can be routed to generate the FIQ. It is a must that this interrupt should have only one source at a time. 7.18.3.2 USB_int_req_IRQ This is the low priority interrupt to the system. The data transfer for all end points other than the FIQ source is initiated through this interrupt. This interrupt has got multiple sources, sources different from the source that created the FIQ at that point in time. 7.18.3.3 Interrupt handling When CPU gets FIQ interrupt it does not need to read the status register as there is only one source for it depending on the selection of the FIQ select register. In the service routine CPU has to clear the interrupt by writing `1' into bit position 2002 Jan 21 34 PHILIPS CONFIDENTIAL Philips Semiconductors Preliminary Specification version 1.3 Generic device for portable multimedia applications SAA7750-N1D SAA7750-N1D `0' of intr_clear_register but when it gets the IRQ interrupt it has to read the Interrupt status register and understand which interrupt bit is set. The service routine has to clear the corresponding interrupt. If it is an interrupt from USB core (Bit 1 to Bit 8 of Status register) the clear interrupt command to the USB core must also be executed. 7.18.3.4 Zero overhead operation To read the data without software overhead the CPU has to rely on the end_of_packet interrupt. The CPU can go on reading the receive data register and the read operation is to be terminated when the end of packet interrupt occurs. Hence the software does not have to track how many bytes it transferred. Still the number of bytes information is needed to remove the garbage bytes read. 7.19 CD Block Decoder The CD decoder block enables the SSA chip to playback from an audio CD or an MP3 CD. Major functionality's of this block include various data interfaces, a minimal block decoder, a buffer manager and an SDRAM controller. External CD engine is controlled through the serial command interface (IIC or UART) and disc data comes in through the serial data interface in either IIS or EIAJ format and the subcode interface in either V4 or EIAJ format. The minimal decoder detects sync and frame address and performs necessary error detection and descrambling. The buffer manager maintains read and write pointers and stores data in the data buffer (SDRAM) through the SDRAM controller. This report provides proposed features and functional descriptions of the CD decoder block. Register addresses are aligned to word (32-bit) boundary to facilitate accesses from the CPU. 7.19.1 7.19.1.1 FUNCTIONAL DESCRIPTION Features · Support of CD-DA mode, CD-ROM Yellow book and CD-ROM XA. · CRC Q-subcode error detection. · EDC C3 error detection to enable optional software correction through use of C2 error flag. · Scratch pad random access area in SDRAM for use by the CPU. · CD-DA seamless playback enables Constant-Angular-Velocity (CAV) drive compatibility · I2C master(1) and UART command interfaces with CD engine. Configurable UART baud rate. · Support of I2S/EIAJ with error flags. · V4/EIAJ subcode interface. · Hardware extraction of formatted Q-channel subcode. · Support of 16Mbit or 64Mbit SDRAM chips with 8- or 16-bit data bus. · Clock of the CD decoder block can be stopped and resumed to save power. · Support of CD-TEXT mode. Important note: the CD-block decoder has a PRIVITEpath to the SDRAM, having priority on the EBI over the ARM. This means that the CD block decoder can ALWAYS access the SDRAM. It also means that in all applications there MUST be an external SDRAM! (1) An I2C slave also exists in the SSA system for connection to the user interface. 2002 Jan 21 35 PHILIPS CONFIDENTIAL Philips Semiconductors Preliminary Specification version 1.3 Generic device for portable multimedia applications SAA7750-N1D SAA7750-N1D Block Diagram(1) FRONT PANEL I2C Slave (VLSI) I2C Master (VLSI) CDM-M5 APB 4 4 4 Minimal Decoder APB Interface V4 / EIAJ Minimal UART Register CD10 I2C / UART I2S / EIAJ MicroController AHB to APB Bridge Buffer Manager AHB master CD-Decoder IRQ AHB AHB slave SDRAM DQ CTRL 12 16 EBI ADDR SDRAM Controller 7 (ARM PL170 PL170) SSA Fig. 8 CD-BLOCKDECODER DIAGRAM 7.19.2 INPUT/OUTPUT PIN FUNCTION in table 7, the function of the pins of the CD blockdecoder are mentioned for both the IIC and the UART mode. (1) CDM-M5 is a Philips CD engine that includes a microcontroller and a CD10 chip. 2002 Jan 21 36 PHILIPS CONFIDENTIAL Philips Semiconductors Preliminary Specification version 1.3 Generic device for portable multimedia applications SAA7750-N1D SAA7750-N1D Table 7 Input/Output Pin Function(1) MODE 1 MODE 1 PIN NAME MODE 2 MODE 2 PIN NAME PIN NR R13 INPUT/ OUTPUT FUNCTION SDA Input/Output IIC data I/O line (open-drain output) UART P13 IIC RXD Input UART Serial Data Input C5 IIC SLK Input/Output IIC clock line (open-drain output) UART TXD Output UART Serial Data Output D5 IIC CRQ Input Communication request line UART ENGINE_RDY Input CD engine is ready to receive the next frame IIC CRST Output CD engine reset line UART HOST_RDY Output Host is ready to receive the next frame C9 IIS or EIAJ CLAB Input C7 IIS or EIAJ DAAB Input IIS/EIAJ serial data C8 IIS or EIAJ WSAB Input IIS/EIAJ word clock D9 IIS or EIAJ EFAB Input Serial Data Interface IIS/EIAJ input bit clock IIS/EIAJ error flags Subcode Interface D8 D6 D7 V4 V4 Input Versatile pin 4: single wire subcode EIAJ SUB Input EIAJ subcode data bits (3 wire) V4 CFLAG Input Absolute time sync Input EIAJ subcode frame sync (3 wire) Input/Output EIAJ subcode clock input (3 wire) Not used SFSY V4 Not used EIAJ C6 V4 EIAJ RCK 7.19.3 I2C Interface This is the communication interface between the CD decoder block and the CD engine. The CD decoder block represents the I2C master and communicates with the CD engine. The interface signals consist of the two wires used by I2C bus-SDA (serial data) and SCL (serial clock), a communication request line CRQ and a reset line (CRST). The CRQ line is used by the CD engine to signal a message is ready to be read out. The CRST line resets the CD engine. The high-low transition of CD engine insert line SENS_I is used for the detection of CD insertion. Important note: since 2 pins of the IIC master interface and the CD-block decoder UART are combined, the use of IIC master interface OR the UART are mutually exclusive! (1) Pin name and function for different modes are listed for shared pins. 2002 Jan 21 37 PHILIPS CONFIDENTIAL Philips Semiconductors Preliminary Specification version 1.3 Generic device for portable multimedia applications SAA7750-N1D SAA7750-N1D 7.19.4 Standard Serial Interface UART The UART serial port in the CD decoder block is a full duplex interface. For each frame, 11 bits are transmitted (through TXD) or received (through RXD): a start bit (logic 0), 8 data bits (LSB first), a parity bit and a stop bit (logic 1). Parity and baud rate can be configured through the UART_CTRL registers (see table 207). Both transmit and receive have a one-byte buffer that can be accessed through the UART_TX and the UART_RX registers, respectively. If enabled, an interrupt is generated at each byte transmitted or received. Baud rate is controlled through BaudRate field of UART_CONF1 register. It is effective for both transmit and receive. The receive logic is able to tolerate a 5% baud-rate shift, provided that the HCLK frequency is correctly set in UART_CONF2 register. All bits in UART_STATUS register can be cleared by writing a logic 1 to that bit, which also clears the interrupt associated with that bit. 7.19.5 Subcode Interface There are two subcode interfaces: 1. One that conforms to "EIAJ CP-2401 CP-2401" (using SBSY, SFSY, RCK and SUB) and can be configured as a 3 wire interface. The interface formats are illustrated in Fig.9. 2. The Philips V4 format on V4 pin as illustrated in Fig.10. The subcode sync word is formed by a pause of 200 ms minimum at nominal speed, where all subcode channels are muted. Each subcode byte starts with a 1 at the P-channel bit position followed by 7 bits (Q to W), with P-channel bits discarded. The gap between two consecutive bytes can vary from 11.3 ms to 90 ms. The byte alignment is found by searching for a minimum gap of 200 ms (at nominal speed) on the V4 input. The gap is counted against 12 rising edges of WSAB on the serial data interface (IIS or EIAJ). Once a start bit is detected, both rising and falling edges of WSAB, in conjunction with CLAB, are used to synchronize the sampling of subcode data. The 96-byte subcode data in a subcode frame is buffered in the subcode area of a 3KB buffer block. In addition, the 96-bit Q-channel subcode is duplicated in a separate 12-byte area within the same block. The last 16 bits of the Q-channel subcode are used internally to perform CRC. 2002 Jan 21 38 PHILIPS CONFIDENTIAL Philips Semiconductors Preliminary Specification version 1.3 Generic device for portable multimedia applications SAA7750-N1D SAA7750-N1D SF0 SF1 SF2 SF3 SF4 SF96 SF97 SF0 SF1 SFSY RCK P-W P-W P-W P-W SUB EIAJ 3-wire subcode interface SFSY RCK P Q R S T U V W SUB Fig. 9 EIAJ Subcode Interface Format 11.3 ms 200 ms min. (subcode sync) 1 W96 Q1 11.3 µs min. 90ms max. R1 S1 T1 U1 V1 1 W1 Q2 P-channel bit replaced by `1' Fig. 10 Philips V4 Subcode Format In audio mode, the first flag bit, F1, of the CFLAG input pulses for every block thus defines the block boundary. The flag is also called absolute time sync. The format of CFLAG is illustrated in Fig.11. Note that the audio sampling must always start from the left channel, which follows a falling edge of WSAB in IIS mode or a rising edge of WSAB in EIAJ mode. 11.3 ms 33.9 ms (nominal speed ) 1 F1 F2 F3 F4 F5 F6 F7 F8 1 Fig. 11 CFLAG Input Timing Diagram 2002 Jan 21 39 PHILIPS CONFIDENTIAL Philips Semiconductors Preliminary Specification version 1.3 Generic device for portable multimedia applications SAA7750-N1D SAA7750-N1D 7.19.6 Serial Data Interface The serial data interface can be switched between two modes: Philips I2S and the EIAJ format. In each case, the serial data is transferred through a 3-wire interface: WSAB (word select), CLAB (serial clock) and DAAB (serial data). The polarity of CLAB can be inverted. The fourth line, EFAB, indicates the C2 error flags that associates with each byte. The error flags are stored in the data buffer and can be used for C3 error correction. For audio mode, EFAB has no meaning as concealment is already performed within the engine. The timing of I2S and EIAJ is illustrated in Fig.12 on page 40 (1). CLAB DAAB WSAB EFAB (error flags) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 right left left LSB valid right MSB valid right LSB valid Philips I2S timing CLAB DAAB 1 0 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 left WSAB right EFAB EIAJ timing Fig. 12 I2S and EIAJ Interface Timing 7.19.7 Minimal Block Decoder This block accepts data from the serial data interface (I2S or EIAJ) and performs necessary word alignment, synchronization, data descrambling and error detection for the type of data being read. Four CD formats are supported: · The CD-DA format for audio playback. The MSF address is embedded in the Q-channel subcode. CRC is performed on the Q-channel data and MSF information is de interleaved. The audio data has no block structure, however, the F1 flag is used to divide the data stream into 2352-byte blocks to facilitate data buffering. Error flags are stored in the data buffer. Data descrambling must be disabled. · The CD-ROM Yellow Book Mode 1 format. The data frame structure is illustrated in Fig.48. The C3 check bytes, including 172 P-parity bytes and 104 Q-parity bytes, along with the C2 error flags coming through EFAB line, are (1) The IIS timing shown in Fig.12 is Philips 24-bit format, in which 24 CLAB cycles are contained within each half cycle of WSAB. There are other formats that are being used, such as 16-bit and 32-bit formats. However, for all formats, the 16 data bits are always aligned to the leading edge. 2002 Jan 21 40 PHILIPS CONFIDENTIAL Philips Semiconductors Preliminary Specification version 1.3 Generic device for portable multimedia applications SAA7750-N1D SAA7750-N1D saved in the buffer and can be used for software C3 correction if desired. Data descrambling is performed before EDC. The four EDC bytes are generated from the sync pattern, the header, and the user data. EDC calculation is performed by the minimal decoder to validate these data fields. · The CD-ROM XA Mode 2 Form 1. The data frame structure is illustrated in Fig.49. The form bit is included in both copies of sub-header. For each block, two form bits are extracted from each copy of sub-header and then compared. A mismatch is marked in the status field of the buffer block and also causes EDC failure since sub-header is used for EDC calculation. Data descrambling is performed before EDC. Note that EDC for this format does not cover the MSF address. · The CD-ROM XA Mode 2 Form 2. As shown in Fig.50, compared with Form 1 data, Form 2 blocks do not contain C3 check bytes in exchange for more user data. The 4-byte EDC is not used for discs of this format. Descrambling and form bits extraction are performed in the same way as in Form 1. Sub-header mismatch is marked in the status field of the corresponding buffer block. Format of an MP3 disc can be either CD-ROM Yellow Book Mode 1 or CD-ROM XA Mode 2 Form 1. For CD-ROM modes, the EDC polynomial for a data frame is: G(x) = X32+X31+X16+X15+X4+X3+X+1. An EDC failure is indicated in the status field of the buffer block. The 16-bit CRC of Q-subcode specifies a Cyclic Redundancy Check character computed over the CONTROL, ADR and DATA-Q fields. The field contains the inverted parity bits. The most significant bit of the CRC is in bit 81. The CRC generation polynomial is: P(x) = X16+X12+X5+1. A flywheel circuit is needed to interpolate a data frame sync if the sync pattern is not seen at the expected time. Some protection against spurious sync pattern is also needed by only allowing the sync pattern detector to operate within a small window which encompasses the expected time for the sync pattern. Address interpolation must be implemented. Address interpolation is needed for Q-subcode frames as the MSF address information is only guaranteed to appear on 9 out of 10 consecutive frames while the other slots may contain UPC or MCN information. If EDC is enabled in CD-ROM Yellow Book Mode 1 and CD-ROM XA Mode 2 Form 1, the block decoder will stop at any data block that fails EDC if EDCFailStop bit is set; BUF_WR_PTR and BlockCnt values will remain as they were when the last EDC-passed frame was buffered. 7.19.8 CD TEXT MODE CD-TEXT data can be stored in the Lead-In Area and the Program Area and is read out from the disc through R-W subcode channels. The structure of CD-TEXT data is illustrated in Fig.13 2002 Jan 21 41 PHILIPS CONFIDENTIAL Philips Semiconductors Preliminary Specification version 1.3 Generic device for portable multimedia applications SAA7750-N1D SAA7750-N1D Text Group Text Group Block 0 Block 1 Text Group Text Group Block 2 Text Group Block 3 max. 256 Packs Pack (0) Pack (1) Pack (n) Header Field = Text Data field = 4 bytes 12 bytes n