SAA2502 SAA2500 SAA2501 SAA2502H QFP44 X22OUT MCLK24 X22IN MGE469 MGE468 FSC384 - Datasheet Archive

 

DATA SHEET SAA2502 ISO/MPEG Audio Source Decoder Preliminary specification File under Integrated Circuits, IC01 1997 Apr 18

 

INTEGRATED CIRCUITS DATA SHEET SAA2502 SAA2502 ISO/MPEG Audio Source Decoder Preliminary specification File under Integrated Circuits, IC01 1997 Apr 18 Philips Semiconductors Preliminary specification ISO/MPEG Audio Source Decoder SAA2502 SAA2502 9 1 2 3 4 5 6 7 7.1 7.2 7.2.1 7.2.2 7.2.3 7.2.4 7.3 7.3.1 7.3.2 7.3.3 7.4 7.4.1 7.4.2 7.4.3 7.4.4 7.4.5 7.4.6 7.4.7 7.4.8 7.4.9 7.5 7.5.1 7.5.2 7.5.3 7.6 7.6.1 7.6.2 7.6.3 7.6.4 7.6.5 7.6.6 8 APPENDIX 8.1 8.1.1 8.1.2 8.1.3 8.1.4 L3 interface specification Introduction Example of a data transfer Timing requirements Timing 1997 Apr 18 2 DEFINITIONS 16 Basic functionality Clock generator module External sample clock Free running internal sample clock Locked internal sample clock Limited sampling frequency support for internal sampling clocks Input interface module Master input mode Slave input mode Buffer controlled input mode Decoder core Frame synchronization to input data streams Master input mode bit rate generation Sample clock generation Decoder precision Scale factor CRC protection Handling of errors in the coded input data Dynamic range compression Baseband audio processing Decoder latency time Output interface module I2S output SPIDF output Bit serial analog output Control interface module Resetting Interrupts Microcontroller interface Initialization Transfer protocols Local registers Introduction Reflow soldering Wave soldering Repairing soldered joints 15 FUNCTIONAL DESCRIPTION SOLDERING 14.1 14.2 14.3 14.4 PINNING PACKAGE OUTLINE 14 BLOCK DIAGRAM APPLICATION INFORMATION 13 ORDERING INFORMATION Host interface: CDATA, CCLK and CMODE 12 GENERAL DESCRIPTION AC CHARACTERISTICS 11.1 APPLICATIONS DC CHARACTERISTICS 11 FEATURES LIMITING VALUES 10 CONTENTS LIFE SUPPORT APPLICATIONS Philips Semiconductors Preliminary specification ISO/MPEG Audio Source Decoder 1 SAA2502 SAA2502 2 FEATURES APPLICATIONS · Low sampling frequency decoding possibilities (24 kHz, 22.05 kHz and 16 kHz) of MPEG2 are supported · Astra Digital Radio (ADR) · A variety of output formats are supported: I2S, SPDIF and 256 or more times oversampled bit serial analog stereo · Digital Versatile Disc (DVD) · Digital Audio Broadcast (DAB) · Digital Video Broadcast (DVB) · General purpose MPEG2 audio decoding. · Automatic internal dynamic range compression algorithm using programmable compression parameters 3 · Non byte-aligned coded input data is handled GENERAL DESCRIPTION The SAA2502 SAA2502 is a second generation ISO/MPEG audio source decoder. The device specification has been enhanced with respect to the SAA2500 SAA2500 and SAA2501 SAA2501 ICs and therefore it offers in principle all features of its predecessors. · Built-in provisions to generate high quality sampling clocks for all six supported sampling frequencies; these sampling clocks may locked to an external PLL to support an extensive list of input data reference clock frequencies It supports layer I and II of MPEG1 and the MPEG2 requirements for a stereo decoder. · Bit-rate and sampling-rate settings may be overruled by the microcontroller while the SAA2502 SAA2502 is trying to establish frame synchronization · Input interface mode which requests data based on input buffer content, enables the handling of variable bit-rate input streams and input data offered in (fixed length) bursts · An interrupt output pin which can generate interrupt requests at the occurrence of various events; consequently polling by the microcontroller is not needed in most situations · L3 and the I2C-bus microcontroller interface protocols are supported · The control interface is always fully operational (also while STOP is asserted) · CRC protection of scale factors is provided for all supported sample frequencies. 4 ORDERING INFORMATION PACKAGE TYPE NUMBER NAME SAA2502H SAA2502H 1997 Apr 18 QFP44 QFP44 DESCRIPTION plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 × 10 × 1.75 mm 3 VERSION SOT307-2 Philips Semiconductors Preliminary specification ISO/MPEG Audio Source Decoder 5 SAA2502 SAA2502 BLOCK DIAGRAM MCLKIN handbook, full pagewidth MCLKOUT 31 32 29 VDD1 VDD3 X22OUT X22OUT MCLK24 MCLK24 X22IN X22IN 27 26 CDATA CMODE VDD2 CCLK PHDIF 23 REFCLK 18 30 44 22 8 7 STOP INT 9 RESET 10 12 11 33 41 FSCLK FSCLKIN TC0 TC1 1 25 CLOCK GENERATOR PHASE COMPARATOR DIVIDER 24 DECODING CONTROL 21 40 5 43 3 SAA2502 SAA2502 2 4 CD CDEF CDSY CDCL CDVAL CDRQ 15 SPDIF ENCODER 17 DEQUANTIZATION AND SCALING 19 14 INPUT INTERFACE DEMULTIPLEXER 20 SYNTHESIS SUB-BAND FILTER 13 16 28 42 GND1 GND2 GND3 6 39 DIGITAL-TOANALOG CONVERTER 37 38 34 35 36 MGE469 MGE469 Fig.1 Block diagram. 1997 Apr 18 4 REFP REFN TDI TDO TCK TMS TRST SD SCK WS SPDIF LFTPOS LFTNEG RGTPOS RGTNEG Philips Semiconductors Preliminary specification ISO/MPEG Audio Source Decoder 6 SAA2502 SAA2502 PINNING SYMBOL PIN DESCRIPTION FSCLK 1 sample rate clock output; buffered signal SCK 2 baseband audio data I2S clock output SD 3 baseband audio I2S data output WS 4 baseband audio data I2S word select output TRST 5 boundary scan test reset input SPDIF 6 SPDIF baseband audio output CCLK 7 L3 clock/I2C-bus bit clock input CDATA 8 L3 data/I2C-bus serial data input/output; note 1 CMODE 9 L3 mode (address/data select input) INT 10 interrupt request output; active LOW; note 1 RESET 11 master reset input STOP 12 soft reset/stop decoding input CDRQ 13 coded data request output CDCL 14 coded data bit clock input/output; note 2 CD 15 MPEG coded data input GND1 16 ground 1 CDEF 17 coded data error flag input VDD1 18 supply voltage 1 CDSY 19 coded data byte or frame sync input CDVAL 20 coded data valid flag input TMS 21 boundary scan test mode select input REFCLK 22 PLL reference clock input PHDIF 23 PLL phase comparator output; note 2 TCK 24 boundary scan test clock input FSCLKIN 25 sample rate clock input X22IN X22IN 26 22.579 MHz clock oscillator input or signal input X22OUT X22OUT 27 22.579 MHz clock oscillator output GND2 28 ground 2 MCLK24 MCLK24 29 master clock frequency indication input VDD2 30 supply voltage 2 MCLKOUT 31 master clock oscillator output MCLKIN 32 master clock oscillator input or signal input TDI 33 boundary scan test data input RGTPOS 34 analog right channel positive output RGTNEG 35 analog right channel negative output REFN 36 low reference voltage input for analog outputs REFP 37 high reference voltage input for analog outputs LFTNEG 38 analog left channel negative output LFTPOS 39 analog left channel positive output TC0 40 factory test scan chain control 0 input 1997 Apr 18 5 Philips Semiconductors Preliminary specification ISO/MPEG Audio Source Decoder SYMBOL SAA2502 SAA2502 PIN DESCRIPTION TDO 41 boundary scan test data output GND3 42 ground 3 TC1 43 factory test scan chain control 1 input VDD3 44 supply voltage 3 Notes 1. Output type is: open-drain. 34 RGTPOS 35 RGTNEG 36 REFN 37 REFP 38 LFTNEG 39 LFTPOS 40 TC0 41 TDO 42 GND3 43 TC1 44 VDD3 2. Output type is: 3-state. FSCLK 1 33 TDI SCK 2 32 MCLKIN SD 3 31 MCLKOUT WS 4 30 VDD2 TRST 5 29 MCLK24 MCLK24 SPDIF 6 28 GND2 CCLK 7 27 X22OUT X22OUT CDATA 8 26 X22IN X22IN CMODE 9 25 FSCLKIN SAA2502 SAA2502 24 TCK INT 10 23 PHDIF Fig.2 Pin configuration. 1997 Apr 18 6 TMS 21 REFCLK 22 CDVAL 20 CDSY 19 VDD1 18 CDEF 17 GND1 16 CD 15 CDCL 14 13 CDRQ STOP 12 RESET 11 MGE468 MGE468 Philips Semiconductors Preliminary specification ISO/MPEG Audio Source Decoder 7 7.1 SAA2502 SAA2502 7.2 FUNCTIONAL DESCRIPTION Clock generator module The SAA2502 SAA2502 clock interfacing is designed for application versatility. It consists of 9 signals (see Table 1). Basic functionality From a functional point of view, several blocks can be distinguished in the SAA2502 SAA2502. A clock generator section derives the internally and externally required clock signals from its clock inputs. The input interface section receives or requests coded input data in one of the supported input interface modes. The demultiplexer processor handles frame synchronization, parsing, demultiplexing and error concealment of the input data stream The de-quantization and scaling processor performs the transformation and scaling operations on the (demultiplexed) coded sample representations in the input bitstream to yield sub-band domain samples. The clock generator provides the following clock signals: · Internal sample clocks · External buffered sample clock FSCLK · Processor master clock · Coded input data bit clock input bit rate · Coded input data request clock f = -32 The module can be configured to operate in 3 different modes of operation: · External sample clock mode The sub-band samples are transferred to the synthesis sub-band filter bank processor which reconstructs the baseband audio samples. The output interface block transforms the audio samples to the output formats required by the different output ports. · Free running internal sample clock mode · Locked internal sample clock mode. Clock generator operation mode must be stationary while the device is in normal operation. Changing mode should always be followed by a (soft) reset. I2C-bus/L3 The decoding control block houses the microcontroller interface, and handles the response to external control signals. This section enables the application to configure the SAA2502 SAA2502, to read its decoding status, to read ancillary data and so on. Several pins are reserved for boundary scan test (5 pins) and factory test scan chain control (2 pins). Table 1 Clock interfacing signals SIGNAL DIRECTION FUNCTION MCLKIN input MCLKOUT output master clock oscillator output MCLK24 MCLK24 input master clock frequency indication X22IN X22IN input 22.5792 MHz clock oscillator input or signal input X22OUT X22OUT output 22.5792 MHz clock oscillator output FSCLKIN input external sample rate clock signal input FSCLK output sample rate clock signal output REFCLK input coded input data rate reference clock PHDIF output phase difference indication output between reference clock and sample clock 1997 Apr 18 master clock oscillator input or signal input 7 Philips Semiconductors Preliminary specification ISO/MPEG Audio Source Decoder 7.2.1 SAA2502 SAA2502 EXTERNAL SAMPLE CLOCK Table 3 In applications where a 256 × fs sample clock is available, the use of external crystals may be avoided by putting the SAA2502 SAA2502 clock generator module in `external sample clock mode'. Such mode setting may be realized by setting control flag FSCINP of the control interface. In this event the sample clock has to be provided to the FSCLKIN clock input. If sample rate switching should be supported, required clock frequency changes are the responsibility of the application. After such a clock frequency change, enforcement of a soft reset is advised. SAMPLE FREQUENCY 6.144 24.576 -4 5.6448 22.5792 -4 4.096 24.576 -6 1. Asymmetrical FSCLK. The main advantage of this mode is that the SAA2502 SAA2502 determines automatically which sampling rate is active from the sampling rate setting of the input data bit stream, and then selects either MCLKIN or X22IN X22IN divided by the correct number as the sample clock source. Therefore this mode is particularly suited in applications supporting dynamically varying sampling rates. The required clocks may either be applied to MCLKIN (respectively to X22IN X22IN) or be generated by connecting a crystal between MCLKIN and MCLKOUT (respectively between X22IN X22IN and X22OUT X22OUT). MAXIMUM The recommended crystal oscillator configuration is shown in Fig.3. The specified component values only apply to crystals with a low equivalent series resistance of 200 dB, practically up to 120 dB for the 22-bit output mode).This feature is very attractive from the high quality audio standpoint of view, but such high dynamic range is undesirable when there is a relatively high level of background noise (e.g. for car radio). For those applications the SAA2502 SAA2502 offers the possibility of built in dynamic range compression: 0.0117 dB · Minimum release rate = -384 samples (1.46 dB/s at 48 kHz; 0.488 dB/s at 16 kHz) 0.375 dB · Maximum release rate = -384 samples (46.87 dB/s at 48 kHz; 15.625 dB/s at 16 kHz). · Internal dynamic range compression is offered. Thus any standard MPEG encoded bit stream may be compressed i.e. no added compression information is required. Decreasing amplification factors, must be applied almost immediately to avoid overflow when the audio power increases rapidly; thus attack rate is non-programmable and fast. · The dynamic range compression algorithm is fully parameterised. All major characteristics are programmable through the control interface: ­ Level of compression ­ Maximum compression handbook, halfpage amplification (dB) ­ Compression offset compression slope ­ Compression release rate (compression attack rate has to be fixed). maximum amplification The dynamic range compression algorithm is based on a (in time varying) amplification factor, which is equally applied to all audio output samples. The value of the amplification factor is calculated on basis of the current audio output power level for each (sub)frame of 384 output samples. The applied power to amplification curve is shown in Fig.11. All characteristics of the curve are programmable: 0 dB power (dB) offset · Compression slope minimum = 0, maximum = 0.996 MGE478 MGE478 Fig.11 Dynamic range compression characteristic. · Maximum amplification minimum = 0 dB, maximum = 23.81 dB · Offset minimum = 0 dB, maximum = 47.81 dB. audio signal power attack rate amplification In the context of dynamic range compression definition, the 0 dB power reference level is defined as a sine wave shaped output signal with maximum amplitude in just one (right or left) channel. release rate time The calculation will result in an new amplification factor every 384 samples (i.e. from 8 ms at 48 kHz to 24 ms at 16 kHz sample rate). Subsequent amplification factors may vary considerably. 1997 Apr 18 MGE479 MGE479 handbook, halfpage Offset values close to 0 dB may result in clipped output signals. This is especially true for signals with a high amplitude-to-power ratio (an extreme example of such a signal is a maximum amplitude unit impulse). The occurrence of this effect can be avoided by selecting an offset value close to or greater than 15 dB. Fig.12 Amplification change rates. 20 Philips Semiconductors Preliminary specification ISO/MPEG Audio Source Decoder 7.4.8 SAA2502 SAA2502 BASEBAND AUDIO PROCESSING Baseband audio de-emphasis as indicated in the MPEG input data stream is performed digitally inside the SAA2502 SAA2502. The included `Audio Processing Unit' (APU) see Fig.19, may be used to apply programmable inter-channel crosstalk or independent channel volume control. left decoded handbook, halfpage audio samples LR The APU attenuation coefficients LL, LR, RL and RR may be changed dynamically by the microcontroller, writing their 8-bit indices to the SAA2502 SAA2502 through its control interface. The coefficient changes become effective within one sample period after writing. To avoid audible clicks at coefficient changes, the transition from the current attenuation to the next is smoothed. The relationship between the APU coefficient index and the actual coefficient (i.e. the gain) is shown in Fig.14 and in Table 9 RL right decoded audio samples Fig.13 Audio Processing Unit (APU). The APU has no built-in overflow protection, so the application must assure that the output signals of the APU cannot exceed the 0 dB level. For an update of the APU coefficients, it may be required to increase some of the coefficients and decrease some others. The APU coefficients are always written sequentially in a fixed sequence LL, LR, RL and RR. Therefore, to prevent (temporary) internal APU data overflow, the following sequence of steps may be necessary: handbook, halfpage 0 0 00000000 to 00111111 (2) -83.25 MGE480 MGE480 (1) Step -3/16 dB per coefficient increment. (2) Step -3/8 dB per coefficient increment. 2 01000000 to 11111110 64 to 254 2 11111111 1997 Apr 18 255 Fig.14 Relation between APU coefficient index and gain. APU COEFFICIENT 0 to 63 254 255 gain (dB) APU coefficient index and actual coefficient. DECIMAL APU coefficient index (1) 2. Write LL, LR, RL and RR again, but now change increasing coefficients, keeping the other ones unchanged. BINARY 64 -12 1. Write LL, LR, RL and RR, but change only decreasing coefficients. Overwrite increasing coefficients with their old value (therefore do not change these yet). APU COEFFICIENT INDEX C right output audio samples RR MGB493 MGB493 For coefficient index 0 to 64 the step size is -3/16 dB and for coefficient index 64 to 255 the step size is -3/8 dB. Table 9 left output audio samples LL C ­ -32 ( C ­ 32 ) ­ -16 0 21 Philips Semiconductors Preliminary specification ISO/MPEG Audio Source Decoder 7.4.9 SAA2502 SAA2502 7.4.9.1 DECODER LATENCY TIME Master and slave input interface modes Latency time is defined as elapsed time between the moment that the first byte of an audio frame is delivered to the SAA2502 SAA2502 and the moment that the output response resulting from the first (sub-band) sample of the same frame reaches its maximum. Input buffer latency time tbuf = (minimum of tbuf1 and tbuf2) + cr × 3.52 ms: · tbuf1 is sample frequency dependent (see Table 10) Latency time results from the addition of two internal latency contributions: tlatency = tproc + tbuf. · cr is the ratio between maximum and actual value of MCLKIN frequency. · tbuf2 is input bit rate dependent (see Table 11 and Table 12) · The processing latency time (tproc) is sample frequency dependent (see Table 10). For slave input interface mode NOT the average input bit rate should be used for table look-up, but CDCL frequency (input bit rate during the burst). For free format bit rates the table should be interpolated (tbuf2 is proportional to 1/bit rate). · The input buffer latency time (tbuf) is input interface mode dependent. Precision of latency time calculation is sampling rate and bit rate dependent. Maximum deviation is roughly plus or minus 4 sample periods. Table 10 Processing latency time SAMPLE FREQUENCY (kHz) tproc (ms) tbuf1 LAYER I (ms) tbuf1 LAYER II (ms) 48 6.67 8.00 24.00 44.1 7.26 8.71 26.12 32 10.00 12.00 36.00 24 13.33 16.00 48.00 22.05 14.51 17.41 52.24 16 20.00 24.00 72.00 Table 11 Buffer latency time; high bit rate Table 12 Buffer latency time; low bit rate BIT RATE (kbits/s) tbuf2 (ms) BIT RATE (kbits/s) tbuf2 (ms) 448 5.52 416 5.94 384 6.44 352 7.02 320 7.73 288 8.58 256 9.66 224 11.04 192 12.88 176 14.05 160 15.45 144 17.17 128 19.31 112 22.07 96 25.75 80 30.90 64 38.63 56 44.14 48 51.50 40 61.80 32 77.25 24 103.00 16 154.50 8 309.00 1997 Apr 18 22 Philips Semiconductors Preliminary specification ISO/MPEG Audio Source Decoder 7.4.9.2 SAA2502 SAA2502 Consequently the application may delay delivery of requested data until it becomes available without any effect on correct SAA2502 SAA2502 operation. This option constitutes delayed delivery possibility. Buffer controlled input mode Input buffer latency time behaviour is relatively complex in this mode. At start-up (i.e. during the search-for-frame sync) latency time is very small (tbuf < 2 ms) because the input buffer remains empty. 7.5 After a frame sync is detected, normal decoding starts and the buffer fills up to its desired fill level. That level will result in a buffer latency time tbuf2 (see Tables 11 and 12, tbuf1 plays no role) for constant bit rate operation. · I2S Output interface module The output interface module produces stereo baseband output samples in three different formats at the same time: · SPDIF · 256 times oversampled bit serial analog. It is more complex for variable bit rates, at high bit rates the buffer will hold only a fraction of a frame, while at low bit rates it may hold many frames (each possibly of a different bit rate). Also input buffer content may deviate from the desired level because data consumption rate at the output of the buffer may be high during short periods while replenishing is limited by CDCL frequency. Any of the three outputs may be enabled or disabled in order to save dissipation and minimize EMC generation in applications that do not need all of them. Decoded mono streams and the (user) selected channel of dual channel streams are presented at both (left and right) output channels. As a result buffer latency time in buffer controlled input mode may be predicted more or less accurately only at (re)start time. If indicated in the coded input data, de-emphasis filtering is performed digitally on the output data, thus avoiding the need of external analog de-emphasis filter circuitry. Another consequence of buffer behaviour at very low bit rates in this mode is that buffer latency time values may become large. Therefore it might be possible that the SAA2502 SAA2502 will request data, which is not (yet) available. In those situations the SAA2502 SAA2502 is requesting more data than required; storage of more than one complete frame in the input buffer is never necessary. 7.5.1 I2S OUTPUT This output interface section generates decoded baseband audio data in I2S format (see Fig.15). The I2S output interface section consists of 3 signals (see Table 13). left sample handbook, full pagewidth MSB right sample MSB LSB LSB SD 1 16/18/20/22 32 1 16/18/20/22 32 SCK WS MGB502 MGB502 valid data Fig.15 I2S output serial data transfer format. 1997 Apr 18 23 Philips Semiconductors Preliminary specification ISO/MPEG Audio Source Decoder SAA2502 SAA2502 7.5.2.2 Table 13 Signals of output interfacing SIGNAL DIRECTION FUNCTION SCK output data clock SD output baseband audio data WS output word select The frame synchronization patterns are based on bi-phase violations. They are sent as shown in Table 14 The sequences are sent in place of 4 bi-phase coded bits 0 to 3. They are not bi-phase coded, but are sent as they are. The frequency of clock SCK is 64 times the sample frequency. Table 14 Frame synchronization patterns The signal SD is the serial baseband audio data, sample by sample (left/right interleaved; the left sample and the right immediately following it form one stereo pair). 32 bits are transferred per sample per channel. The samples are transmitted in two's complement, MSB first. The output samples are rounded to either 16, 18, 20 or 22 bit precision, selectable by the control interface flags RND1 and RND0. The remainder of the 32 transferred bits per sample per channel are zero. BINARY 7.5.2.1 DESCRIPTION B left sub-frame follows. SPDIF super-frame starts. Bit 0 of left C channel will be sent in this subframe 11100100 W right subframe follows 11100010 M left subframe follows 7.5.2.3 Validity flag (bit 28, SPDIF subframe, V bit) The V bit is intended to indicate an invalid data sample. Equipment connected to the interface is expected to perform interpolations across small numbers of invalid (V = logic 1) samples. Owing to the manner in which data is decoded in the SAA2502 SAA2502, and the sub-band processing of the signal, an input data error affects output audio signals in a complex way. SPIDF OUTPUT SPIDF format The SPDIF data format is frame based. One SPDIF frame represents one audio sampling period. Complete frames must be transmitted at the audio sample rate. Every frame comprises two sub-frames, each of 32 bits. The data is transmitted in bi-phase mark modulated format to ensure a zero DC component. There is not a simple relationship between input errors and damaged audio samples. Therefore the validity flag value is made programmable (through the control interface unit) Control software can use this bit in any way required. Four bits of data at the beginning of each sub-frame are assigned to frame and sub-frame synchronization, which is achieved using a set of 3 output sequences which violate the bi-phase mark rules. The audio samples occupy 24 bits (bits 4 to 27), transmitted LSB first. Depending on the selected accuracy the 2, 4, 6 or 8 LSBs will be logic 0. 7.5.2.4 User channel data (bit 29, SPDIF subframe, U bit) There is a single user data channel. Two bits of data in this channel are transmitted in each frame. For this minimum implementation only the possibility to send single byte user messages to the user channel is offered. Each byte sent will be preceded by a single logic 1 valued start bit. The 8 bits of the user message are then sent LSB first. Bits 28 to 31 are occupied by the validity flag for the audio sample, a channel status bit (each super-frame of 192 frames contains two groups of 192 channel status bits, one for each channel), a user data bit, and a parity bit (even parity for bits 4 to 31). These bits are described respectively as V, U, C and P in the SPDIF specification. 7.5.2.5 Channel status data (bit 30, SPDIF sub-frame, C bit) A group of C channel status bits consists of 192 bits. Two groups of channel status bits are transmitted every super-frame (one group for each channel) at a rate of one bit per sub-frame. In this application, both channel status words will be identical. The synchronization for the channel status frame is achieved by a pair of preamble violation sequences. The synchronization for the user channel data is embedded within the data. 1997 Apr 18 PATTERN 11101000 The word select signal WS indicates the channel of the output samples (LOW if left, HIGH if right). 7.5.2 Frame synchronization patterns (Bits 0 to 3, SPDIF subframe) 24 Philips Semiconductors Preliminary specification ISO/MPEG Audio Source Decoder SAA2502 SAA2502 Table 15 Channel status data DESCRIPTION Control field; note 1 BITS FIELD INDICATION 0 0 indicates consumer use 1 0 logic 1 reserved for digital data and further standardization 2 C logic 0 = copy prohibited; logic 1 = copy permitted 3 and 4 00 no pre-emphasis (SAA2502 SAA2502 has automatic de-emphasis) 5 0 2 channel audio data 6 and 7 00 mode 0 indication Category code 8 to 15 00000000 2 channel Source number 16 to 19 0000 don't care Channel number 20 to 23 0000 don't care Sample frequency; note 2 24 to 27 field filled in accordance with clause 4.2.2.2 of the SPDIF standard: 0100 = 48 kHz 0000 = 44.1 kHz 1100 = 32 kHz Clock accuracy; note 3 28 and 29 field filled in accordance with clause 4.2.2.2 of the SPDIF standard: 00= level II (normal accuracy of 0.1%) Notes 1. This field is filled according to clause 4.2.2.2 of the SPDIF standard `Channel status data format for digital audio equipment for consumer use' (mode 0). 2. The low sample frequencies of MPEG2 are not defined yet. In order to be able to follow future standardization, the code sent for the three remaining sampling frequencies (24, 22.05 and 16 kHz) is programmable through the controller interface. 3. The remaining 162 bits of each channel status word will all be logic 0. Individual bits of the status channel will be sent bit 0 first. 7.5.2.6 Parity (bit 31, SPDIF sub-frame, P bit) Table 16 SPDIF interface control Even parity is generated on the 28 sub-frame data bits (4 to 31) in bit 31. 7.5.2.7 BIT/BYTE DEFAULT RESULT V bit default = logic 1 digital copy permitted U byte The SPDIF interface will be controlled by the microcontroller via the control interface. The V bit is copied into each SPDIF subframe (once for each data sample). The C bit is inserted twice per SPDIF super-frame into the channel status data (bit 2 in each C channel). The user byte is inserted into the user channel (preceded by a start bit) immediately after reception through the control interface, otherwise the user channel is filled with logic 0s. valid audio data C bit SPDIF control default = logic 0 uuuuuuuu 8 bits user byte 7.5.2.8 Channel status The sampling frequency bits (bits 24 to 27) are derived from the sampling frequency index bits of the input data stream 7.5.2.9 User data Only single 8 bit messages are sent. Individual messages should be time separated far enough to insert at least 9 logic 0s in between (for easy synchronization at the receiver end at random entry points in the stream). 1997 Apr 18 25 Philips Semiconductors Preliminary specification ISO/MPEG Audio Source Decoder 7.5.3 SAA2502 SAA2502 The two analog outputs deliver a `pulse density modulated' signal, switching between REFN and REFP. The format is programmable (through the control interface): BIT SERIAL ANALOG OUTPUT In order to serve applications which require low to medium performance stereo audio output, two bit serial analog outputs are provided (one for each channel). The on-chip DACs each consist of three functional blocks in series: · Non return-to-zero format (subsequent logic 1 pulses are merged) · Return-to-zero format (subsequent logic 1 pulses are separated by logic 0 levels). · 4 × fs up-sampling filter · AC and DC dithering block · N × fs noise shaper; see Table 17. The quality of the analog output signal depends on several external factors: Table 17 Value of N for N × fs noise shaper · Stability and decoupling of the analog supply SAMPLE RATE MODE · Absence of jitter on the sample clock VALUES · Which external low-pass filter circuit is used FSC384 FSC384 = 0 N = 256 · The layout of the low-pass filter. FSC384 FSC384 = 1 External sample clock mode N = 384 The recommended external low-pass filter is shown in Fig.17. With this circuit the DACs performance is