SA-1100 AP-702 SA1100 28F128J3A 28F640J3A 28F320J3A 2242H 2642H AP-617 - Datasheet Archive

 

Memory to StrongARM* SA-1100 CPU Design Guide Application Note 702 May 2000 Order Number: 292250-002 Information in this document

 

3 Volt Intel® StrataFlashTM Memory to StrongARM* SA-1100 SA-1100 CPU Design Guide Application Note 702 May 2000 Order Number: 292250-002 Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800548-4725 or by visiting Intel's website at http://www.intel.com. Copyright © Intel Corporation, 1999­2000 *Other brands and names are the property of their respective owners. AP-702 AP-702 Contents 1.0 Introduction . 1 2.0 Hardware Interface . 1 3.0 Interfacing 3 Volt Intel® StrataFlashTM Memory to the StrongARM* SA-1100 SA-1100 at 190 MHz. 2 3.1 3.2 3.3 3.4 4.0 Interface Considerations . 2 Processor Interface Signals . 3 Control Signal Generation . 3 SA1100 SA1100 with DRAM Interface on the System. 7 3.4.1 DRAM Refresh Corrupting ROM Burst of 4/8 Timing . 7 Summary . 8 iii AP-702 AP-702 Revision History Date of Revision 07/20/99 -001 Original version 05/10/00 iv Version -002 Added the SA1100 SA1100 errata and provided solution. Reformatted document Description AP-702 AP-702 1.0 Introduction 3 Volt Intel® StrataFlashTM memory provides reliable two-bit-per-cell technology at a low cost. This product offers higher performance than previous 5 Volt Intel® StrataFlashTM memories with faster read times and a page-mode interface for increased speed. Other benefits include more density in less space, high-speed interface, support for code and data storage in the same device, and Common Flash Interface (CFI) for easy migration to future devices. This application note will cover the 3 Volt Intel StrataFlash memory's interface to the StrongARM* SA-1100 SA-1100 processor. This application note was written with preliminary information about 3 Volt Intel StrataFlash memory. Any changes in those specifications may not be reflected in this document. These interfaces have not been implemented in hardware. Refer to the appropriate documents or sales personnel for the most current information. 2.0 Hardware Interface This section describes signals and considerations that occur in most of the interfaces. The interfaces in this document use the following signals generated by the 3 Volt Intel StrataFlash memory: VCC: Device power supply. 2.7 V ­ 3.6 V VCCQ: Output buffer power supply. This voltage controls the device's output voltages. 5 V ± 10% or 2.7 V ­ 3.6 V OE#: Output enable is an active low signal that activates the device's outputs during a read operation. Any data remaining on the bus after this signal is driven high will be lost. This signal must remain inactive during a write operation. WE#: Write enable is an active low signal that controls writes to the Command User Interface, write buffer, and array blocks. The rising edge of this signal latches addresses and data. WE# must remain inactive during read access, and must toggle between consecutive writes. CE0:2: The three chip enable signals activate the device's control logic, input buffers, decoders, and sense amplifiers. Multiple chip enable signals allow switching between several 3 Volt Intel StrataFlash memory components without additional decoding. For all designs in this document, CE1 and CE2 are tied to ground. CE0 is used as the only signal to enable the device. Chip enable signals must remain in an active state during any read or write access. When the CE pins disable the 3 Volt Intel StrataFlash memory, the device is deselected and power consumption is reduced to standby levels. For more information on typical CE configurations see the 3 Volt Intel® StrataFlashTM Memory: 28F128J3A 28F128J3A, 28F640J3A 28F640J3A, 28F320J3A 28F320J3A datasheet. RP#: Reset/Power Down is an active low signal. It resets internal automation and puts the device in power-down mode. Exit from reset sets the device in read array mode with page-mode disabled. After exiting from reset or powering on the 3 Volt Intel StrataFlash memory, bit 16 of the read control register must be set to enable page-mode timings. BYTE#: Byte enable is an active low signal. Byte enable low places the 3 Volt Intel StrataFlash memory in x8 mode. Byte enable high places the 3 Volt Intel StrataFlash memory in x16 mode. 1 AP-702 AP-702 This document assumes all other pins (e.g., Address, Data, etc.) are connected in such a way as to insure proper device functioning. All interfaces in this document use page-mode timings. Before 3 Volt Intel StrataFlash memory's page-mode timings can be used, Read Configuration Register bit 16 (RCR.16) must be set using the Set Read Configuration Register command. For more information on the RCR bits see the 3 Volt Intel® StrataFlashTM Memory:28F128J3A 28F128J3A, 28F640J3A 28F640J3A, 28F320J3A 28F320J3A datasheet. 3.0 Interfacing 3 Volt Intel® StrataFlashTM Memory to the StrongARM* SA-1100 SA-1100 at 190 MHz The SA-1100 SA-1100 microprocessor delivers a combination of high performance and low power that can be useful for emerging portable applications. The SA-1100 SA-1100 incorporates a 32-bit StrongARM* RISC processor core as well as an on-board memory controller. 3.1 Interface Considerations By setting up certain registers, a glueless interface is achieved between 3 Volt Intel StrataFlash memory and the StrongARM SA-1100 SA-1100. The interface described in this application note uses two 32-Mbit Intel StrataFlash memory components to match the 32-bit data bus of the SA-1100 SA-1100 (DE-S1100-Ex). All components can interface at 3.3 V. The SA-1100 SA-1100 runs from a 1.5 V power supply, and the 3 Volt Intel StrataFlash memory uses a 2.7 V to 3.6 V. Both can interface between 3.0 V and 3.6 V. RCR.16 should be set to enable page-mode before page-mode timings are used. Figure 1 is a block diagram of the glueless interface between the two 32-Mbit 3 Volt Intel StrataFlash memory devices and SA-1100 SA-1100. Figure 1. 3 Volt Intel® StrataFlashTM Memory/SA-1100 Interface 1.5 V VDD VDDX 3V 3V 3V VCC VCCQ D31:0 A23:2 A22:1 nOE OE# nWE WE# nCS0 SA-1100 SA-1100 DQ31:0 CE0 nCS1 ROM_SEL 3V 3V CE1 CE2 BYTE# nRESET 2 RP# 3 Volt Intel® StrataFlashTM Memory AP-702 AP-702 3.2 Processor Interface Signals The following are signal descriptions for the SA-1100 SA-1100 (DE-S1100-Ex version): A25:0: The 26-bit address bus transmits addresses to memory from the processor. nCS(3:0):Static chip selects. These signals are chip selects to static memory devices. nCS0 corresponds to address 0x00, which is where the boot device is expected to be. D31:0: The 32-bit data bus transfers data between the processor and memory. nOE: The Not (active-low) Output Enable indicates the memory output enable. nWE: The Not (active-low) Write Enable indicates to memory that writes are enabled. ROM_SEL: ROM Select. This pin is used to configure the ROM width. If it is grounded, the ROM width is 16 bits. If it is pulled high, the ROM width is 32 bits. 3.3 Control Signal Generation MSC1/MSC0 are SA-1100 SA-1100 memory control registers for configuring the interface to flash. Upon reset these values are forced to their slowest non-burst timings. Timing bits are specified as memory clock cycles. Memory clock cycles are half the rate of the internal CPU cycles. Each memory control register (MSC1/0) contains information for two memory regions as selected by CS3:0. MSC0 (Bits 31-16) control the CS1 memory region MSC0 (Bits 15-0) control the CS0 memory region MSC1 (Bits 31-16) control the CS3 memory region MSC1 (Bits 15-0) control the CS2 memory region The following table describes the 32 bits of the first MSC control register (in a 190 MHz SA-1100 SA-1100) as it relates to flash. 3 AP-702 AP-702 Table 1. SA-1100 SA-1100 Memory Control Register Table Bit Name 1­0 RTx[1:0] 2 RBWx Description 10 ­ Burst-of-four Flash 3 Volt Intel® StrataFlashTM Memory Read Region (CS0) Value (2242H 2242H) 3 Volt Intel StrataFlash Memory Write Region (CS1) Value (2642H 2642H) 10b = 2 decimal 10b = 2 decimal 0b = 0 0b = 0 01000b = 8 decimal 01000b = 8 decimal Flash Bus Width 0 ­ 32 bits 1 ­ 16 bits Flash Delay First Access 7­3 RDFx[4:0] This determines the read access time or first access of a burst flash. One memory clock cycle is added to this value. Read: Flash Delay Next Access (Page access) 12­8 RDNx[4:0] Number of memory clock cycles (minus 1) from address to data valid for subsequent accesses of a burst flash. 00010b = 2 decimal Write: Flash Write Pulse Width Low This determines the write pulse width when writing to flash. One memory clock cycle is added to this value. 15­13 RRRx[2:0] Flash Write Pulse Width High/ Write Recovery Before Read Write pulse width high and write recovery before read is 2*RRR + 1 memory cycle. 00110b = 6 decimal 001b = 1 decimal 001b = 1 decimal The parameter RDN is used for both the page-access time during reads and the flash write-pulsewidth-low time during writes. Because of this, read performance is impacted (read page access time becomes 74 ns) if the same memory region (e.g., CS0) is used for reading and writing to the flash. To work around this, the flash is read from one memory region (CS0) and written to in another region (CS1). The timings are optimized for each region thus improving read performance. Because of Intel StrataFlash memory's CE logic, no additional glue logic is required. To configure the 3 Volt Intel StrataFlash memory read region as shown in Figure 1, the MSC0[15:0] register should be set to a value of 2242H 2242H. Page mode read timing diagrams for a 190 MHz SA-1100 SA-1100 device are generated using this value. Figure 3 depicts this page-mode read timing diagram. To configure the 3 Volt Intel StrataFlash memory write region, the MCS1[15:0] register should be set to a value of 2642H 2642H. 4 AP-702 AP-702 Figure 2. 3 Volt Intel® StrataFlashTM Memory and SA-1100 SA-1100 at 190 MHz Page Mode Read Timing Diagram (CS0 Memory Region) Memory Clock RDF + 1.5 = 100ns nCS0 RDF + 1 = 95ns A[25:5] A[4] RDN +1 A[3:2] RDN +1 1 0 32ns 2 3 32ns 32ns 1 0 RDN +1 2 3 nOE D0 D1 D2 D3 D4 D5 D6 D7 Read (Input) Data Figure 3. 3 Volt Intel® StrataFlashTM Memory and SA-1100 SA-1100 at 190 MHz Page Mode Read Timing Diagram (CS1 Memory Region) . . CPU Clock Memory Clock . . tAS tCEH 2*RRR + 1 tAS tCEH 2*RRR + 1 tAS nCS1 tAH tASW A[25:0] tAH tASW A0 A1 tCES tDSWH RDN + 1 tCES tCES RDN + 1 nWE nOE D[31:0] tDH D0 D1 5 AP-702 AP-702 The following is a table of write timing values generated by the SA-1100 SA-1100 at 190 MHz and the corresponding 3 Volt Intel StrataFlash memory minimum specification requirement. Table 2. SA-1100 SA-1100 Variable Write Timing Table SA-1100 SA-1100 Description SA-1100 SA-1100 at 190 MHz Values 3 Volt Intel® StrataFlashTM Memory Variable 3 Volt Intel StrataFlash Memory Description 3 Volt Intel StrataFlash Memory Min. Spec. Requirement nCS setup to nWE low (4 CPU cycles) 21 ns tELWL CEx low to WE# going low 0 ns Write pulse width (2*RDN + 2 CPU cycles) 74 ns tWP Write pulse width 70 ns tDSWH Write data setup to nWE high (2*RDN + 3 CPU cycles) 79 ns tDVWH Data setup to WE# going high 50 ns tAS Address setup to nCS low (1 CPU cycle) 5 ns NA tASW Address setup to nWE low (5 CPU cycles) 26 ns NA (tAS + tDSWH) 100 ns tAVWH Address setup to WE# going high 50 ns tCES tCEH nCS held asserted after nWE deasserted (2 CPU cycles) 11 ns tWHEH CEx hold from WE# high 10 ns tDH Data hold after nWE high (3 CPU cycles) 16 ns tWHDX Data hold from WE# high 0 ns tAH Address hold after nWE deasserted (3 CPU cycles) 16 ns tWHAX Address hold from WE# high 0 ns (tCES + 4*RRR+2 + tCEH CPU cycles) 63 ns tWPH Write pulse width high 30 ns (tCEH + 4*RRR+2 CPU cycles) 42 ns tWHGL Write recovery before read 35 ns NOTE: All the 3 Volt Intel StrataFlash memory write parameter minimum requirements were met by the SA-1100 SA-1100. If a reset occurs when a block erase, program, or lock-bit configuration operation is taking place, RP# must remain low for a time of tPLPH (35 µs). This is significantly less than the time the SA1100 SA1100 requires nRESET to be held active (150 ms). Therefore, this should not be a concern if RP# is connected to nRESET. After reset, the 3 Volt Intel StrataFlash component has a minimum requirement of 310 ns (tPHQV + tPHRH) between RP# going high to valid data. After power-on or hard reset, the SA-1100 SA-1100 configures the static interface for the boot flash (connected to CS0) for the slowest non-burst flash (RDF=0x1FH). For the 190 MHz device, the first access occurs 342 ns after nRESET goes high. This exceeds the required minimum time of the 3 Volt Intel StrataFlash memory device. For faster versions of the SA-1100 SA-1100 that do not meet this requirement, a delay should be inserted. Reference AP-617 AP-617 Additional Flash Data Protection Using VPP, RP#, and WP# for details about CPU reset and RESET# timing. Whenever the 3 Volt Intel StrataFlash memory comes out of reset/power down, RCR.16 must be set to enable page-mode. 6 AP-702 AP-702 The following is a table of reset timing values for the SA-1100 SA-1100 at 190 MHz and the corresponding 3 Volt Intel StrataFlash memory minimum spec. requirement. Table 3. SA-1100 SA-1100 Variable Read Timing Table SA-1100 SA-1100 Description nRESET pulse width (min. requirement) SA-1100 SA-1100 at 190 MHz Values 3 Volt Intel StrataFlash Memory Description 3 Volt Intel StrataFlash Memory Min. Spec. Requirement RP# pulse low time 35 µs RP# high to reset during erase, program, or lockbit configuration 100 ns tPHQV 342 ns tPLPH tPHRH Flash delay first access after nRESET goes high (32.5 memory cycles) 150 ms 3 Volt Intel® StrataFlashTM Memory Variable Reset to output delay 210 ns tPHRH + tPHQV 310 ns NOTE: All the 3 Volt Intel StrataFlash memory reset parameter minimum requirements were met. Consult the appropriate datasheets for specific information about the individual components in the interface (see Appendix A for a list of additional information). 3.4 SA1100 SA1100 with DRAM Interface on the System When an SA1100 SA1100 is controlling DRAM in a system, it cannot use the asynchronous page-mode interface for flash in that same system. Flash and DRAM can co-exist in an SA1100 SA1100 system only by using a non page-mode asynchronous interface to the flash. This limitation results from the SA1100 SA1100 bus interface unit which deasserts flash's CE, while inserting refresh cycle in the middle of the page-mode access. It re-asserts CE to finish the page but does not meet (tELQV) flash requirement. It will not have this problem if the system does not use DRAM, because refresh cycles would not be interrupting flash reads. The following errata is published in the SA-1100 SA-1100 Specification Update document: 3.4.1 DRAM Refresh Corrupting ROM Burst of 4/8 Timing Asynchronous DRAM refreshes are allowed to interrupt burst transfers to any static, asynchronous RAM between 32-bit transfers. This works properly when any of those memory types are configured for non-burst timings (MSCx:RTx = 0 or 1). But, when flash is configured for burst timings (MSCx:RTx = 2 or 3), burst-of-4/8 aligned addresses may erroneously use the burst access time, tAPA (MSCx:RDNx) rather than the intended non-burst access time, (tELQV: tAVQV) and (MSCx:RDFx). This happens whenever the refresh request (internally generated) occurs just prior to a burst-of-4/8 unaligned address. The problem will affect burst-of-4 timings on either 16-bit or 32-bit data busses, or burst-of-8 timings on 16-bit data busses. The suggested workaround is to use non-burst timing (MSCx:RTx = 0) for flash as shown in Figure 4. 7 AP-702 AP-702 Figure 4. 3 Volt Intel® StrataFlashTM Memory and SA-1100 SA-1100 in Non-Burst Timing Mode Mem. Clock nCS0/CE0# RDF+2 RDF+1 RDF+1 RDF+1 A[25:0] nOE/OE# R3 R2 D[31:0] nWE/WE# 4.0 Summary 3 Volt Intel StrataFlash memory devices provide 2X the bits in 1X the space. These devices provide reliable two-bit-per-cell storage technology. Faster performance can be enabled by setting RCR bit 16 to enable page-mode reads. Interfaces between 3 Volt Intel StrataFlash components and various processors can generally be accomplished with a PLD to generate wait-states and WE#, and a decoder to generate chip enable signals. 3 Volt Intel StrataFlash memory devices are able to have different I/O voltages by using different VCCQ voltages. 3 Volt Intel StrataFlash memory components come in a variety of different packages and densities for increased flexibility. 3 Volt Intel StrataFlash memory is an excellent option for code and data applications where high density and low cost are required. 8 AP-702 AP-702 Appendix A Additional Information Order Number Document/Tool ® 290667 Intel StrataFlashTM Memory; 28F128J3A 28F128J3A, 28F640J3A 28F640J3A, 38F320J3A 38F320J3A datasheet 298130 Intel® StrataFlashTM Memory; 28F128J3A 28F128J3A, 28F640J3A 28F640J3A, 38F320J3A 38F320J3A Specification Update 297859 AP-677 AP-677 Intel® StrataFlashTM Memory Technology 292222 AP-664 AP-664 Designing Intel® StrataFlashTM Memory into Intel® Architecture 292221 AP-663 AP-663 Using the Intel® StrataFlashTM Memory Write Buffer 292218 AP-660 AP-660 Migration Guide to 3 Volt Intel® StrataFlashTM Memory 292204 AP-646 AP-646 Common Flash Interface (CFI) and Command Sets 292172 AP-617 AP-617 Additional Flash Data Protection Using V PP, RP#, and WP# NOTES: 1. Please call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International customers should contact their local Intel or distribution sales office. 2. Visit Intel's World Wide Web home page at http://www.intel.com for technical documentation and tools. 3. For the most current information on Intel StrataFlash memory, visit our website at http://developer.intel.com/ design/flash/isf. 9